ASTEADILY increasing demand for power has recently led

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1 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY Reliability Analysis and Modeling of Power MOSFETs in the 42-V-PowerNet Alberto Castellazzi, Member, IEEE, York C. Gerstenmaier, Rainer Kraus, and Gerhard K. M. Wachutka, Member, IEEE Abstract This paper analyzes the operation of PowerMOS- FETs in the 42-V-PowerNet and shows that very stressful conditions are encountered, which can lead to severe reliability problems. To enable thorough investigations by circuit simulations an accurate physics-based compact model of the devices is proposed: it includes all important electrothermal effects relevant to the description of the observed failure mechanisms. By means of an advanced thermal-modeling approach, multichip assemblies can be accurately described, including mutual heating effects between neighboring devices. Some properly chosen examples demonstrate the validity of the model and its usefulness for reliability investigations. Index Terms Electrothermal effects, modeling, power metal-oxide semiconductor field-effect transistors (MOSFETs), reliability. NOMENCLATURE Diffusion coefficient of electrons cm s. Depth of the body region [cm]. Band-gap energy [J]. Base current [A]. Breakdown current [A]. Breakdown current parameter [A] [A]. Collector current [A]. Transport-current density Acm. Boltzmann s constant JK. Acceptor concentration cm. Intrinsic carrier density cm. Elementary charge [C]. Cross section of the body-region cm. Junction temperature [K]. Reference temperature (300 K) [K]. Breakdown voltage [V]. 300 K Manuscript received March 8, 2005; revised October 26, Recommended by Associate Editor J. Shen. A. Castellazi is with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich 8092, Switzerland ( castellazzi@iis.ee.ethz. ch). Y. C. Gerstenmaier is with Siemens AG, Corporate Technology, Munich 81730, Germany. R. Kraus is with the Institute of Electronics, University of Bundeswehr, Neubiberg 85577, Germany. G. K. M. Wachutka is with the Institute for Physics of Electrotechnology, Munich University of Technology, Munich 80333, Germany. Digital Object Identifier /TPEL Breakdown voltage at Threshold voltage [V]. Threshold voltage at BJT current gain. 300 K [V]. 300 K [V]. Thermal coefficient of the breakdown voltage. Thermal coefficient of the threshold voltage. Mobility of the charge carriers at cm V s. Electron mobility cm V s. Hole mobility cm V s. 300 K I. INTRODUCTION ASTEADILY increasing demand for power has recently led to a review of the hitherto-adopted philosophy for the generation and distribution of electrical energy in automobiles, that resulted, among others, in the introduction of the 42-V-PowerNet [1]. At the heart of this novel concept is the integrated starter generator (ISG): a single motor (typically a three-phase asynchronous machine) carries out the dual function of providing the required torque for the combustion engine at start-up or hybrid drive operation and of generating electrical power after the engine has been started. For that to be possible, bidirectional power transfer capability between the motor and the batteries must be ensured. That implies the presence of an ac dc converter between the motor and the 42-V power source and of a dc dc converter between the 42-V and 14-V sides (the presence of loads supplied at 14-V is still foreseen in the first generation of the 42-V-PowerNet). With the term ISG reference is usually made to a whole system as schematically depicted in Fig. 1, which also indicates the extensive presence of additional switches, used for power-management functions toward the loads or between the batteries and the distributed energy reservoirs (Super-caps and dc-link capacitor). Because of their advantageous features as compared with other devices (e.g., possibility to take advantage of the intrinsic body-diode, ease of parallelability) -channel low-voltage Power metal-oxide semiconductor field-effect transistors (MOSFETs) are mainly chosen for use within the ISG circuitry, both as high-frequency switches, in the power converters, and as linear regulators, in the other positions. In an effort to achieve optimum power-density figures, while coping with the cost restrictions of the automotive market, the transistors are exposed to very stressful conditions. These range from the fast and snubberless repetitive switching of considerable current levels, which results in avalanche breakdown of the device even for low values of parasitic inductance, to the repetitive /$ IEEE

2 604 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006 Fig. 1. Schematic representation of the ISG in the 42 V-PowerNet. dissipation of considerable amounts of energy in short circuit or linear operation (i.e., in the saturation region of the device characteristics). With specified ambient temperatures ranging between 40 C and 140 C, [2], values well in excess of 200 C can be measured on the silicon chips during transient operation. The consequence, in some cases, is a severe degradation of the original properties of the transistors. An application-oriented investigation for performance and reliability is necessary to optimize the system design and achieve its safe operation. Experiments alone are not sufficient, since it is difficult to test all possible conditions and effects inside the devices are not visible. The availability of a complete and accurate, while simple and versatile, physics-based compact model of the devices becomes paramount. Fig. 2. Basic cell of the powermosfet. Some intrinsic components are evidenced in particular. The indications for the electrical variables refer to the reverse-recovery of the body-diode. II. OPERATIONAL CONDITIONS AND FAILURE MECHANISMS A. High-Frequency Operation Fig. 2 depicts the basic cell of an -channel vertical MOSFET, indicating in particular those intrinsic components which are of critical importance in the interpretation of the nonideal behavior of the device. As indicated the structure between source and drain corresponds to a power diode,, usually referred to as the body or drain-source diode of the device. Within the power conversion circuitry, the transistors are used as high-frequency switches in half-bridge cells switching inductive loads, as schematized in Fig. 3: high-side MOSFET (HSM), low-side MOSFET (LSM) and the load is represented as a current-source. According to the direction of power transfer, one transistor acts as the control (or active) switch and the other one as the rectifier (in the example of Fig. 3, for instance, the LSM acts as rectifier). During the off-state of the active MOSFET, a voltage significantly higher than the threshold level is applied between the gate and source terminals of the rectifying one to turn it on. So, the channel forms, offering the smallest impedance path for the load current, which flows entirely through it. This practice, referred to as active (or synchronous) rectification, is well known and is commonly adopted in modern power conversion circuitry. However, to avoid short-circuiting of the power source to ground, a dead-time is inserted between turn-off of one switch and turn-on of the other one. During these dead-times, the Fig. 3. Schematic representation of a half-bridge cell switching an inductive load. body-diode of the rectifier is used as a freewheeling element for the load current. The n p n n -structure in Fig. 2, corresponding to the reverse series connection of and, actually represents a parasitic bipolar transistor, indicated as BJT in the following. and are typically regarded as the base-emitter and basecollector junctions, respectively.,, and indicate the drain-source, drain-gate, and gate-body capacitance, respectively. is the (parasitic) gate resistance and the resistance of the p -body. When conducts, is slightly reverse-biased by the voltage drop across. The BJT is in the reverse-active bias mode, with the n n -drain-region actually acting as an emitter and the n -source-region as a collector. Under this bias condition a collector-emitter current also flows. Because of the shorts provided by the source metallization between the n and p regions of the source (i.e., emitter and base of the BJT in the forward-active bias) and because of the relative thickness of the p region (i.e., the base of the BJT), the current gain of the intrinsic BJT is typically rather small; in the reverse-active bias, too, the gain is low, with the ratio between and amounting to few units. When the control switch in the half-bridge cell is turned on, a positive voltage drop falls from drain to source of the rectifier, that is across the collector-base junction of the BJT. During

3 CASTELLAZZI et al.: RELIABILITY ANALYSIS AND MODELING OF POWER MOSFETs 605 Fig. 4. Measured reverse-recovery current waveforms for different speeds of the switching-transition. The measured device is a 75-V80-A avalanche-rated MOSFET. conduction in the reverse-active bias mode, charge is stored within this junction and it must be removed in order to recover its reverse-blocking capability. The process of extracting the excess charge in a reasonably short time is inevitably associated with the appearance of reverse current peaks, referred to in the literature as reverse-recovery current of the body-diode, [3]. When the drain current becomes zero (and then negative), the drain-source voltage,, of the rectifier starts rising and so does the drain-gate voltage,. The p n junction is reverse biased and a positive voltage drop falls across the p n junction as a result of the current flowing through. If this voltage drop becomes high-enough to forward bias the p n junction, then activation of the parasitic BJT takes place. The investigations of [4] have shown that a major role in the activation of the BJT is played by the current flowing through when the drain potential rises. As indicated in Fig. 2, this current also flows through, which is connected in series with it. This causes the appearance of a voltage drop across the gate and source terminals of the device. Being connected in parallel to the gate-source capacitance must charge up to the same voltage level. This capacitance is made up of a component,, not shown in Fig. 2, resulting from the overlapping of the gate oxide with the source metallization and another component, in Fig. 2, which is associated with the overlapping of the gate oxide with the p-well structure. The latter is typically not included in the compact models of PowerMOSFETs. Nevertheless it is crucial in the activation of the parasitic BJT, since it is directly connected to its base. So, part of the current through it takes the path represented by and part is directly injected into the p n base-emitter junction of the BJT, enhancing the probability for it to turn on. Once the BJT has turned on, current flows from the collector toward the emitter (i.e., drain and source of the rectifier). Because of the positive temperature coefficient of the collector-emitter current, current-crowding phenomena with localized overheating are likely to take place. If temperatures in excess of a given value are reached, the BJT enters a self-sustaining thermal runaway regime, [5], leading to the failure of the PowerMOSFET. Fig. 4 shows the drain-current of the HSM in a half-bridge cell when used as the control switch, for two different transition Fig. 5. Transfer characteristics of a low-voltage PowerMOSFET measured at two different temperature values. speeds. The turn-on current of the HSM reflects the reverse-recovery current of the body-diode of the LSM. The dashed line indicates a safe reverse-recovery; as the switching-time decreases the current is seen to diverge (full line in Fig. 4) quickly leading to the destruction of the transistor. The minimum voltage which needs to be applied in order for the diode to conduct becomes smaller as the temperature increases, whereas the value of increases with temperature; so, the probability for the parasitic BJT to turn on also increases with temperature. Even in the case of safe reverse-recovery, the overlapping of the high recovery current peaks with the drain-source voltage is responsible for considerable power losses (in both switches of the half-bridge). Moreover, with values of up to 1 A/ns, the parasitic inductance causes major deviations from the ideal switching behavior of the device, resulting in degradation of performance [6], [7]. B. Linear and Short-Circuit Operation When used as interfaces toward the loads or between the batteries and the capacitors the transistors are basically required to perform limiting and protective functions. This is the case, for example, in the frequent load-dumping action, in which they are used to dissipate, in a controlled manner, the energy contained in an inductive load. In this case, the gate-source voltage is made a function of the variable to be controlled and can span all over the range of allowed values. This is referred to as linear operation here. For relatively high values of MOSFETs exhibit a negative temperature coefficient of the drain current: that is, an increase in temperature causes a decrease of the drain current, as a result of the diminishment with temperature of the carriers mobility. At lower values of, however, the decrease of with temperature prevails, resulting in a positive temperature coefficient of the drain current. Fig. 5, which reports the transfer-characteristics of a PowerMOSFET measured at two different temperature values, summarizes such behavior. The transition between the two operational regions is referred to as the point of zero temperature coefficient (ZTC in Fig. 5) [8]. Since some hundred thousand cells are connected in parallel to make up a PowerMOSFET, operation of the transistor left of the ZTC is thermally unstable. In the transient regime, current crowding takes place, leading to the formation of hot-

4 606 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006 Fig. 7. Measured current and temperature waveforms for the MOSFET driven in short-circuit. Fig. 6. (a) Temperature increase at three different locations of a Power- MOSFET chip surface: the device is driven with constant Vgs and Vds in conditions of thermal instability. (b) Photograph of the device with an indication of the points of measurement. spots and temperature gradients within the chip. Whereas for high-voltage devices and older technologies thermally unstable behavior was typically confined to a region of negligible interest for most application purposes, recent investigations have shown that this range broadens for reduced channel length [8]. For that reason, operation as linear regulators is particularly critical for low-voltage devices of modern generation, such as the ones used within the 42-V-PowerNet. Fig. 6(a) reports the temperature measured on different locations of the chip surface as a response to a power pulse of 5 ms, with constant and constant applied. The transistor is driven in the thermally unstable region of operation. As the current distribution becomes more and more inhomogeneous, very high temperature values can be reached at some chip locations, while considerable gradients also come into being, as anticipated. A photograph of the device with an indication of the points of measurement is provided in Fig. 6(b). These results were obtained measuring the thermal power radiated at the surface by means of an optical fiber connected to an infrared sensor, as described in more detail in [9]. Due to the space resolution of the equipment, all temperature profiles presented here correspond to an average value over many cells, so that even higher values can be realistically assumed for some of them. This can result in degradation of the materials making up the transistor (e.g., local melting of the aluminum used for the source-metallization). Since specifications about the safe operation of the devices usually assume uniform power distribution, unexpected failures can occur. Examples of typical failures for this operational mode are discussed in [10]. For a safe operation of the transistors in the thermally unstable region of operation it becomes very important to properly control the gate-source voltage: critical variables such as device temperature need to be sensed and their values taken into account in driving the devices. If this is not possible a safety margin must be observed: the device operation must be sufficiently below the critical values of current and drain voltage to avoid dangerous conditions. If a full (i.e., significantly higher than the threshold voltage) is used to drive the transistor with a given applied, the resulting condition can be referred to as short-circuit, in virtue of the small impedance shown by the MOSFET. In conjunction with many applications within the the 42-V-PowerNet (e.g., in lamp-ballasts), the transistors must be able to withstand such operational mode for some time before turning-off. Fig. 7 shows a measurement of the drain-current and of the temperature increase at one location of the chip surface for the device driven in short-circuit. The pulse-width is about 450 s here. In the initial portion of the pulse the self-protecting behavior resulting from the negative temperature coefficient of the drain-current, as discussed above, can be recognized; however, as the junction temperature of the device increases, current tails appear at turn-off. As the temperature further increases, a point is reached where the device can no longer be turned off and fails. In the application, the turn-off command comes in many cases from a temperature sensor. Since it is quite difficult to determine the location of maximum temperature, it is also difficult to prevent the device from reaching excessive values. And that, just as in the case considered above, leads to severe material degradation and eventually to failure of the device. A typical example for short-circuit operation is visible in Fig. 8. In linear and short-circuit operation too, a central role for the failure of the device is played by the activation of the parasitic BJT. In these cases, however, that is due to thermal generation of carriers, that is, to a different mechanism as compared with the case of high-frequency switching. More precisely, the situation

5 CASTELLAZZI et al.: RELIABILITY ANALYSIS AND MODELING OF POWER MOSFETs 607 As emerging from the results presented above, the analysis for reliability requires a device model descriptive of: the parasitic BJT structure, including the reverse-recovery and breakdown current of the body-diode, and the resistance of the body region, ; the gate-body capacitance,, associated with the overlapping of the gate with the body; packaging related effects, such as the voltage drops caused by the parasitic source inductance and the gate resistance. 1) Intrinsic BJT: The collector current as a function of the base-emitter,, and base-collector voltage,, is described by (1) where is a constant multiplication factor accounting for the active device area. can be approximated as Fig. 8. Photograph of a PowerMOSFET failed in short-circuit operation. The device is a 75 V 80 A-rated transistor in TO-220 package. (2) with (3) For the intrinsic carrier-density, which mainly determines the temperature dependence of the collector current, the equation is used as given in [11] (4) Fig. 9. Schematic representation of the effect of a positive drain-source voltage on the activation of the parasitic BJT. is a constant and the temperature dependence of the band-gap energy is modeled according to [12] as depicted in Fig. 9 applies when the device is operated with a positive. An electron current flows through the channel. However, a space-charge layer exists between drain and source and the electrical field in this layer accelerates the thermally generated electron-hole pairs in opposite directions. The resulting current flows into the p -body region of the device. Thus, with relevance to Fig. 2, it can cause the appearance of a positive voltage drop across, leading to the activation of the parasitic BJT. This current increases with temperature. As already pointed out, also increases with temperature, while the minimum voltage drop required to cause the base-emitter junction to inject reduces. Therefore, in this case too, the probability for the parasitic BJT to be activated increases with temperature. A. Electrical Aspects III. MODELING TASK where and are characteristic constants of the considered material. Their value for silicon is given in [12]. The base current is related to the collector current by the current gain of the transistor (i.e., ) which can be determined, for example, by means of device simulation. The dynamic behavior of the body-diode is modeled according to the approach of [13]. The reverse-recovery current associated with the removal of the diode charge can be described by (5) with (6) The diode charge is obtained with the help of a small subcircuit [13]. is the static component of the diode forward current; the static time-constant represents the lifetime of the charge carriers. is a dynamic time-constant which can be regarded as a fitting parameter.

6 608 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006 Fig. 10. Basic scheme of a charge-modeled capacitance. For the breakdown current of the body-diode the empirical relation can be written as where is a constant., on the other hand, is temperaturedependent and can be described by The resistance associated with the body-region (i.e., the base of the parasitic BJT) can be described approximately as 2) Gate-Body Capacitance: The charge-model is applied to the description of the voltage dependent capacitance. As shown in Fig. 10, a capacitor of fixed value,, is connected in series with a controlled voltage source, whose value is a function of the voltage applied at the device terminals,. The resulting equivalent capacitance is: (7) (8) (9) (10) is the portion of the gate-source capacitance associated with the overlapping of the gate electrode with the body. For values of the voltage across it below threshold, influences the accumulation or depletion of charge in the -region. Furthermore, as pointed out above, it can lead to dynamic injection of carriers into the base-emitter junction of the parasitic BJT. When the channel is formed above threshold, on the other hand, is connected in parallel to and, both of much greater value, and it is also no longer effective onto the parasitic BJT turn-on. Consequently, it is modeled as where is a constant. Defining as (11) yields the desired behavior. in (13) is a constant parameter which controls the abruptness of the transition between the conditions and. The capacitance depends not only on ; it is also influenced by. The value of determines whether the drain region below the gate is in accumulation or depletion, resulting in a constant gate-oxide or the series connection of oxide and variable depletion capacitance, respectively. The drain region below the gate (the -epitaxial region) is surrounded by -junctions with depletion layers controlled by. Therefore the value of is not exactly determined by the whole gate width; an effective area, depending on the drain-source voltage, must be considered instead. is described using the conventional expression for the junction capacitance [12]. For the channel current standard equations including the description of short-channel effects were used [14]. 3) Package Related Effects: The model is completed with the inclusion of the package description, that is with the parasitic inductance and resistance of the pins and bondwires. The model so developed was calibrated and validated statically, dynamically, and against changes in ambient temperature. Fig. 11 presents three comparisons of simulated to measured data, selected to demonstrate the validity of the model. A brief description of each graph is provided in the caption to the figure. B. Thermal Aspects In accordance with common practice, the modeling of the thermal impedance associated with a single transistor can be performed analytically or experimentally [15], [16] [alternatively, use can be also made of simulation, e.g., with the finite element method (FEM)]. However, to allow also for fast and fully self consistent electrothermal simulation of multichip power modules over longer time intervals, the electrical model of the MOSFETs is coupled here with a novel and advanced transient thermal model, presented in detail in [17] and [18]. According to this model, the thermal evolution of each chip within the system can be described by means of a thermal equivalent network as drawn in Fig. 12. All the thermal resistors have unit value, while the thermal capacitors are attributed the values of effective time-constants, 1. is the number of blocks chosen to approximate the thermal response (thermal impedance) of the system. The effective time constants are a small set of 8 to 20 approximately logarithmically distributed numbers, which replace the infinite set of usually unknown exact time constants as explained in [17] and [18]. The range of the is between 10 s and 1000 s for typical module sizes. Apart from this, there is a large amount of arbitrariness in defining the. Different sets of will do equally well in providing a very accurate approximation of the thermal impedances. As has been pointed out in [17] and [18], the temperature evolution at an arbitrary location in the set-up, usually chosen at the center of the chip heat sources, can be expressed as (12) (13)

7 CASTELLAZZI et al.: RELIABILITY ANALYSIS AND MODELING OF POWER MOSFETs 609 Fig. 11. Comparison of experimental and simulation results for model validation: (a) output characteristics of the PowerMOSFET, (b) body-diode reverse-recovery current (Irr), and (c) body-diode output characteristics at three different temperature values. Fig. 12. Thermal equivalent circuit for chip temperature T including heating of neighboring chips by sources P according to (14). with the generalized heat sources (i.e., the current sources in the equivalent circuit of Fig. 12) defined by (14) Here, is a function describing the power dissipated by the heat source (chip). The dissipated power depends in the general electro-thermal case on the local temperature, since the electrical device behavior is dependent on. is the number of chips in the module. in Fig. 12 denotes a constant external reference temperature usually chosen to be zero. The coefficients are obtained by linear least square fits to FEM-simulated heating curves (e.g., with [19]). Once the model matrices are established for all locations of interest, the thermal evolution at these locations can be calculated swiftly with the help of a circuit simulator (e.g., PSpice, Saber, Simplorer). The advantage of this thermal network is its invariance concerning the number of thermal heat sources and thermal ports (thermal contact areas), which only influences the modified heat sources (14). Other advantages of the circuit are the small size (for small ), simplicity and, perhaps most important, simple parameter determination for, as discussed above. Together with the electric model and circuit, which provides the dissipated powers of the devices by multiplication of load currents and voltages, a full electrothermal simulation of an electronic set-up can be performed. In [18], the thermal model has been extended to include the effects of varying surface or ambient temperature and varying heat flows at the thermal contact areas. The thermal model thus is valid for all boundary conditions applied at the thermal contact areas. The same circuit as in Fig. 12 can be used for the extended model with the modified heat sources (14) then including additional terms for the sources, for varying ambient temperature and surface heat flows in addition to the chip heat sources. IV. SIMULATION RESULTS As an application example, a full electrothermal simulation of a multichip-module for the bidirectional dc dc converter of the ISG was performed. A three-phase buck converter was considered [20], [21]. Fig. 13 shows the temperature evolution of the HSM and of the LSM (working as the active switch and as the rectifier, respectively) in one of the half-bridges of the six-chip module. The switching instances can clearly be read off from the temperature evolution. The on-state losses between turn-on

8 610 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006 Fig. 13. Electrothermal simulation result for chip temperatures in dc dc-converter operating at 170 khz. Fig. 15. Simulated short-circuit drain-currents for different values of drainsource voltage. Fig. 14. Temperature increase for two MOSFETS of the dc dc-converter in short circuit operation. The HSM is in permanent on-state and the LSM in offstate. and turn-off correspond to an average device current of 50 A. The converter operating frequency amounts to 170 khz, with switching times of less than 200 ns. In particular, the applied thermal-model accounts for the interaction of different chips, which is demonstrated by the example of an overload condition at the output of the converter. In order to maintain a constant output voltage the converter works with its highest duty ratio, i.e., the HSMs are nearly constantly turned on and the LSMs turned off. Fig. 14 reports the resulting temperature evolution in the two MOSFETs. Although the losses in the LSM are negligible, its temperature rise is noticeable (14 C in 2 s) due to the power dissipated in the neighboring HSM. The results of the simulations above can serve as input data (i.e., initial conditions) for subsequent investigations on a shorter time-scale, of the sort discussed in Section II. For example, Fig. 15 shows the short-circuit drain current, for a simulation with a pulse width of 500 s and three slightly different values of drain-source voltage, leading to different maximum temperature levels at the end of the pulse. As can be seen, the current tails at turn-off, as also experimentally observed (see Fig. 7), and the eventual failure of the device, could be reconstructed. As another example, the device behavior in the thermally unstable portion of its transfer characteristic (see Fig. 5) was investigated. In view of the nature of the problem, a parametric modeling concept was applied here, with the chip considered Fig. 16. Simulated drain current of three parallel MOSFET cells for the transistor driven in thermal instability. Vdsand Vgsare constant. as made up of a number of elementary cells, each described by the same model, properly scaled. This allows for a comfortable analysis of how parameter mismatches between parallel cells influence the device behavior. The results of a simulation carried out with three parallel cells are given in Fig. 16. Each cell has a slightly different value of threshold-voltage and thermal impedance, as is the case in a real device. More precisely, Cell 3 has the highest as well as the highest thermal-resistance. The resulting drain-currents show that the model is descriptive of the formation of hot-spots. In this case, too, pn-leakage and BJT-current are thermally generated and, due to their positive temperature coefficients, contribute to the unstable behavior of the device. One last example concerns the activation of the parasitic BJT due to the reverse-recovery of the body-diode of the LSM (Section II-A). A simulation result for this failure mode is presented in Fig. 17 and can be directly compared with the measurements of Fig. 4. V. CONCLUSION Novel automotive applications have significantly extended the spectrum of working conditions for PowerMOSFETs. Although some of the failure mechanisms had been already investigated in the past for high-voltage transistors, no thorough char-

9 CASTELLAZZI et al.: RELIABILITY ANALYSIS AND MODELING OF POWER MOSFETs 611 Fig. 17. Simulated drain current for the fast-switching failure of the transistor due to activation of the parasitic BJT. acterization exists for low-voltage devices, for which quite different conditions apply. In particular, no comprehensive model suitable for inclusion in circuit simulation and reliability analysis had been provided yet. The compact-model developed in this work is descriptive of all significant effects, thus enabling an accurate and straightforward assessment of the importance of the most diverse device characteristics, from physical parameters to package parasitics, under any operational condition. Furthermore, the thermal modeling concept applied allows for the realistic analysis of multichip modules, as are commonly found in the 42-V-PowerNet. REFERENCES [1] J. G. Kassakian, Automotive electrical systems the power electronics market of the future, in Proc. 15th Annu. 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Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, [15] S. Clemente, Transient thermal response of power semiconductors to short power pulses, IEEE Trans. Power Electron., vol. 8, no. 4, pp , Oct [16] P. E. Bagnoli, C. Casarosa, M. Ciampi, and E. Dallago, Thermal resistance analysis by induced transient (TRAIT) method for power electronic devices thermal characterization part I: fundamentals and theory, IEEE Trans. Power Electron., vol. 13, no. 6, pp , Oct [17] Y. C. Gerstenmaier and G. Wachutka, Efficient calculation of transient temperature fields responding to fast changing heatsources over long duration in power electronic systems, IEEE Trans. Comp. Packag. Technol., vol. 27, no. 1, pp , Mar [18] Y. C. Gerstenmaier, A. Castellazzi, and G. Wachutka, Electro-thermal simulation of multi-chip-modules with novel transient thermal model, in Proc. IEEE THERMINIC, Sophia Antipolis, France, Sep. 2004, pp [19] Ansys, Inc., User Manual [20] A. Consoli, G. Scarcella, A. Testa, and G. Catona, Comparative investigation on standard and multiphase buck converters for automotive applications, in Proc. Eur. Conf. Power Electron. Appl. (EPE), Sep. 2003, [CD ROM]. [21] M. Gerber, J. A. Ferreira, L. W. Hofsajer, and N. Seliger, High density packaging of the passive components in an automotive dc dc converter, in Proc. IEEE PESC 05, Mar. 2005, vol. 20, no. 2, pp Alberto Castellazzi (M 04) was born in Treviglio, Italy, in He received the M.S. degree in physics from the University of Milan, Milan, Italy, in 1998 and the PhD degree in electrical engineering from the Munich University of Technology, Munich, Germany, in From 1998 to 2000, he was with Carlo Gavazzi Space, Milan, as a Designer of dc dc converters for space applications. In 2000, he joined the Power Electronics Department, Siemens Corporate Technology, Munich, studying the reliability of PowerMOSFETs in novel automotive applications. In 2004 and 2005, he was a Research Scientist with the Institute for Physics of Electrotechnology, Munich University of Technology, where he was mainly involved in 2 D electrothermal device simulation. Since January 2006, he has been with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, and the Power Electronics Associated Research Laboratory (PEARL) of ALSTOM-Transportation, Semeac, France, working on IGBTs for traction applications. His research interests are dc dc converters, electrothermal device simulation and investigation of power reliability. Dr. Castellazzi is a member of the IEEE Power Electronics Society, the IEEE Electron Devices Society, and the European Power Electronics Association. York C. Gerstenmaier received the M.S. and Ph.D. degrees in physics from the University of Bonn, Bonn, Germany. His doctoral research was in the area of quantum mechanical many-body theory. In 1987, he joined the Power Electronics Department, Siemens Corporate Technology, Munich, Germany. Since then he has been involved in the development of power electronic components and systems, modeling tools, and simulation. He has authored more than 40 scientific publications. Currently, he is concerned with thermal and electrothermal modeling and development of power electronic systems. Dr. Gerstenmaier is a member of the THERMINIC Programme Committee.

10 612 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006 Rainer Kraus was born in Lauingen, Germany. He received the Dipl.-Phys. degree from the University of Munich, Munich, Germany, in 1982, and the Ph.D. degree in electrical engineering from the University of Bundeswehr Munich, Neubiberg, Germany, in Since 1984, he has been with the Institute of Electronics, University of Bundeswehr Munich, as a Researcher and, since 1992, also as a Lecturer. From 1984 to 1990, he worked on design and analysis of DRAM and SRAM circuits in cooperation with Siemens Semiconductors, Memory Products (now Infineon Technologies), Munich. Since 1990, he has been engaged in the analysis and modeling of power semiconductor devices in cooperation with Siemens, Corporate Technology. His main present research interest is in the design of RF circuits in CMOS technologies. Gerhard K. M. Wachutka (M 90) received the D.Sc. degree from the Ludwig-Maximilians-Universität, Munich, Germany, in From 1985 to 1988, he was with Siemens Corporate Research and Development, Munich, where he headed a modeling group active in the development of modern high-power semiconductor devices. In 1989, he joined the Fritz-Haber-Institute of the Max-Planck-Society, Berlin, Germany, where he worked in the field of theoretical solid-state physics. From 1990 to 1994, he was head of the Microtransducers Modeling and Characterization Group, Physical Electronics Laboratory, Swiss Federal Institute of Technology (ETH), Zürich. He has authored or coauthored more than 180 publications in scientific or technical journals. Since 1994, he has been head of the Institute for Physics of Electrotechnology, Munich University of Technology, where his research activities are focused on the design, modeling, characterization, and diagnosis of the fabrication and operation of semiconductor microdevices and microsystems. Dr. Wachutka is a member of the American Electrochemical Society, the American Materials Research Society, the ESD Association, the VDE Association for Electrical, Electronic and Information Technologies, the German Physical Society, the American Physical Society, and the AMA Society for Sensorics.