CMOS linear image sensor

Transcription

1 High-speed readout (00 klines/s) The is a CMOS linear image sensor developed for industrial cameras that require high-speed scanning. The columnparallel readout system, which has a readout amplifier and an A/D converter for each pixel, allows high-speed readout. For the A/D converter resolution, either 0-bit (high-speed mode: 00 klines/s max.) or 2-bit (low-speed mode: 25 klines/s max.) can be selected. Video signal is output serially in 0 MHz LVDS format. Features Applications Pixel size: 7 7 µm Number of pixels: 4096 High-speed readout: 00 klines/s Simultaneous integration of all pixels power supply operation SPI communication function Built-in 0-bit/2-bit A/D converters Machine vision Film inspection Printed circuit board appearance inspection Print inspection Structure Parameter Specification Unit Number of pixels Pixel pitch 7 µm Pixel height 7 µm Effective photosensitive area length mm Package Ceramic - Window material* Borosilicate glass - *: AR coated (% or less reflectance at 400 to 00 nm) Absolute maximum ratings (Ta=25 C) Parameter Symbol Condition Value Unit Analog terminal Vdd(A) -0.3 to +3.9 V Supply voltage Digital terminal Vdd(D) -0.3 to +3.9 V Counter terminal Vdd(C) -0.3 to +3.9 V Digital input signal terminal voltage* 2 Vi -0.3 to +3.9 V Vref_cp terminal voltage Vref_cp -0.3 to +6.5 V Vref_cp2 terminal voltage Vref_cp2-2.0 to +0.3 V Operating temperature Topr No dew condensation* 3-5 to +70 C Storage temperature Tstg No dew condensation* 3-0 to +70 C *2: CS, SCLK, MOSI, RSTB, MCLK, MST, All-reset, Pll-reset *3: When there is a temperature difference between a product and the surrounding area in high humidity environment, dew condensation may occur on the product surface. Dew condensation on the product may cause deterioration in characteristics and reliability. Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings.

2 Recommended operating conditions (Ta=25 C) Parameter Symbol Min. Typ. Max. Unit Analog terminal Vdd(A) Supply voltage Digital terminal Vdd(D) V Counter terminal Vdd(C) Digital input voltage High level Vi(H) 3 Vdd(D) Vdd(D) V Low level Vi(L) Electrical characteristics Digital input signal [Ta=25 C, Vdd(A)=Vdd(D)=Vdd(C)=, unless otherwise noted] Parameter Symbol Min. Typ. Max. Unit Master clock pulse frequency f(mclk) MHz Master clock pulse duty cycle D(MCLK) % Master start pulse High-speed mode 300/f(MCLK) - - interval* 4 tpi(mst) Low-speed mode 200/f(MCLK) - - s Master start pulse High-speed mode 66/f(MCLK) - - High period* 4 thp(mst) Low-speed mode 664/f(MCLK) - - s Master start pulse High-speed mode 2/f(MCLK) - - Low period* 4 tlp(mst) Low-speed mode /f(mclk) - - s Master clock - Master start delay time tcsd ns Master clock - Reset delay time tcrd ns Rise time* 5 tr(sigi) ns Fall time* 5 tf(sigi) ns *4: The maximum line rate is 00 klines/s in high-speed mode. Line rate is 00 klines/s when tpi(mst) = 300/f(MCLK). The maximum line rate is 25 klines/s in low-speed mode. Line rate is 25 klines/s when tpi(mst) = 200/f(MCLK). *5: Time for the input voltage to rise or fall between 0% and 90% MCLK and MST input timings tr(sigi) tf(sigi) MCLK MST tcsd tr(sigi) tr(sigi) thp(mst) tpi(mst) tf(sigi) tlp(mst) KMPDC0677EA 2

3 PLL_Reset, All_Reset input timing After 00 µs of turning on the power, set PLL_Reset to low level for at least 5 master clock cycles and then do the same for All_Reset. Vdd(A) Vdd(D) Vdd(C) Rise time of power supply voltage >00 µs MCLK tcrd tcrd >5 clk PLL_Reset >5 clk All_Reset KMPDC0663EA Digital output signal [Ta=25 C, Vdd(A)=Vdd(D)=Vdd(C)=, f(mclk)=30 MHz, unless otherwise noted] Parameter Symbol Min. Typ. Max. Unit Video data rate (LVDS) DR f(mclk) 6 MHz Line rate High-speed mode LR Low-speed mode klines/s LVDS output voltage* Offset Vcom Differential Vdiff V LVDS rise time* 7 tr(lvds) ns LVDS fall time* 7 tf(lvds) ns Pclk OutX[m] period tpdd ns Pclk CTR period tpdc ns Pclk Sync period Rise time tpdsr ns Fall time tpdsf CMOS output voltage High Vsigo(H) Vdd(D)-0.25 Vdd(D) - Low Vsigo(L) V Clock pulse frequency High-speed mode - f(mclk) - f(tgclk) of timing generator Low-speed mode - f(mclk)/4 - MHz CMOS output rise time* tr(sigo) ns CMOS output fall time* tf(sigo) ns *6: Attach a 00 Ω terminator to the LVDS output terminal. *7: Time for the output voltage to rise or fall between 0% and 90% when there is a 2 pf load capacitor attached to the output terminal *: Time for the output voltage to rise or fall between 0% and 90% when there is a 0 pf load capacitor attached to the output terminal LVDS output voltage, rise and fall time Out_Xp[m] Out_Xn[m] Vcom Vdiff tr(lvds) tf(lvds) KMPDC065EA 3

4 Output timing of video output and Sync signal pclk Out_X [m] Sync tpdd tpdsf tpdsr CTR tpdc KMPDC0659EA Out_X[m] is video output. X: A to P (port), m: 0=lower bit, =higher bit Video output should be acquired at the rising timing of pclk. Video output starts after the rising of Sync. Sync can be used as reference of data acquisition [refer to Timing chart (P.)]. On the rising edge of CTR, the lower bits are output from D0 and the higher bits from D6. CTR can be used as reference of data acquisition [refer to Timing chart (P.9)]. Current consumption [Ta=25 C, Vdd(A)=Vdd(D)=Vdd(C)=, f(mclk)=30 MHz, LR=00 klines/s, unless otherwise noted] Parameter Symbol Min. Typ. Max. Unit Vdd A) terminal* 9 Ic Vdd(D) terminal* 9 Ic ma Vdd(C) terminal* 9 Ic *9: Apply saturation exposure light. Electrical characteristics of A/D converter [Ta=25 C, Vdd(A)=Vdd(D)=Vdd(C)=, f(mclk)=30 MHz, unless otherwise noted] Parameter Symbol Specification Unit High-speed mode 0* Resolution RESO 0 bit Low-speed mode 2 Conversion voltage range - 0 to.3 V *0: Equivalent to 0-bit. From offset output to saturated output is approximately 024 DN. 4

5 Electrical and optical characteristics [Ta=25 C, Vdd(A)=Vdd(D)=Vdd(C)=, f(mclk)=30 MHz, gain: default value, offset: default value, tpi(mst)=0 µs (high-speed mode), 40 µs (low-speed mode), unless otherwise noted] Common to all modes Parameter Symbol Min. Typ. Max. Unit Spectral response range λ 400 to 000 nm Peak sensitivity wavelength λp nm Gain= - ±5 ±0 Photoresponse nonuniformity* PRNU Gain= - ±5 ±0 % Image lag* 2 Lag % Saturation charge Qsat ke- SNR max. Gain= Gain= db *: The output uniformity when a uniform light with a light exposure that is approximately 50% of saturation output is applied. It is defined as follows for the 4090 pixels excluding the 3 pixels at each end of the sensor. PRNU = (ΔX/X) 00 [%] *2: The signal component of the previous data that remains after data is read out under saturation output conditions. Image lag increases if light greater than the saturation exposure is incident. High-speed mode Parameter Symbol Gain Min. Typ. Max. Unit - 3 mv DN Offset variation* 3 VSNU mv DN mv DN Dark output* 4 VD mv DN V/(lx s) Photosensitivity* 5-36k - DN/(lx s) Sw V/(lx s) - 290k - DN/(lx s) µv/e mdn/e- Conversion efficiency CE µv/e mdn/e V Saturation output Vsat DN mv-rms DN-rms Readout noise* 6 Nread mv-rms DN-rms Dynamic range* 7 Drange

6 Low-speed mode Parameter Symbol Gain Min. Typ. Max. Unit - 3 mv DN Offset variation* 3 VSNU mv DN mv DN Dark output* 4 VD mv DN V/(lx s) - 40k - DN/(lx s) Photosensitivity* 5 Sw V/(lx s) - 200k - DN/(lx s) µv/e mdn/e- Conversion efficiency CE µv/e mdn/e V Saturation output Vsat DN mv-rms DN-rms Readout noise* 6 Nread mv-rms DN-rms Dynamic range* 7 Drange *3: Measured in the dark state. Difference between the maximum and minimum. *4: Ts=0 ms, voltage difference from the offset output level *5: 256 K, tungsten lamp *6: Dark state *7: Vsat/Nread Note: DN (digital number): unit of A/D converter output Spectral response (typical example) (Ta=25 C) Spectral transmittance characteristics of window material (Typ. Ta=25 C) Photosensitivity (A/W) Transmittance (%) Wavelength (nm) KMPDB0493EA Wavelength (nm) KMPDB0494EA 6

7 Block diagram The video output signal is divided and output through 6 ports (A through P). Each port outputs 256 pixels of data (pixel numbers output from each port: A= to 256, B=257 to 52,... P=34 to 4096). KMPDC0637EA Enlarged view of video output (full output mode) Output for each port divides data into LVDS (lower bits and higher bits) pairs. Port A to 256 pixels Port B 257 to 52 pixels Port P 34 to 4096 pixels 6-bit 6-bit 6-bit 6-bit 6-bit 6-bit Serializer A Serializer A Serializer B Serializer B Serializer P Serializer P Lower bit Higher bit Lower bit Higher bit Lower bit Higher bit KMPDC075EA 7

8 Timing chart Description of operation The integration time is determined by the low period of the start pulse. ST ➀ ➁ ➂ Integration time Integration time Integration time Video output (Port A) Video output (Port B) Video data Video data ( to 256 pixels) ( to 256 pixels) Video data Video data (257 to 52 pixels) (257 to 52 pixels) KMPDC076EA () The start of integration time is determined by the falling edge of the start pulse. (2) The end of integration time is determined by the rising edge of the start pulse. (3) Video data is output after the rising edge of the next start pulse cycle. Video data is output in order from the first pixel. (256 pixels of data are output for each port.) * Signal integration is possible even during video output TGCLK n-th frame integration time ST thp(mst) tlp(mst) 35 clocks tpi(mst) Sync Out_A [0] Out_A [] Out_P [0] Out_P [] 3 clocks Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data (n-2)-th frame data 256 pixels (n-)-th frame data 256 pixels n-th frame data 256 pixels CS KMPDC0660EA Line rate equals the reciprocal of start pulse interval. TGCLK is a timing generator clock inside the sensor. TGCLK is the same frequency as that of MCLK in high-speed mode, and the /4 in low-speed mode. The integration time equals the low period of start pulse plus 06 clock cycles of TGCLK. SPI set within 3 TGCLK clocks after the rising edge of the start pulse is updated starting from the nth frame data. In /4 output mode, only the following outputs are valid. Out_A[0], Out_C[0], Out_E[0], Out_G[0], Out_I[0], Out_K[0], Out_M[0] and Out_O[0]

9 ex.: Port A, B Full output mode PCLK Sync CTR Out_A[0] D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D5 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 Out_A[] D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 Out_B[0] D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 D5 D0 D D2 D3 D4 Out_B[] D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 D D6 D7 D D9 D0 Invalid data st pixel data 2nd pixel data 3rd pixel data KMPDC066EA /4 output mode PCLK Sync CTR Out_A[0] 4 cycles D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D D0 D D2 D3 D4 D5 D6 D7 D D9 D0 D Invalid data Port A st pixel data Port B st pixel data Port A 2nd pixel data Port B 2nd pixel data KMPDC0662EA Operation example Example Line rate = 00 kline/s, master clock pulse frequency = 30 MHz, high-speed mode, full output mode, integration time max. MST pulse cycle: 0 µs Integration time: µs MST.7 µs Sync.53 µs Video output 256 KMPDC069EA Master start pulse cycle = 300/f(MCLK) = 0 µs (equals the reciprocal of start pulse interval.) Master start pulse s low period = Master start pulse cycle Master start pulse s High period min. = 300/f(MCLK) - 66/f(MCLK) = 300/30 MHz - 66/30 MHz = 34/30 MHz = 4.47 µs Integration time = master start pulse low period + 06 cycles of master clock pulses = ( )/30MHz = µs Sync rises about.7 µs after the rising edge of the master start pulse. Then the video output signal is output in order from the first pixel (256 pixels is output from each port). 9

10 Example 2: Line rate = 25kline/s, master clock pulse frequency = 30MHz, low-speed mode, /4 output mode, integration time max. MST pulse cycle: 40 µs Integration time: 32 µs MST 4.67 µs Sync 34.3 µs Video output 256 KMPDC0692EA Master start pulse cycle = 200/f(MCLK) = 40 µs (equals the reciprocal of start pulse interval.) Master start pulse s low period = Master start pulse cycle Master start pulse s High period min. = 200/f(MCLK) - 664/f(MCLK) = 200/30 MHz - 664/30 MHz = 536/30 MHz = 7.7 µs Integration time = master start pulse low period cycles of master clock pulses = ( )/30 MHz = 32 µs Sync rises approximately 4.67 µs after the rising edge of the master start pulse. Then the video output signal is output in order from the first pixel (256 pixels is output from each port). 0

11 SPI address setting Address (Decimal) Register Default value Binary Decimal Setting 0 Mode[:0] Mode[0] high-speed/low-speed mode (default: high-speed mode) Mode[] number of video output terminal (default: full output mode) 9 pclk_delay[5:0] pclk timing (default: pclk-delay [5:0]=0) 20 AGC[4:0] Gain (default: gain=) 2 Offset[:] Offset[7:0] Output offset (default: 3) Note) Always set the addresses shown in the above table. The image sensor may malfunction if any other address is set. High-speed/low-speed mode Maximum line rate is selectable from following 2 modes: It is set to High-speed mode when Mode[0] is 0 (Low), Low-speed mode when Mode[0] is (High). High-speed mode (Mode[0]=0): Maximum line rate = 00 klines/s, A/D converter resolution = 0-bit (From offset output to saturation output is approximately 024 DN.) Low-speed mode (Mode[0]=): Maximum line rate = 25 klines/s, A/D converter resolution = 2-bit Number of video output terminal The number of video output terminal is selectable from following 2 modes: Full output mode (Mode[]=0): Video output=64 terminals (32 LVDS pairs) /4 output mode (Mode[]=): Video output=6 terminals ( LVDS pairs) * To make the line rate faster than 25 klines/s, do not use /4 output mode. Note) Refer to [timing chart (P.9)] in detail. pclk timing The pclk output timing can be delayed inside the sensor. Set pclk_delay[5:0] between 0 and 63. When pclk_delay[5:0] is increased by, the pclk output is delayed by approximately 0.5 ns. Gain setting The sensor may not operate properly if a setting not in the following table is specified. Specify a setting shown in the table. AGC[4:0] Decimal Binary Gain Description [4] [3] [2] [] [0] Default setting

12 Output offset setting Set Offset[:0] between 0 and 023. When Offset[:0] is increased by, the offset value increases by DN. Due to the variations in each chip, the actual offset value will be slightly off from the specified value. Set offset[:0] to 0. SPI setting Set the SPI using SCLK, CS, and MOSI. Setting RSTB to low level resets all parameters. SCLK CS tset(cs) thold(cs) MOSI A6 A5 A0 W D7 D6 D0 MISO tset(mo) thold(mo) KMPDC0693EA (Ta=25 C, Vdd(A)=Vdd(D)=, f(mclk)=30 MHz, LR=00 klines/s, unless otherwise noted) Item Symbol Min. Typ. Max. Unit SPI clock pulse frequency f(sclk) MHz SPI setup time (CS) tset(cs) ns SPI hold time (CS) thold(cs) ns SPI setup time (MOSI) tset(mo) ns SPI hold time (MOSI) thold(mo) ns Digital input signal rise time* tr(sigi) ns Digital input signal fall time* tf(sigi) ns *: The time for input voltage to rise or fall between 0% and 90% Example of SPI setting Writing AGC [4:0]= (setting gain to 2 times) SCLK CS MOSI A6 A5 A4 A3 A2 A A0 W D7 D6 D5 D4 D3 D2 D D0 MISO KMPDC0694EA 2

13 Checking the SPI setting You can check the current SPI setting in the following manner. SCLK CS MOSI A6 A5 A0 R MISO D7 D6 D0 tsmd tr(sigo), tf(sigo) KMPDC0695EA (Ta=25 C, Vdd(A)=Vdd(D)=, f(mclk)=30 MHz, LR=00 klines/s, unless otherwise noted) Item Symbol Min. Typ. Max. Unit Output signal rise time* 9 tr(sigo) ns Output signal fall time* 9 tf(sigo) ns SCLK-MISO delay time tsmd ns *9: Time for the output voltage to rise or fall between 0% and 90% when the load capacitance of the output terminal is 0 pf Example of checking the SPI setting Confirms AGC [4:0]= (gain=2 times) SCLK CS MOSI A6 A5 A4 A3 A2 A A0 r MISO D7 D6 D5 D4 D3 D2 D D0 KMPDC0696EA 3

14 Dimensional outline (unit: mm) 4.45 ± 0.05* ± 0.2 Photosensitive area.46 ± 0.05* Window.40 ± 0.2* 3.35 ± 0.2* 4.60 ± 0.2* st pixel 6.50 ± Index mark 0.50* 6 ϕ.20 Direction of scan Photosensitive surface 3.00 (0.) (0.2) (3.0) 4.00 Index mark ± 0.27 A B C D E F G H I J K Tolerance unless otherwise noted: ±0.2 *: Distance from package edge to photosensitive area center *2: Distance from package edge to photosensitive area edge *3: Distance from package bottom to photosensitive area *4: Distance from glass surface to photosensitive surface *5: Distance from package top to photosensitive surface *6: Glass thickness ± 0.27 KMPDA0572EA 4

15 Pin connections Pin no. Symbol Function I/O A2 Out_An[0] Video output signal O A4 Out_An[] Video output signal O A6 Out_Cn[0] Video output signal O A Out_Cn[] Video output signal O A0 Out_En[0] Video output signal O A2 Out_En[] Video output signal O A4 Out_Gn[0] Video output signal O A6 Out_Gn[] Video output signal O A Out_In[0] Video output signal O A20 Out_In[] Video output signal O A22 Out_Kn[0] Video output signal O A24 Out_Kn[] Video output signal O A26 Out_Mn[0] Video output signal O A2 Out_Mn[] Video output signal O A30 Out_On[0] Video output signal O B Out_Ap[0] Video output signal O B3 Out_Ap[] Video output signal O B5 Out_Cp[0] Video output signal O B7 Out_Cp[] Video output signal O B9 Out_Ep[0] Video output signal O B Out_Ep[] Video output signal O B3 Out_Gp[0] Video output signal O B5 Out_Gp[] Video output signal O B7 Out_Ip[0] Video output signal O B9 Out_Ip[] Video output signal O B2 Out_Kp[0] Video output signal O B23 Out_Kp[] Video output signal O B25 Out_Mp[0] Video output signal O B27 Out_Mp[] Video output signal O B29 Out_Op[0] Video output signal O B3 Out_Op[] Video output signal O C2 Vdd(D) Supply voltage () I C4 Ground - C6 PCLKn Bit output sync signal O C CTRn Pixel sync signal O C0 NC No connection - C2 NC No connection - C4 NC No connection - C6 NC No connection - C NC No connection - C20 NC No connection - C22 NC No connection - C24 NC No connection - C26 Syncn Frame sync signal O C2 MCLK Master clock signal I C30 Out_On[] Video output signal O D Vdd(D) Supply voltage () I D3 Ground - D5 PCLKp Bit output sync signal O D7 CTRp Pixel sync signal O D9 Vref_cp Bias voltage for charge pump circuit (5.5 V)* 20 O D Vref_cp2 Bias voltage for charge pump circuit (-.5 V)* 20 O D3 Vref Bias voltage* 20 O D5 Vref2 Bias voltage* 20 O D7 Vref3 Bias voltage* 20 O D9 Vref4 Bias voltage* 20 O D2 Vref5 Bias voltage* 20 O *20: Insert a µf capacitor between each terminal and. Note: Leave NC pins open; do not connect to. Pin no. Symbol Function I/O D23 Vref6 Bias voltage* 20 O D25 Syncp Frame sync signal O D27 MST Master start signal I D29 (C) Ground - D3 Vdd(C) Supply voltage () I E2 Vdd(D) Supply voltage () I E4 Ground - E6 Pll_Reset Pll circuit reset I E CS SPI selection signal I E24 NC No connection - E26 All_Reset Timing generator reset I E2 (C) Ground - E30 Vdd(C) Supply voltage () I F Vdd(D) Supply voltage () I F3 Ground - F5 SCLK SPI clock signal I F7 MOSI SPI input signal I F9 RSTB SPI reset signal I F23 NC No connection - F25 NC No connection - F27 NC No connection - F29 (C) Ground - F3 Vdd(C) Supply voltage () I G2 Vdd(D) Supply voltage () I G4 Ground - G6 MISO SPI output signal O G TGCLK Timing generator clock signal O G24 NC No connection - G26 NC No connection - G2 (C) Ground - G30 Vdd(C) Supply voltage () I H Vdd(D) Supply voltage () I H3 Ground - H5 NC No connection - H7 NC No connection - H9 Vref7 Bias voltage* 20 O H Vref Bias voltage* 20 O H3 Vref9 Bias voltage* 20 O H5 Vref0 Bias voltage* 20 O H7 Vref Bias voltage* 20 O H9 Vref2 Bias voltage* 20 O H2 Vref3 Bias voltage* 20 O H23 Vref4 Bias voltage* 20 O H25 NC No connection - H27 NC No connection - H29 (C) Ground - H3 Vdd(C) Supply voltage () I I2 Vdd(D) Supply voltage () I I4 Ground - I6 NC No connection - I NC No connection - I0 Vdd(A) Supply voltage () I I2 Ground - I4 Vdd(A) Supply voltage () I I6 Ground - I Vdd(A) Supply voltage () I I20 Ground - 5

16 Pin no. Symbol Function I/O I22 Vdd(A) Supply voltage () I I24 Ground - I26 NC No connection - I2 NC No connection - I30 Out_Pn[] Video output signal O J Out_Bp[0] Video output signal O J3 Out_Bp[] Video output signal O J5 Out_Dp[0] Video output signal O J7 Out_Dp[] Video output signal O J9 Out_Fp[0] Video output signal O J Out_Fp[] Video output signal O J3 Out_Hp[0] Video output signal O J5 Out_Hp[] Video output signal O J7 Out_Jp[0] Video output signal O J9 Out_Jp[] Video output signal O J2 Out_Lp[0] Video output signal O J23 Out_Lp[] Video output signal O J25 Out_Np[0] Video output signal O Note: The video output symbol is defined as follows: Out_An[0] [0]: lower (0 to 5) bits, []: higher (6 to ) bits p: positive input of the differential pair, n: negative input of the differential pair A to P: output ports Pin no. Symbol Function I/O J27 Out_Np[] Video output signal O J29 Out_Pp[0] Video output signal O J3 Out_Pp[] Video output signal O K2 Out_Bn[0] Video output signal O K4 Out_Bn[] Video output signal O K6 Out_Dn[0] Video output signal O K Out_Dn[] Video output signal O K0 Out_Fn[0] Video output signal O K2 Out_Fn[] Video output signal O K4 Out_Hn[0] Video output signal O K6 Out_Hn[] Video output signal O K Out_Jn[0] Video output signal O K20 Out_Jn[] Video output signal O K22 Out_Ln[0] Video output signal O K24 Out_Ln[] Video output signal O K26 Out_Nn[0] Video output signal O K2 Out_Nn[] Video output signal O K30 Out_Pn[0] Video output signal O Precautions () Electrostatic countermeasures This device has a built-in protection circuit against static electrical charges. However, to prevent destroying the device with electrostatic charges, take countermeasures such as grounding yourself, the workbench and tools. Also protect this device from surge voltages which might be caused by peripheral equipment. (2) Light input window If dust or stain adheres to the surface of the light input window glass, it will appear as black spots on the image. When cleaning, avoid rubbing the window surface with dry cloth, dry cotton swab or the like, since doing so may generate static electricity. Use soft cloth, paper, a cotton swab, or the like moistened with alcohol to wipe off dust and stain. Then blow compressed air so that no stain remains. (3) Soldering To prevent damaging the device during soldering, take precautions to prevent excessive soldering temperatures and times. Soldering should be performed within 5 seconds at a soldering temperature below 260 C. (4) Operating and storage environments Handle the device within the temperature range of the absolute maximum ratings. Operating or storing the device at an excessively high temperature and humidity may cause variations in performance characteristics and must be avoided. (5) UV light irradiation Because this product is not designed to resist characteristic deterioration under UV light irradiation, do not apply UV light irradiation to it. (6) Fixing the product in place When using screws to fix the product in place, use M2 screws. Set the tightening torque to 0.0 N m or less. 6

17 Connection circuit example µf µf µf µf µf 0. µf 0. µf 0. µf 0. µf 0. µf Vdd(C) Vdd(C) Vdd(C) Vdd(C) Vdd(C) Vref_cp µf Vref_cp2 µf Vref µf Vref2 µf Vref3 µf Vref4 µf Vref5 µf Vref6 µf Vref7 µf Vref µf Vref9 µf Vref0 µf Vref µf Vref2 µf Vref3 µf Vref4 µf Vdd(A) Vdd(A) Vdd(A) Vdd(A) Vdd(D) Vdd(D) Vdd(D) Out_Xp[m] Out_Xn[m] PCLKp PCLKn CTRp CTRn Syncp Syncn MCLK MST Pll_Reset All_Reset CS SCLK MOSI RSTB MISO TGCLK Vdd(D) Vdd(D) Vdd(D) Vdd(D) Digital buffer 00 Ω 00 Ω 00 Ω 00 Ω µf µf Digital buffer Connect and (C) with a single point. KMPDC063EA 7

18 Related information Precautions Disclaimer Image sensors Information described in this material is current as of July 20. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. HAMAMATSU PHOTONICS K.K., Solid State Division 26- Ichino-cho, Higashi-ku, Hamamatsu City, Japan, Telephone: () , Fax: () U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 007, U.S.A., Telephone: () , Fax: () , Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 0, D-22 Herrsching am Ammersee, Germany, Telephone: (49) , Fax: (49) , France: Hamamatsu Photonics France S.A.R.L.: 9, Rue du Saule Trapu, Parc du Moulin de Massy, 92 Massy Cedex, France, Telephone: 33-() , Fax: 33-() , infos@hamamatsu.fr United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 0 Tewin Road, Welwyn Garden City, Hertfordshire AL7 BW, United Kingdom, Telephone: (44) , Fax: (44) , info@hamamatsu.co.uk North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan Kista, Sweden, Telephone: (46) , Fax: (46) , info@hamamatsu.se Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, int. 6, Arese (Milano), Italy, Telephone: (39) , Fax: (39) , info@hamamatsu.it China: Hamamatsu Photonics (China) Co., Ltd.: B20, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 00020, China, Telephone: (6) , Fax: (6) , hpc@hamamatsu.com.cn Taiwan: Hamamatsu Photonics Taiwan Co., Ltd.: F-3, No. 5, Section2, Gongdao 5th Road, East District, Hsinchu, 300, Taiwan R.O.C. Telephone: (6) , Fax: (6) , info@hamamatsu.com.tw Cat. No. KMPD4E02 Jul. 20 DN