CCD47-10 NIMO Back Illuminated Compact Pack High Performance CCD Sensor
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1 CCD47-10 NIMO Back Illuminated Compact Pack High Performance CCD Sensor FEATURES 1024 by 1024 Nominal (1056 by 1027 Usable Pixels) Image area 13.3 x 13.3mm Back Illuminated format for high quantum efficiency Full-Frame Operation 13µm Square Pixels Symmetrical anti-static gate protection Very low noise output amplifiers Gated Dump Drain on Output Register 100% Active area New Compact Footprint Package APPLICATIONS Spectroscopy Scientific Imaging Star Tracking Medical Imaging INTRODUCTION This version of the CCD47 family of CCD sensors has full-frame architecture. Back illumination technology, in combination with extremely low noise amplifiers, makes the device well suited to the most demanding scientific applications. To improve the sensitivity further, the CCD is manufactured without antiblooming structures. The device has a single serial output register. Separate charge detection circuits are incorporated at each end of the register, which is split so that a line of charge can be transferred to either output, or split between the two. The register is provided with a drain and control gate along the outer edge of the channel for charge dump purposes. Other variants of the CCD47-10 available are front illuminated format and inverted mode (MPP). In common with all e2v technologies CCD Sensors, the CCD47-10 is also available with a fibre-optic window or taper, or with a phosphor coating. Designers are advised to consult e2v technologies should they be considering using CCD sensors in abnormal environments or if they require customised packaging. TYPICAL PERFORMANCE (Low noise mode) GENERAL DATA Format Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc Telephone: +44 (0) Facsimile: +44 (0) Contact e2v by enquiries@e2v.com or visit for global sales and operations centres. Pixel readout frequency 5 MHz Output amplifier sensitivity 4.5 µv/e - Peak signal 120 ke - /pixel Dynamic 20 khz 50000:1 Spectral range nm Readout 20 khz 2.0 e - rms Image area 13.3 x 13.3 mm Active pixels 1056 (H) x 1027 (V) Pixel size 13 x 13µm Number of output amplifiers 2 Weight (approx., no window) 6g Package Package size 22.6 x 29.9 mm Number of pins 24 Inter-pin spacing 2.54 mm Window material Quartz or Removable glass Package type Ceramic DIL array e2v technologies (uk) limited 2016 A1A Version 9, Oct 2016 Template: DF764388A
2 PERFORMANCE AT 243 K ( 30 C) UNLESS STATED OTHERWISE Min Typical Max Units Note Peak charge storage - 120,000 - e /pixel 1 Peak output voltage (unbinned) mv 1 Dark signal at 293 K Standard Silicon - 20,000 40,000 Deep Depleted Silicon 43,000 85,000 e /pixel/s 2, 3 Dynamic Range - 50, Charge transfer efficiency Parallel % Serial % 5 Output amplifier responsivity Low noise mode µv/e Readout noise Low noise mode rms e 6 Maximum readout frequency MHz 7 Dark signal nonuniformity at 293 K (std. deviation) Standard Silicon Deep Depleted Silicon Response non-uniformity (std. deviation) % SPECTRAL RESPONSE AT 243 K ( 30 C) Standard Silicon Wavelength (nm) Enhanced Process UV Coated Minimum Response (QE) Basic Process Mid-band Coated Basic Process Broadband Coated Maximum Response Nonuniformity (1σ) e /pixel/s 3, % % % % % 900 (1) % (1) For Shielded Anti-Blooming (SAB) variants the minimum response at 900nm is reduced to 24% Deep Depleted Silicon Wavelength (nm) Minimum Response (QE) Basic Process NIR Enhanced Process Coated Multilayer 2 Coated Basic Process Uncoated Maximum Response Nonuniformity (1σ) % % % % % e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 2
3 ELECTRICAL INTERFACE CHARACTERISTICS Electrode Capacitances (Measured at mid-clock level) Min Typical Max I /I interphase nf I /SS nf R /R interphase pf R //SS 60 pf R /(SS + DG + OD) pf Output impedance at typical operating conditions Ω NOTES 1. Signal level at which resolution begins to degrade. The typical values are those expected from design. Not measured as a production test. 2. The typical average (background) dark signal at any temperature T (kelvin) between 233 K and 293 K and VSS + 9.5V may be estimated from: Q d /Q d0 = 122T 3 e 6400/T Where Q d0 is the dark signal at 293 K. 3. Test carried out at 243 K and scaled to 293 K using the formula in note Dynamic range is the ratio of full-well capacity to readout noise. 5. CCD characterisation measurement using charge generated by X-ray photons of known energy. Not measured as a production test. 6. Measured at a pixel readout frequency of 18 KHz using a dual-slope integrator technique (i.e. correlated double sampling). 7. Readout above 5 MHz into a 15pF load can be achieved but performance to the parameters given cannot be guaranteed. 8. Excluding white defects. e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 3
4 BLEMISH SPECIFICATION Traps Black spots White spots Pixels where charge is temporarily held. Traps are counted if they have a capacity greater than 200 e at 243 K. Are counted when they have a signal level of less than 80% of the local mean at a signal level of approximately half full-well at 243K. Are counted when they have a generation rate 20 times the specified maximum dark signal generation rate (measured at 243 K). The typical temperature dependence of white spot blemishes is the same as that of the average dark signal i.e.: Q d /Q d0 = 122T 3 e 6400/T Column defects A column which contains at least 21 white or 21 black defects. GRADE Column defects; black or white White Black spots Traps >200 e White spots Grade 5 Devices which are fully functional, with image quality below that of grade 2, and which may not meet all other performance parameters. Minimum separation between adjacent black columns 50 Pixels Note: The effect of temperature on defects is that traps will be observed less at higher temperatures but more may appear below 233 K. The amplitude of white spots and columns will decrease rapidly with temperature. e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 4
5 TYPICAL SPECTRAL RESPONSE (At 30 C ) e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 5
6 TYPICAL OUTPUT CIRCUIT NOISE (If Measured using clamp and sample) TYPICAL VARIATION OF DARK CURRENT WITH SUBSTRATE VOLTAGE e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 6
7 TYPICAL VARIATION OF DARK SIGNAL WITH TEMPERATURE DEVICE SCHEMATIC e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 7
8 CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS CLOCK HIGH OR DC LEVEL (V) Min Typical Max MAXIMUM RATINGS with respect to V SS PIN REF DESCRIPTION 1 ABD Anti-blooming drain (see note 10) 2 I 3 Image area clock ±20V 3 I 2 Image area clock ±20V 4 I 1 Image area clock ±20V 5 OG Output Gate ±20V 6 - No Connection SS Substrate VOD -0.3 to +25V 8 R Output reset pulse (left and right amplifiers) ±20V 9 R 2L Output register clock (left section) ±20V 10 R 1L Output register clock (left section) ±20V 11 OD Output transistor drain (left and right amplifiers) to +32V 12 OSL Output transistor source (left amplifier) See note to +25V 13 OSR Output transistor source (right amplifier) See note to +25V 14 RD Reset transistor drain (left and right amplifiers) to +25V 15 R 1R Output register clock (right section) ±20V 16 R 2R Output register clock (right section) ±20V 17 R 3 Output register clock (left and right sections) ±20V 18 SS Substrate No Connection DG Dump gate (see note 12) ±20V 21 I 1 Image area clock ±20V 22 I 2 Image area clock ±20V 23 I 3 Image area clock ±20V 24 ABG Anti-blooming gate ±20V Maximum voltages between pairs of pins: pin 12 (OSL) to pin 11 (OD)... ±15 V pin 11 (OD) to pin 13 (OSR)... ±15 V Maximum output transistor current ma e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 8
9 NOTES 9. Readout register clock pulse low levels +1V; other clock low levels 0 ± 0.5V 10. Drain not incorporated, but bias is still necessary to 5V below OD. Connect to ground using a 3 to 5 ma current source or appropriate load resistor (typically 5 to 10kΩ). 12. Non-charge dumping level shown. For operation in charge dumping mode, DG should be pulsed to 12 ± 2V 13. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be required to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ from device to device. 14. With the R connections shown, the device will operate through the right-hand output only. In order to operate from both outputs R 1 (L) and R 2 (L) should be reversed. e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 9
10 FRAME READOUT TIMING DIAGRAM DETAIL OF LINE TRANSFER (Not to scale) (For output from a single amplifier) e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 10
11 DETAIL OF VERTICAL LINE TRANSFER (Single line dump) DETAIL OF VERTICAL LINE TRANSFER (Multiple line dump) e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 11
12 DETAIL OF OUTPUT CLOCKING LINE OUTPUT FORMAT CLOCK TIMING REQUIREMENTS Symbol Description Min Typical Max T i Image clock period 4 14 see note 15 µs t wi Image clock pulse width 2 5 see note 15 µs t ri Image clock pulse rise time (10 to T i 2t wi µs 90%) t fi Image clock pulse fall time (10 to t ri t ri T i -2t wi µs 90%) t oi Image clock pulse overlap (t ri + t fi )/2 0.6 (3t wi - T i )/2 µs t dir Delay time, I stop to R start 1 2 see note 15 µs t dri Delay time, R stop to I start 1 1 see note 15 µs T r Output register clock cycle period see note 15 ns t rr Clock pulse rise time (10 to 90%) T r 0.3T r ns t fr Clock pulse fall time (10 to 90%) t rr 0.1T r 0.3T r ns t or Clock pulse overlap t rr 0.1T r ns t wx Reset pulse width T r 0.3T r ns t rx, t fx Reset pulse rise and fall times 0.2t wx 0.5t rr 0.1T r ns t dx Delay time, R low to R 3 low T r 0.8T r ns NOTES 15. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times. e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 12
13 OUTPUT CIRCUIT NOTES 16. The amplifier has a DC restoration circuit which is internally activated whenever I 2 is high. 17. Not critical; can be a 3 to 5mA constant current supply or an appropriate load resistor. e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 13
14 OUTLINES (All dimensions in millimetres; dimensions without limits are nominal) Standard Ceramic Package e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 14
15 ORDERING INFORMATION Options include: Temporary quartz window Permanent quartz window Temporary glass window Permanent glass window Fibre-optic coupling UV coating X-ray phosphor coating For further information on the performance of these and other options, contact e2v. HANDLING CCD SENSORS CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include: Working at a fully grounded workbench Operator wearing a grounded wrist strap All receiving socket pins to be positively grounded Unattended CCDs should not be left out of their conducting foam or socket. Evidence of incorrect handling will invalidate the warranty. All devices are provided with internal protection circuits to the gate electrodes (pins 2, 3, 4, 5, 8, 9, 10, 15, 16, 17, 20, 21, 22, 23, 24) but not to the other pins. HIGH ENERGY RADIATION Device characteristics will change when subject to ionising radiation. Users planning to use CCDs in a high radiation environment are advised to contact e2v. TEMPERATURE LIMITS Min Typical Max Storage K Operating K Operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. Maximum device heating/cooling... 5 K/min e2v technologies (uk) limited 2016 Document subject to disclaimer on page 1 A1A Version 9, page 15
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