WE05MF. 2 SOT-553 (Top View) Features IEC COMPATIBILITY (EN ) Tel: Transient Voltage Suppressor SOT-553

Transcription

1 Document: W030044, Rev: A Transient Voltage Suppressor Features Solid-state silicon-avalanche technology 30 Watts Peak Pulse Power per Line (t p =8/20μs) Low operating and clamping voltages Up to Four (4) Lines of Protection Working Voltages: 5 V Low Leakage Current IEC COMPATIBILITY (EN6000-4) SOT-553 IEC (ESD) ±5kV (air), ±8kV (contact) IEC (EFT) 40A (5/50ns) Mechanical Characteristics Applications SOT-553 package Molding compound flammability rating: UL 94V-0 Marking: Marking Code Packaging: Tape and Reel RoHS/WEEE Compliant Cellular Handsets & Accessories Personal Digital Assistants (PDAs) Notebooks & Handhelds Portable Instrumentation Digital Cameras MP3 Player Circuit Diagram Schematic & PIN Configuration SOT-553 (Top View) / 5

2 Absolute Maximum Rating Rating Symbol Value Units Peak Pulse Power ( t p =8/20μs ) P PP 30 Watts Peak Forward Voltage ( I F =A, t p =8/20μs ) V FP.5 V Operating Temperature T J -55 to + 25 C Storage Temperature T STG -55 to +50 C Electrical Parameters (T=25 ) Symbol Parameter I IPP Maximum Reverse Peak Pulse Current I F VC VRWM IR VBR IT IF Clamping IPP Working Peak Reverse Voltage Maximum Reverse Leakage VRWM Breakdown IT Test Current Forward Current V C V BR V RWM I R V F V I T I PP VF Forward IF Electrical Characteristics Parameter Symbol Conditions Minimum Typical Maximum Units Reverse Stand-Off Voltage V RWM 5.0 V Reverse Breakdown Voltage V BR I T=mA 6.0 V Reverse Leakage Current I R V RWM=5V,T=25 C μa Peak Pulse Current I PP tp =8/20μs 2 A Clamping Voltage V C I PP=2A, t p=8/20μs V Junction Capacitance C j Between I/O pins and Ground VR = 0V, f = MHz 6.5 pf 2 / 5

3 Typical Characteristics Figure : Peak Pulse Power vs. Pulse Time Figure 2: Power Derating Curve Ppp Peak Pulse Power - Ppp(KW) ,000 t d Pulse Duration - µs Percent of Rated Power for Ipp Ambient Temperature - T A ( ) Figure 3: Insertion Loss Figure 4: Normalized Junction Capacitance vs. Reverse Voltage CH S2 LOG 6 db / REF 0 db START.030 MHz STOP MHz Cj(VR)/Cj(VR=0)..0 F=MHz Reverse Voltage -V R (V) Figure 5: ESD Clamping( 8kV Contact per IEC ) Tek Run: 2.50GS/s Sample CH 0.0 VΩ M 30.0ns Ch 7.0V 3 / 5

4 Application Information The are TVS arrays designed to protect I/O or data lines from the damaging effects of ESD or EFT. This product provides unidirectional protection; the device is connected as follows: UNIDIRECTIONAL COMMON-MODE CONFIGURATION The provides up to four (4) lines of protection in a common-mode configuration as depicted in Figure. Circuit connectivity is as follows: I/O is connected to Pin 5. I/O 2 is connected to Pin 4. I/O 3 is connected to Pin 3. I/O 4 is connected to Pin. Pin 2 is connected to ground. I/O I/O I/O INTEGRATED CIRCUIT I/O 3 I/O 4 Figure Unidirectional Configuration Common-Mode I/O Port Protections CIRCUIT BOARD LAYOUT RECOMMENDATIONS Circuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are recommended: The protection device should be placed near the input terminals or connectors, the device will divert the transient current immediately before it can be coupled into the nearby traces. The path length between the TVS device and the protected line should be minimized. All conductive loops including power and ground loops should be minimized. The transient current return path to ground should be kept as short as possible to reduce parasitic inductance. Ground planes should be used whenever possible. For multilayer PCBs, use ground vias. 4 / 5

5 Outline Drawing SOT-553 PACKAGE OUTLINE b D e E E DIMENSIONS SYMBOL INCHES MILLIMETER MIN MAX MIN MAX A b C D A E C E L e L X G Z DIMENSIONS DIM INCHES MILLIMETERS Z G Notes. Dimensioning and tolerances per ANSI Y4.5M, Controlling Dimension: Inches 3. Dimensions are exclusive of mold flash and metal burrs. Y P TYP 0.50 TYP X P Y Marking Codes Part Number Marking Code E5F 5 / 5