Design and Analysis of Low Power Phase Locked Loop Based Frequency Synthesizer using Cadence Tool

Transcription

1 Design and Analysis of Low Power Phase Locked Loop Based Frequency Synthesizer using Cadence Tool K.Deepa 1, R.Shankar 2 1, 2 Department of ECE 1, 2 Kongunadu College of Engineering & Technology Abstract- The CMOS PLL based Frequency Synthesizer is a vital role in Receiver front end Sub component. The main objective of this paper is to design a high frequency of oscillation, less phase noise and power efficient PLL. In general, the PLL contains PFD, Loop Filter, VCO and Frequency Divider. The VCO is a critical component in Phase Locked Loop for low power CMOS designs. Here the Source Coupled VCO is proposed, Even though it consumes more power and area.power dissipation is one of the main important performance parameter now. The Adaptive Voltage level techniques have applied in obtainableeffortmoderate the power dissipation. In this paper provides over all circuit diagram of PLL block diagram. It is designed in CADENCE VIRTUOSO 180nm Technology. Exploiting CADENCE software schematic diagram of overall PLL is drawn and the power, Frequency of oscillation and noise performance are analyzed. Keywords- Source Coupled VCO, PFD, PLL, CADENCE, Frequency Divider and Charge Pump. I. INTRODUCTION A PLL is a feedback system that compares the output frequency/phase with the inputfrequency/phase. Phase-locked loops can be making used for frequency synthesizing, carriersynchronization, Carrier recovery, Frequency division, frequency multiplication and frequency Demodulation. A VCO is the compassion of the PLL and shall be designed eitherby LC or RC. A LC VCOs have higher phase noise performance compared with ringvco S. Nevertheless, the LC VCO has a small tuning range for large layout area and probably has higher power. The ring oscillators do not have the problem of the on-chip inductors vital for the LC oscillators. Hence, the chip area is reduced. The phase noise performance of ring oscillators is much poorer in general. In addition, by the side of high oscillation frequencies, the powerconsumption of the ring oscillators possibly will not be low which a key requirement for battery-operated devices is.to resolve these complications, we put effort on single stage source coupled VCO exclusive of using an LC tank circuit. Current work is done with majorintention of reduced power consumption in design of VCOwith different reduction techniques. The main part of this PLL is thescvco, which has been designed to get superior phase noise. II. SYSTEM OVERVIEW The Phase-locked loops (PLLs) generate timely onchip clocks for different applications such as clock and data recovery, microprocessor clock generation and frequency synthesizer. A PLL is a closed-loop feedback system set predetermined phase correlation between its output clock phase and the phase of a reference clock. A PLL follow the phase changes that are within the bandwidth of the PLL. A PLL is a negative feedback control system circuit. As the name means, theintention of a PLL is to generate a signal during which the phase is same compared to the phase ofa reference signal. This is preparedsubsequent to many iterations of comparing the reference andfeedback signals. Overall target of the PLL is to match the phase of the reference and feedback signals during the lock mode then PLL output is constant. After, the PLL prolongs to compare the two signals. A basic form of a PLL consists of four main blocks: 1. Phase Frequency Detector (PFD) 2. Low Pass Filter (LPF) 3. Voltage Controlled Oscillator (VCO) 4. Frequency divider (or) Programmable Counter ( N) III. PLL ARCHITECTURE To synchronize the frequency, different types of PLLs are being used in the application of wireless communication. PLLs are contains of PFD, CP, LPF, SCVCO and frequency divider. This is shown in Fig. 1. In addition to SCVCO and PFD compares feedback signal through input signal and generates the error signal. A charge pump circuit is next to the LPF is used to minimize the conflicts at the input of SCVCO and to get a sharper andflat signal at the SCVCO output. To shape a phase-locked loop (PLL) and the phaseerror output of PFD is provided to a charge pump. Then the low pass filtermixes thesignal to acquire a sharper and smooth signal. Therefore, the conflicts at the input ofscvco get diminished. Page 123

2 Fig.1.The block diagram of PLL 1. PHASE FREQUENCY DETECTOR (PFD) A phase frequency detector (PFD) is a device, which compares the phase of two input signals and provides a signal in the form of phase error. It has two inputs which match upto two different input signals, generally one from a voltage controlled oscillator and other is a reference source. The Schematic Circuit of Phase Frequency Detector (Fig.2) compares the primary edges of data and data1 (data is the input signal and data1 is the feedback signal). If the data1 signal escorts the data, "Up" remains low while the "Down" set off high. From that, the phase difference between data1 and data could be found 2.CHARGE PUMP (CP) A charge pump circuit is used to convert the digital signal from the phase frequency detector to analog signal, the output of which is used to control the frequency of the voltage control oscillator.the schematic of charge pump is shown in Fig.3. Fig. 3: Schematic Circuit of Charge Pump. 3. LOW PASS FILTER (LPF) Fig.2. Schematic Circuit of Phase Frequency Detector. Page 124 Filters are commonly added behind the charge pump to reduce the undulation. The operation of the low pass filter is to translate the output signal of PFD to controlvoltage and too the filter out any high frequency noise established by the PFD. The low pass filter shown in Fig. (4).Which isused with simple RC low-pass filter.as the output of the PFD is oscillating, the output of the low pass filter will demonstrate a

3 ripple as well, even the loop is locked.a high-speed low power consumption positive edge triggered Delayed (D) flipflopwas designed for increasing the speed of counter in Phase locked loop, using 180nm CMOS technology. The Frequency of Oscillation is given as: Initially we have mathematical analysis, Fosc = 1/2. Δt = I d / 4.C. Vth (1) Where, Fosc = the frequency of Oscillation. The average power dissipated by the VCO is, Pavg = VDD. Iavg = VDD. I D (2) An adaptive voltage level circuit could be used either at the upper end of the cell to reduce supply voltage (AVLS scheme) or at the lower end of the cell to raise the potential of the ground node (AVLG scheme). Here applied both AVLS and AVLG techniques simultaneously to the VCO circuit. TheVCO with AVL technique is shown in Fig.6.AVL technique gives better power decrease in evaluation of AVLS and AVLG techniques. Fig. 4: Low Pass Filter. 4. SCVCO WITH AVL (AVLS & AVLG) TECHNIQUE The operation of the SCVCO in Fig 5 is load MOSFETs M3 and M4 pull the output. The MOSFETs M5 and M6 act as constant-current source dropping a current I d. MOSFETs M1 and M2 act as switches. MOSFET M1 is off and M2 is on, since the voltage of terminal out1 is larger than voltage of terminal out2. Hence current during MOSFET M2 is 2 I d and the capacitor will be altered by current Id, because constant current source M6 dropping current I d. When the voltage of X and Y capacitor terminal is same then capacitor is completely charged. The current Id through C, source point X to discharge down towards ground. When point X obtains down, M1 turn on and M2 turns off. 5. FREQUENCY DIVIDER Fig.6: VCO with AVL technique Fig.5: An operation of the SCVCO Frequency divider divides the VCO frequency to generate a frequency, which is comparable with reference Page 125

4 frequency. It divides the clock signal of VCO and then applied to phase frequency detector that compare it with input data.it divides the clock signal of VCO and generate clock as shown in Fig. (7). Fig. 7: Schematic Circuit of Frequency Divider. IV. RESULTS AND WAVE FORMS The PLL based frequency Synthesizer for high performance application have been designed using 180 nm CMOS technology with ma and Simulated by Cadence Virtuoso software.the proposed voltage controlled oscillator has designed for getting optimized 3.2 GHz frequency. A design has been done with 180 nm CMOS technology and 0.7 Volt supply voltage. The final output waveform of complete PLL isshown in Fig. (8). Where, signal1 is for input data signal coming to PFD, signal2 is output of PFD UP signal, signal3 is for output of PFD DOWNsignal, signal4 is output of charge pump, signal5 is output of Low Pass Filter, signal6 isoutput of SCVCO provided two output signal which can compared with both signal, finally gave into one and signal7 is output of frequency dividercircuit that is performing divide by 2 operation which is second input to the phasefrequency detector. Fig. 8: waveforms of different stages of output signal for PLL. Page 126 V. CONCLUSION Modern wireless communication system spend phase locked loop (PLL) mainly onsynchronization clock synthesis, skew and jitter reduction. As to increase ofspeed of the circuit operation, there is required of a PLL circuit with faster locking capability. The PLL has been designed with low power, small chip size area, and high Frequency of oscillation and betterphase noise using 180 nm CMOS technology for High performance PLL and simulated by CADENCE VIRTUOSO environment. While increasing the number of stages for getting thehigher frequency the power dissipation and size of oscillator was going to increase.therefore, instead of increasing the number of stages and time constant again controlvoltage and width of the CMOS can be adjusted for getting the higher frequency. REFERENCES [1] Ajay Kumar Dadoria and Kavita Khare A Novel Approach For Leakage Power Reduction Techniques In 65nm Technologies International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014

5 [2] Amit Tripathi, Dr. Rajesh Nema A Low Power Consumption Single Stage Source Coupled CMOS Voltage Controlled Oscillator (VCO) Using 0.18 μm CMOS Technology International Journal of Emerging Technology and Advanced Engineering, Volume 2, Issue 11, November 2012 [3] Arpit Patel, Rakesh Chaudhari, Sarman K. Hadia, Nilesh D.Patel Wide-Band Current Starved Ring CMOS Voltage Controlled Oscillator (VCO) using 0.18 μm CMOS Technology International Journal Of Engineering Sciences & Research Technology, Volume 3, Issue 5, May, 2014 [4] Behzad Razavi, Deign of Analog CMOS Integrated Circuits, Book by Tata MC Graw-Hil Edition, [5] Ilias Chlis, Domenico Pepe and Domenico Zito Comparative Analyses of Phase Noise in 28nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair Hindawi Publishing Scientific World Journal,Volume 7, No.2, Augest 2014 [10] Rupesh Kumar Patlani, Rekha Yadav Design of Low Power Ring VCO and LC-VCO using 45 nm Technology IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 4, June [11] S. Y. Lee and J. Y. Hsieh, Analysis and implementation of a 0.9V voltage-controlled oscillator with low phase noise and low power dissipation, IEEE Transaction on Circuits and Systems II, vol. 55, no.7, pp , Jul [12] Sheetal Soni, Shyam Akashe Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology International Journal of Computer Applications,Volume 83 No 15, December 2013 [13] Siavash Moghadami, Farzaneh JalaliBidgoli and Arash Ahmadi Analysis and Design LC Cross Coupled VCO Regarding Different Phase Noise Approaches IEEE Transactions on Industrial electronics, May 2013 [6] K. Gnana Deepika, K. Mariya Priyadarshini and K. David Solomon Raj Sleepy Keeper Approach for Power Performance Tuning in VLSI Design International Journal of Electronics and Communication Engineering, Volume 6, Number 1 (2013), pp [7] M. Sai Sarath Kumar, M. Aarthy A 2.8 GHz Low Power High Tuning Voltage Controlled Ring Oscillator International Journal of Engineering and Advanced Technology (IJEAT), Volume-3, Issue-4, April 2014 [8] Mr.Om Prakash, Dr.B.S.Rai, Dr.Arun Kumar Design and analysis of low power energyefficient, domino logic circuit for high speed applications International Journal of Scientific Research Engineering & Technology (IJSRET) Volume 1 Issue12 pp March 2013 [9] Rashmi K Patil, Vrushali G Nasre A Performance Comparison of Current Starved VCO and Source Coupled VCO for PLL in 0.18μm CMOS Process International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 2, February 2012 Page 127