LINEARITY ENHANCEMENT TECHNIQUES FOR WIDEBAND RF FRONT-END RECEIVERS

Transcription

1 LINEARITY ENHANCEMENT TECHNIQUES FOR WIDEBAND RF FRONT-END RECEIVERS by Kihwa Choi A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, Pennsylvania June 009

2 Keywords: RF front-end, receiver, low-noise amplifier, active balun, folded mixer, gain, linearity, noise figure, scattering parameters, intermodulation distortion, second-order input intercept point, third-order input intercept point, linearity enhancement techniques, Volterra series, Taylor series, Volterra kernel, frequency-dependent nonlinearity coefficients, derivative superposition, wideband derivative superposition, self-biasing current reuse technique, DC offset, impedance matching network. Copyright Kihwa Choi, 009 All rights reserved. ii

3 To my wife, daughter, and son for their patience and support iii

4 ACKNOWLEDGEMENTS This thesis would have been impossible without support of many people. I would like to express my sincere gratitude to them, though their invaluable support deserves much more than this short note of appreciation. It is difficult to overstate my gratitude to my advisor Prof. Tamal Mukherjee and Jeyanandh Paramesh. Their enthusiastic and inspirational leadership in research helped me stay on the right track from the moment I changed research topic. Their extensive technical support was definitely far beyond their duty as a thesis advisor. Until then, Prof. C. Patrick Yue guided me to learn how to do research on RF circuit design. Also, I would like to express my gratitude to Prof. L. Richard Carley and Prof. Ramesh Harjani. It was great honor to have them as my thesis committee. Their constructive suggestions made the thesis sound great in many aspects and made the missing essential parts in the thesis filled. I am grateful to my company, Samsung Electronics, for providing me this wonderful chance to do research so that I can catch up with the latest research trend. I would like to really express my gratitude to my parents, brothers, and sister for their faithful support throughout my life. Also, I would like to thank all my colleague students, Abhishek Jajoo, Cheng-Yuan Wen, Gokce Keskin, Jaewon Choi, Jon Proesel, Sandipan Kundu, Shadi Saberi Ghouchani, Umut Arslan, and the other graduate students. Without them, my life and research at Carnegie Mellon University might have been monotonous and dry. Finally, I would like to thank my wife, HoKyoung Kim, for her patience and support, including dedication to our two sweethearts. I dedicate this thesis to her with my love. iv

5 ABSTRACT A multi-standard RF front-end wideband receiver should achieve not only wide bandwidth to support wideband operation, but also high linearity to minimize sensitivity degradation due to in-band intermodulation and cross modulation distortion due to coexistence of strong interference signals. This dissertation addresses both wideband circuit designs and linearity enhancement techniques. First of all, wideband circuit designs are described for RF front-end receivers including low-noise amplifier (LNA), active balun, and down-conversion mixer. The RF front-end receiver is designed for wideband operation, while accommodating low voltage and low power operation. Small supply voltage, needed for scaled CMOS where transistors can operate at multi-ghz frequencies, however, degrades linearity of the RF front-end receiver. The degradation of the second-order distortion is minimized by using fully differential topology in the mixer, but there is still the second-order distortion due to process variation and asymmetric circuit operation, resulting in DC offsets from different mechanisms. The DC offsets in a fully differential circuit are segmented into different categories depending contribution mechanisms. The relationship between DC offset and nonlinearity is derived and the measurement approach of nonlinearity from DC offset is demonstrated with simulated and measured results in the wideband receiver. Linearity requirements are more stringent in multi-standard RF front-end receivers since out-of-band interference signals fall into within operation bandwidth, requiring higher linearity since they cannot be filtered out any longer for multi-standard applications by an off-chip band selection filter. Wideband derivative superposition v

6 (WBDS) and self-biasing current reuse (SBCR) techniques are combined to achieve high linearity even in a low-voltage operation for a wideband LNA. These linearity enhancements are analyzed by the newly introduced frequency-dependent nonlinearity coefficients and conceptual diagrams are shown to provide intuitive understanding about nonlinear behavior of a linearity-enhanced wideband LNA. The coefficients provide more accurate linearity estimation in an initial circuit design phase and enable us to reduce circuit optimization iterations since they can capture the memory effects of FETs such as parasitic capacitances. To confirm the proposed linearity enhancement techniques, the two prototype LNAs with Chebyshev bandpass filter (BPF) and transformer-based input matching networks are designed, and the simulated and measured results of IIP are presented over an operation bandwidth as well as with different frequency spacing of two sinusoidal testtone signals. Furthermore, the measured results of the second-order input intercept point (IIP) of the two LNAs are shown to observe the linearity degradation due to strong inband interference signals in a multi-standard radio depending on frequency allocation and spacing, which have not been addressed in precedent publications. vi

7 LIST OF CONTENTS Acknowledgements... iv Abstract... v Table of contents... ix List of Tables... xii Chapter Introduction.... RF Front-End Receiver.... Issues in Multi-Standard RF Front-End Receivers Motivation Research Contributions Thesis Organization... 9 Chapter Wideband RF Circuit Design Techniques.... Introduction.... Wideband RF Front-End Receiver.... Wideband Low Noise Amplifier Active Balun with Compensation Circuits....5 Low-Voltage Folded Mixer....6 Simulated and Measured Results of the Wideband Receiver Summary... 4 Chapter Wideband Linearity Enhancement Techniques for LNAs Introduction Theory for Nonlinearity Analysis Linearity Enhancement Techniques Summary Chapter 4 Proposed Highly-Linear Wideband LNA Introduction Self-biasing Current Reuse (SBCR) Technique Wideband Derivative Superposition (WBDS) Method Derivation of IIP Expression Using Volterra Series... 8 vii

8 4.5 Summary Chapter 5 LNA Design, Simulated and Measured Results Circuit Design of the Proposed LNA Simulated and Measured Results Summary Chapter 6 Conclusions Suggestions for Future Research... 0 Introduction to Volterra Series and Harmonic Input... Volterra Analysis of the Derivative Superposition Topology... 6 Volterra Analysis of the Wideband Modified Derivative Superposition Topology... 6 Matching Table of Frequency-dependent Nonlinearity Coefficients from HB Analysis... 6 Bibliography... 8 viii

9 TABLE OF CONTENTS Number Page Figure -. Direct-conversion receiver architecture.... Figure -. Architectures of RF front-end receivers for multi-standard applications....6 Figure -. Frequency spectrum and state-of-art IIP....8 Figure -. Receiver block diagram for link budget calculation....4 Figure -. (a) Simplified input matching network of a transformer-based wideband LNA and (b) its equivalent input matching circuit....7 Figure -. Embedded Chebyshev BPF input matching network...8 Figure -4. Shunt peaking network: (a) simplified schematic and (b) its equivalent circuit....0 Figure -5. Wideband LNA with transformer-based input matching network.... Figure -6. A schematic of the active balun with compensation feedback circuit.... Figure -7. Simplified schematic of the folded Gilbert cell mixer....4 Figure -8. Simulated DC offset vs. LO device mismatch....6 Figure -9. Chip micrograph and performance summary...7 Figure -0. Frequency response of CG, NF and IIP....8 Figure -. Effect of supply voltage on CG....9 Figure -. Effect of input stage current density on CG, NF, and IIP....0 Figure -. Effect of LO amplitude on CG, NF, and IIP....0 Figure -4. DC offsets due to different contributors in the mixer.... Figure -5. (a) IIP and IIP extrapolation plot and (b) IF output spectrum...4 Figure -6. The chip micrograph of the receiver with wirebond and COB....5 Figure -7. Comparison of simulated and measured S-parameter S....6 Figure -8. Frequency responses of CG, NF, and IIP....6 Figure -9. DC offsets due to different contributors in the receiver....8 Figure -0. DC offset voltage due to self-mixing with different LO amplitude....9 Figure -. Differential circuit with input-referred offset voltage for relationship between DC offset and nonlinearity....9 Figure -. Nonlinearity of simulated, measured, and calculated results....4 Figure -. (a) A MOSFET transistor, (b) its incremental model including back-gate effect, and (c) simplified equivalent circuit with the assumption that the nonlinearity is weak and memoryless Figure -. Flow chart for the derivation of an IIP derivation...5 Figure -. Line spectrum of the positive frequency terms with two-tone input signals....5 Figure -4. (a) Simplified schematic of a CS amplifier, (b) its DC transfer characteristics, and (c) IIP plots Figure -5. IIP plots with different source degeneration inductances at 0. and GHz Figure -6. (a) Schematic of the derivative superposition method, (b) conceptual diagram of DS and (c) small-signal equivalent circuit Figure -7. Derivative superposition method. (a) st -, nd -, and rd -order power series coefficients of the auxiliary transistor, (b) st -, nd -, and rd -order ix

10 power series coefficients of the main transistor, (c) rd -order power series coefficients and superposition, (d) Calculated IIP dbv....6 Figure -8. IIP plots in different frequencies with 0. nh source inductance....6 Figure -9. (a) Schematic of the modified DS method and (b) conceptual vector diagram Figure -0. (a) Schematic of the alternative DS method and (b) conceptual diagram Figure 4-. (a) Simplified common-source amplifier and (b) IIP vs. V ds....7 Figure 4-. The effects of voltage headroom on IIP: (a) simplified schematic and (a) IIP vs. Vds plot Figure 4-. LNA schematic with the self-biasing current reuse technique of the redcolored portion Figure 4-4. (a) Node voltages and (b) currents in the LNA with the SBCR technique Figure 4-5. Conceptual diagram of linearity behavior over an operating frequency (a) at the low-frequency optimized topology, (b) at the high-frequency optimized topology, and (c) the resulting IIP plot Figure 4-6. LNA schematic with wideband derivative superposition (WBDS) method Figure 4-7. Polar plot of the frequency-dependent nonlinearity coefficients as a function of frequency Figure 4-8. Conceptual vector diagram with SBCR and WBDS techniques (a) at low frequency and (b) at high frequency....8 Figure 4-9. (a) Simplified LNA schematic with SBCR and WBDS techniques and (b) its equivalent circuit....8 Figure 5-. Input matching network (a) Chebyshev BPF matching (b) transformerbased matching...86 Figure 5-. Distributed gate capacitance and channel resistance at high frequencies Figure 5-. Simplified schematic of linearity-enhanced wideband LNAs Figure 5-4. First-, second-, and third-order DC transfer coefficients of (a) the auxiliary and (b) main transistors, (c) third-order coefficients and superposition, (d) calculated IIP dbv in the proposed topology....9 Figure 5-5. Chip micrographs of the proposed LNAs with (a) transformer-based and (b) Chebyshev BPF input matching networks....9 Figure 5-6. Simulated and measured results of the designed LNA (a) with transformer-based matching network and (b) with Chebyshev BPF matching network....9 Figure 5-7. Parallel RC load impedance for Bode-Fano limit Figure 5-8. NF and NF opt of the LNA with Chebyshev matching network Figure 5-9. NF comparison of the LNA with transformer-based matching with or without the SBCR Figure 5-0. Noise summary of the devices in the LNA with Chebyshev BPF matching Figure 5-. IIP vs. gate bias voltage at 4GHz in the LNA with Chebyshev BPF input matching network Figure 5-. IIP extrapolation plot at 4GHz in the LNA with Chebyshev BPF input matching network...99 x

11 Figure 5-. IIP plot over frequency range in the LNA with transformer-based input matching network Figure 5-4. Simulated and measured IIP (a) vs. frequency range and (b) vs. frequency spacing plots in the wideband LNAs with transformer-based matching and with Chebyshev BPF matching....0 Figure 5-5. IIP vs. frequency spacing plots of (a) transformer-based matching and (b) Chebyshev BPF matching LNAs at different reference frequencies....0 Figure 5-6. IIP vs. frequency plots of (a) transformer-based matching and (b) Chebyshev BPF matching LNAs at different nd -order IMD frequencies....0 Figure 5-7. Mechanism of IMD tones depending on frequency spacing Figure 5-8. IIP vs. frequency spacing plots of transformer-based matching (a)-(c) and Chebyshev BPF matching (d)-(f) LNAs at different nd -order IMD frequencies with different reference frequencies Figure 6-. IIP comparison plot with narrowband and wideband LNAs xi

12 LIST OF TABLES Number Page Table. IIP requirements of several standards... 5 Table. Component values of Chebyshev BPF and transformer-based matching networks Table. Component values of the designed wideband LNA prototypes Table 4. IIP comparison with narrow band and wideband LNAs xii

13 Chapter Equation Chapter Section Introduction As wireless telecommunication services are proliferating across the world, more demands for both a new standard and multiple standards seem uprising rapidly to satisfy the end users who want to access an increasing number of services from a single handset regardless of geographical region []. This leads to ubiquitous wireless connectivity that supports multiple standards across multiple frequency bands []. Minimizing the number of external components and highly integrated solutions in low-cost CMOS technologies are the keys when the same mobile handset supports multi-standard services. Zero-IF or direct-conversion receiver architecture is most suitable for the high-level integration for multi-standard RF receivers. One of the key challenges for multi-standard RF receivers is how to achieve high linearity and low noise over a wide frequency range [].. RF Front-End Receiver One of the key components for wireless telecommunication systems is the RF frontend receiver which receives both wanted and interference signals. It filters out the unwanted out-of-band signal out, and amplifies the received weak signal with low noise, and then downconverts the amplified signal into a baseband signal, with subsequent filtering, amplification and dizitization, as shown in the direct-conversion receiver

14 architecture of Figure -. Gain, noise, and linearity should be carefully taken into account in each block of the receiver to deliver desired communication quality when the receiver is designed, while making a circuit implementation feasible in a given technology. The importance of these three design parameters is described below. BPF LNA Balun Mixer LPF VGA ADC I 0 90 LO Q Figure -. Direct-conversion receiver architecture. The received signal can be very weak since the transmitted signal will experience attenuation due to spatial separation between the transmitter and the receiver or due to objects located on the signal path. The signal has to be amplified such that it has large enough amplitude to be digitized correctly while providing a required signal-to-noise ratio (SNR) at the input of an analog-digital converter (ADC). Since the received signal is weak, the noise generated in the RF front-end receiver must be minimized the degradation of the receiver sensitivity. A low-noise amplifier is typically implemented to reduce noise caused by the losses of the input matching network and the noise of the amplifying devices. The received signal can include unwanted out-of-band signals with large amplitude. These unwanted signals can be filtered out by a band selection filter of an RF front-end receiver. Therefore, linearity requirements for the out-of-band interference signals can be

15 alleviated at the cost of using the band selection filter. Most of RF front-end receivers have dedicated hardware for multiple standards with multiple band selection filters. Accordingly, high linearity is not necessarily required in a conventional narrowband receiver unless the filtered out-of-band interference signals are so strong that they can deteriorate the linearity of the receiver. However, the co-existence of multiple standards in the same cell area creates a hostile jamming environment for multi-standard wideband receivers. These interference signals degrade the receiver sensitivity and thus can cause the handset to drop the call. Thus higher linearity is demanded to guarantee the required sensitivity in the hostile environment, compared to a single standard receiver. In general, a RF front-end receiver consists of a low-noise amplifier, balun, and mixer. In the receiver, a single-ended LNA topology is preferred since it can reduce I/O pins and power consumption while providing easy interconnection between the single-ended antenna or RF filter and LNA. On the other hand, a differential topology in the subsequent devices such as a mixer and a variable gain amplifier as shown in Figure - is preferred not only to minimize the second-order distortion but also to reject power supply and substrate noise [4]. Therefore, a balun is required to convert the single-ended signal of the LNA into the differential signal for the mixer in the receiver. For implementation of the balun, a passive or active balun can be chosen depending on the receiver link budget in the system level design. An active balun is preferred to alleviate the gain requirement in the subsequent stage as well as the NF requirement in the previous stage. To facilitate low-voltage operation, a folded Gilbert cell mixer [5] or a passive mixer is preferred to a conventional Gilbert cell mixer since it has three stacked transistors and one load resistor.

16 . Issues in Multi-Standard RF Front-End Receivers There are mainly two approaches to satisfy requirements of multi-standard RF frontend receivers: ) parallel combination of a narrowband receiver and ) a single tunable or wideband receiver. The single chip solution is more flexible and efficient in terms of area, power, and cost. The key components in achieving the RF requirements of multiple standards with a fully integrated single chip solution are an LNA with low noise, a mixer with a very high dynamic range, and a careful control of DC offset [6]. For the key components of multistandard RF front-end receivers, wide bandwidth, low noise, and high linearity are important design parameters to achieve RF requirements. As a CMOS technology scales down, the noise and bandwidth performance of RF front-end improves, but unfortunately the linearity performance degrades with supply voltage reduction and high-field mobility effects [7], [8]. On the contrary, the required linearity becomes higher due to the coexistence of adjacent blockers from multiple standards, which were filtered out by a band selection filter in a narrowband front-end receiver. In other words, since the co-existing blockers within an operating wide bandwidth experience intermodulation and crossmodulation without out-of-band filtering, higher linearity is inevitably required to support multiple standards in a single chip solution. Furthermore, the second-order intermodulation products are becoming a critical contributor of nonlinearity even in an amplifier before downconversion in a mixer since the IMD terms which fall out of the operating bandwidth in a narrowband amplifier fall within the in-band in a wideband amplifier and thus deteriorate linearity along with the third-order intermodulation terms depending on frequency spacing between interference signals. 4

17 To evaluate the required performance of RF blocks for multi-standard applications, the receiver (Rx) link budget calculation can be performed using cascade equations for gain, NF, and IIP, based on the system-level performance requirements. The required IIP for several narrowband and wideband standards is summarized in Table. As described above, the IIP requirement for multi-standard front-end receivers is expected to be much higher than that for each receiver. For example, the IIP requirement for multi-standard receivers has to be at least greater than the highest IIP among the standards, i.e., 0 dbm and + dbm for LNA and mixer, respectively. Table. IIP requirements of RF blocks in several standards. Standard Receiver IIP [dbm] LNA IIP [dbm] Mixer IIP [dbm] UMTS [] WLAN 80. a/b/g [] -6* WiMAX 80.6 e [9] UWB (Group ) [0] Multiband receiver [] * high gain mode. Motivation As we can see in the upper figure of Figure -, multiple-dedicated RF front-end circuits are necessary to support different standards. The single chip solution as shown in the lower figure of Figure - is preferred due to its compact size and possible reconfigurability between standards. On top of wideband circuit design, the key challenge in the design of the single-chip, multi-standard RF front-end is to achieve high linearity 5

18 without out-of-band filtering since multiple blockers from different communications coexist within an operation bandwidth and thus deteriorate linearity due to crossmodulation and intermodulation. Figure -. Architectures of RF front-end receivers for multi-standard applications. As the part of a low-voltage wideband RF front-end receiver, the wideband folded mixer was designed in [5] to facilitate low-voltage operation with 0.8.-V supply. The designed mixer showed reasonably competitive performance over 7 GHz bandwidth even under 0.8-V power supply. Along with this folded wideband mixer, the wideband RF front-end receiver with an active balun was designed in [] such that it achieved relatively wideband operation over 5 GHz bandwidth while achieving high secondorder linearity and low DC offset by adopting a fully differential topology after the 6

19 wideband LNA. However, the RF front-end receiver showed low linearity performance due to both low supply voltage and degradation of linearity by IMD contribution on the IIP. According to the previous research [] and system-level link budget calculation, the required IIP in a mixer should be much higher than that in a LNA since interference signals are amplified in the LNA, with deteriorating IMD terms further in the following stages. For example, for multi-standard receiver [], the required IIP in the mixer as shown in Table is db higher than that in the LNA. To understand why the wideband receiver in [] has low IIP even though the mixer IIP is not as low as to degrade the receiver IIP, further analysis and simulation are performed. It turned out that the linearity of the LNA and active balun was not so high due to low supply voltage as well as IMD contribution on the IIP. To achieve high linearity in the wideband receiver, some survey has been performed including precedent narrowband linearity enhancement techniques for LNAs, as described below. To support multiple standards, wide bandwidth and high linearity are required for different frequency coverage as shown in the frequency spectrum plot of Figure - along with IIP versus frequency plot for state-of-art LNAs. The square marks represent IIP of narrow band LNAs and the circle marks represent IIP of wideband LNAs. The reference circled with red dotted line used linearity enhancement techniques to achieve such a high IIP for a narrow band LNA and wideband LNA. While numerous techniques have been proposed for increasing LNA bandwidth (e.g., [0], []), there have been relatively few studies of linearity enhancement in wideband LNAs. For example, [4] and [] employ noise and distortion cancellation techniques to 7

20 achieve an IIP of about 0 dbm for small frequency spacing at 0.8. GHz and GHz while consuming a large amount of power of 7.4 mw and mw, respectively. In the design of highly-linear wideband RF front-end receivers, linearity enhancement and wideband circuit techniques should be incorporated and implemented simultaneously while minimizing power consumption for high mobility of handsets. Linearity Enhancement Techniques () J. Lee, MTT 006 () A. Ismail, JSSC 004 () A. Bevilacqua, JSSC 004 (4) D. Mukherjee, RAWCON 00 (5) V. Aparin, MTT 005 (6) S. Ganesan, MTT 006 (7) C. Kim, JSSC 005 (8) S. Blaakmeer, JSSC 008 (9) F. Agnelli, CAS 006 (0)A. Amer, CAS 007 Figure -. Frequency spectrum and state-of-art IIP..4 Research Contributions The contribution of this research is to provide the techniques to implement both a wideband RF front-end receiver and a linearity-enhanced wideband LNA, in conjunction with analyzing DC offset, nonlinearity behavior, and the relationship between DC offset and linearity. The details of contributions are described below: ) Designed the wideband RF front-end receiver including a LNA, active balun, and mixer. 8

21 ) Demonstrated how to segment DC offsets caused by different DC offset mechanisms in a differential circuit, showed the relationship between DC offset and nonlinearity, and quantified the relationship by simulated, calculated, and measured results in the wideband RF front-end receiver. ) Proposed a linearity-enhanced wideband LNA topology. 4) Analyzed how linearity over the wide frequency range is improved with a wideband derivative superposition method using newly introduced frequencydependent nonlinearity coefficients in the proposed LNA topology. 5) Designed linearity-enhanced wideband LNA prototypes and verified the effectiveness of the proposed linearity-enhanced wideband LNA topology..5 Thesis Organization Chapter describes the design of a low-power wideband RF front-end receiver. First, receiver architectures are described and then the link budget calculation is explained to define the requirements of the receiver building blocks such as an LNA, active balun, and mixer. Second, wideband LNA topologies are introduced and then a proper topology for the wideband LNA is chosen. As a part of design for a wideband RF front-end receiver, matching networks are described for the design of the wideband LNA. Third, the design of the active balun and low-voltage folded mixer are described to complete the wideband RF front-end receiver. The detailed analysis is shown for the mixer with simulated and measured results. Fourth, the simulated and measured results of the wideband RF frontend receiver are shown with frequency responses, receiver DC offset, linearity, and the relationship between DC offset and linearity. 9

22 Chapter describes theories for nonlinearity analysis including DC and frequencydomain theories. Then some limitations of precedent analysis approaches are addressed and the frequency-dependent nonlinearity coefficients are newly introduced to capture memory effects of a MOSFET. The state-of-art linearity enhancement techniques are presented to provide the understanding of distortion cancellation using Volterra series as well as to address the limitation of those narrow band techniques. Chapter 4 describes two proposed linearity enhancement approaches. One is the wideband derivative superposition (WBDS) which makes IMD terms cancelled with IMD terms at two frequencies such that IIP has two peaks over an operating frequency bandwidth. The other one is the self-bias current reuse (SBCR) technique which bleeds some amount of current directly to an RF input transistor with self-biasing such that the voltage headroom problem in a deeply-scaled CMOS technology can be alleviated even under low supply voltages. Conceptual diagrams of nonlinearity cancellation are shown with both derived IIP expression and newly introduced frequency-dependent nonlinearity coefficients to provide insight how two IIP peaks can be achieved over wide operating bandwidth in the proposed LNA topology. Chapter 5 describes the prototype implementation of two linearity-enhanced wideband LNAs using the proposed LNA topology. Two wideband LNAs are implemented in a 0. μm CMOS technology and the simulated and measured results are presented to confirm the effectiveness of the proposed topology. Chapter 6 concludes with a summary as well as suggestions for future research. 0

23 Chapter Equation Chapter (Next) Section Wideband RF Circuit Design Techniques. Introduction Several wireless standards have been used for their own communication services with dedicated RF front-end receivers. The straight solution for multiple standards employs parallel narrowband receivers at the expense of die area. A key factor for successful design of multi-standard wideband systems is a low-power wideband RF front-end receiver across multiple frequency bands in a single chip while meeting RF performance requirements in a wideband LNA, an active balun, and a down-conversion mixer. To design a compact low-power wideband receiver, the design of a 5-GHz CMOS wideband RF front-end receiver is presented with an LNA utilizing a transformer matching network, an active balun with compensation feedback, and a low-voltage folded mixer. To achieve low-power operation and to realize a compact input matching network, the LNA utilizes transformer-based input matching. The active balun is adopted to convert single-ended signal into double-balanced one while alleviating gain and NF requirements in the following stage and in the previous stage, respectively. To facilitate low-voltage operation, the folded mixer is employed. For measurement of the wideband receiver, a chip is attached on a PCB board using Chip-On-Board (COB) with bond wires.

24 The relationship between DC offset, IIP, and IIP is derived and confirmed by simulated, calculated, and measured results. With this approach, nonlinearity in mass production line can be estimated accurately and promptly without expensive RF measurement facilities. While a number of wideband RF front-ends have been reported, detailed circuit analysis and optimization have been limited to wideband LNA designs. The design of wideband mixers has not been studied extensively except in []. The distributed mixer achieves wideband performance at the expense of large die area and high power consumption. Another important requirement for the wideband mixer is low-voltage operation to facilitate integration of the RF transceiver and the baseband DSP using scaled CMOS processes. Low-voltage mixers using a folded Gilbert cell topology have been proposed in [4], [5]. However, these designs are limited to narrow-band operation owing to the use of LC-tank for biasing. To facilitate low-voltage operation, the mixer employs a folded Gilbert cell topology with PMOS devices for LO switches and utilizes on-chip broadband RF chokes for biasing. Detailed DC offset analysis in a mixer is shown in the following section [5] and receiver nonlinearity is calculated based on the measured DC offsets and then compared to the measured results. In Section., the wideband RF front-end receiver is described on top of receiver architectures and Rx link budget calculation. The implementation of the wideband lownoise amplifier is described in Section. along with matching networks, followed by the design of the active balun in Section.4 and the design of the low-voltage folded mixer in Section.5. The simulated and measured results of the wideband receiver are shown in

25 Section.6. Finally, the wideband circuit design techniques are summarized in Section.7.. Wideband RF Front-End Receiver.. Receiver Architectures The main categories of the RF front-end receiver architectures are heterodyne and homodyne [6]. The heterodyne receiver is widely used for current wireless applications since it achieves high performance requirements without limitations. However, it requires an external image rejection filter and thus more components are required, resulting in more area and power consumption. On the other hand, the homodyne receiver also called the direction conversion or zero IF receiver has no image problem and thus needs no external band selection filters. This architecture is more promising for high level integration. However, the direction conversion architecture has some drawbacks [7]: DC offset, /f noise, I/Q mismatch, even-order distortion, and LO leakage. In this Chapter, the direct conversion receiver architecture is chosen to implement a compact low-power wideband RF front-end receiver... Receiver Link Budget Calculation When a RF front-end receiver is designed with several RF building blocks, an Rx link budget calculation is mandatory in the receiver design such that each block can reasonably share the performance requirements by determining the feasibility of any given blocks. The link budget calculation is also an excellent means for anyone to begin to understand the various factors which must be traded off to realize a given area, cost, feasibility, and level of reliability for a communications link.

26 In the RF front-end receiver, the total gain, NF, and IIP of the receiver (G total, NF total, and IIP total, respectively) are calculated by the cascade equations of (.)-(.4) where g, g,, g n are the linear gain of each stage, nf, nf,, and nf n are the noise factor of each stage, and iip,, iip,,, iip,n are the linear IIP of each stage, as shown in Figure -. ( ) G [ db] = 0log g g L g (.) total n NF db = nf nf + nf + + L+ nf n total [ ] 0log g gg ggl gn (.) IIP g g g n total [ dbm] 0log L + iip, iip, iip, iip (.), n gg Lg g g g gglg n IIP total [ dbm] 0log L + (.4) iip, iip, iip, iip, n g nf iip iip,, g nf iip iip,, g nf iip iip,, g 4 nf 4 iip iip,4,4 g 5 nf 5 iip iip,5,5 Figure -. Receiver block diagram for link budget calculation... Wideband RF Front-End Receiver Design The design of a 5-GHz CMOS wideband RF front-end receiver is performed with an LNA utilizing a transformer matching network, an active balun with compensation feedback, and a low-voltage folded mixer. To achieve low-power operation as well as to realize a compact input matching network, the LNA utilizes transformer-based input 4

27 matching. The active balun is adopted to convert single-ended signal into doublebalanced one while alleviating gain and NF requirements in the subsequent stage and in the previous stage, respectively. To facilitate low-voltage operation, the mixer employs a folded Gilbert cell topology with PMOS devices for LO switches and utilizes on-chip broadband RF chokes for biasing. For measurement, a chip is attached on a PCB board using Chip-On-Board (COB) with bond wires. The RF front-end consumes 9. mw from a.-v supply. The receiver achieves a CG of 8.5. db, a single-sideband NF of db, an IIP of. 9. dbm, and an IIP of 8. to.7 dbm between 5 GHz. Relationship between DC offset, IIP, and IIP is derived and confirmed by simulated, measured, and calculated results. The calculated IIP and IIP based on measured DC offsets have relatively better match with measured IIP and IIP results, compared to the simulated ones. With this approach, nonlinearity in mass production line can be estimated accurately and promptly without expensive RF measurement facilities.. Wideband Low Noise Amplifier.. Wideband LNA Topologies Among wideband LNAs, the distributed amplifiers [8] absorb all circuit parasitic capacitances by incorporating on-chip transmission lines and provide wide bandwidth at the expense of delay. These LNAs demand high-quality transmission lines, making them less attractive to low-cost on-chip solutions due to the large chip area. The resistive feedback amplifiers [9] can achieve wideband input matching, reducing the NF by the local feedback with a feedback resistance and high voltage gain. However, large power consumption is required to obtain a high loop gain in a single stage due to the inherently low transconductance of a CMOS transistor, while stability will be caused with multiple 5

28 stages. For moderate chip solutions in terms of area and power consumption, the ladder network [0] and Chebyshev BPF network [0] amplifiers are proposed with multisection reactive networks so that the overall input reactance is resonated out over a wide bandwidth. Another benefit of the LNA employing the Chebyshev BPF network is that the topology can incorporate with linearity enhancement techniques addressed in Section.... Matching Networks In this sub-section, a transformer-based input matching and Chebyshev BPF input matching networks are analyzed to show how a wide bandwidth can be achieved with a multi-section reactive network and a transformer. In addition, the shunt-peaking output load network widely used in a wideband LNA is explained to address its limitation on linearity enhancement techniques in Section 4.. A. Transformer-based Input Matching Network [] For a moderately wide bandwidth with a relatively small chip area, the transformerbased input matching network is proposed. Figure - (a) shows the simplified input matching network of the transformer-based wideband LNA and Figure - (b) represents its equivalent circuit. 6

29 (a) (b) Figure -. (a) Simplified input matching network of a transformer-based wideband LNA and (b) its equivalent input matching circuit. With the assumption that k M / LL = is as close to as to neglect ( ) Figure - (b), the input impedance of the LNA is given by k L in sk L ( + sω C L + s C L ) Zin() s = + sωcl + s( CL + nkcl) + sk CCLL + (.5) skccll T T s T s 4 T T s T s T ωt T p s T p s where n is the turn ratio of the primary and secondary coils, k the coupling coefficient, C T the total gate-source capacitance of the LNA input transistor, and ω T the unity-gain frequency of the input transistor. As written in Eq. (.5), the input matching networks have two complex poles at the frequency smaller than the lower frequency of the target bandwidth and two complex poles at the frequency greater than the higher frequency of the target bandwidth, respectively. In addition, it has one zero at DC and one complex zeros at the center frequency of the target bandwidth, ω T ± 4/ ωt CL T s /4π, such that the LNA has wideband input matching by arranging four complex poles and one complex zero. B. Input Matching Network Using LP-to-BP Filter Transformations 7

30 The input matching network using LP-to-BP filter transformations shown in Figure - expands the use of an inductively degenerated common-source amplifier by embedding the input network in a multi-section reactive network so that the overall input matching network is resonated over a wide frequency range [0]. The parasitics of the input device are embedded as the part of input matching networks. Figure -. Embedded Chebyshev BPF input matching network. The input impedance of the MOS amplifier with a source degeneration inductor is written as in Eq. (.6) Z s = s L + L + + L (.6) ( ) () g S ωt S sct where C T is the equivalent gate-source capacitance, L g the gate inductance, L S the source degeneration inductance, and ω T the unity-gain frequency of the NMOS amplifier. The gate-drain capacitance C gd is not taken into account due to the complexity of the equation. The π-network topology in Figure - is chosen to achieve sharp out-of-band cutoff characteristic by employing Chebyshev LP-to-BP transformations. For filter termination and input impedance matching, the real part of the input impedance Z (s) is ideally determined to be equal to the source resistance, that is, ω T L S =R S. Ideally the power loss in the filter passband is 0 db with a ripple. Based on the bandwidth and in-band ripple, 8

31 the reactive components of the filter, C C and L L, are determined. The parasitics of input devices are embedded as the part of input matching networks. The input impedance of the amplifier including the π-network filter structure is derived as shown in Eq. (.7). Z in ( ) 4 ( ) 4 z+ zs s + + zs + z4s slz ( s) ( s) = 4 6 s p+ ps + ps + + p4s + p5s + p6s Z( s) (.7) where z = LL, z = CLL L, z = CL + CL + CL, z4 = CCL L, p = L, p = CLL + CLL + CL L, p CC LL L =, p ( + ) + L + ( C + C ) = C C L C L, 4 = CCL( L + L) + CCLL + CCL( + ), and p6 = CCC LL L. Ideally with the p L L 5 assumption that the real part of the Z () s is equal to R S, the input matching network has one zero at DC, four complex zeroes, and 6 poles such that it provides wideband input matching by arranging the poles and zeros properly at the expense of an in-band ripple. C. Wideband Output Load Network: Shunt Peaking In addition to a wideband input matching network, the output load network should be designed properly to achieve flat gain over a wide frequency range. One of the most popular peaking techniques, the shunt-peaking technique as shown in Figure -4 is applied. By adding an inductance in series with a load resistor, the impedance looking into the load introduces a zero at ω = R / L and thus increases with frequency. The z d d increasing impedance compensates the offset of the decreasing impedance due to the parasitic capacitance of the following stage, resulting in constant load impedance over a wide frequency range. The behavior of the shunt-peaking load can be interpreted with the time-domain view. Since the inductor delays current flow through the resistor, the 9

32 capacitor can be charged fast due to more available current. Faster charging time means a shorter rising time, that is, can be interpreted the wider bandwidth. (a) (b) Figure -4. Shunt peaking network: (a) simplified schematic and (b) its equivalent circuit. The output impedance Z () s in Figure -4 (b) is written by Z out () s = ( ) out R s L / R (.8) d d d slc d par src d par To obtain an optimum inductance value, a factor m is introduced and defined as the ratio of the Rd C par and L / R time constants []: d d RC d par m =. (.9) L / R d d To maximize the bandwidth, m should be approximately.4, resulting in extending the bandwidth to.85 times wider than the uncompensated bandwidth. On the other hand, the shunt-peaking inductance L d is determined by two opposite requirements [0]: the 0

33 inductance L d should be large to have large gain, and it should be small to resonate with the load parasitic capacitance added by the parasitic of the following stage such as a mixer in a receiver and a buffer amplifier for test purpose out of band. The load resistance R d is determined so that the zero frequency is located closely to the lowest operating frequency to compensate the gain decreased abruptly at the low frequencies. Usually the largest load resistance is chosen to achieve high gain, but it limits the voltage headroom, resulting in degrading linearity that will be addressed in detail in Section Implementation of LNA with Transformer-Based Matching Network Figure -5 shows the simplified schematic of the LNA with transformer-based input matching network of the previous sub-section... To achieve high gain and large reverse isolation, a cascode topology is employed with the source degeneration inductor Ls to realize 50-Ω real input impedance. The external gate-source capacitance C d is added to reduce the gate inductance value required for input match since the gate-source capacitance of the transistor M is usually small. The use of the degeneration inductor poses inherent narrowband input match due to narrowband resonance in the equivalent series RLC resonant circuit. These series RLC circuits are embedded as the part of an input matching network with the transformer (L, L ) and shunt capacitor (C p ). The detailed analysis of the input matching network is described in the sub-section...

34 VDD Rd Ld LNAout Rs Vs Vin Cp L k Cc L VBS Cd M 8μ / 0.μ M 56μ / 0.μ Ls Figure -5. Wideband LNA with transformer-based input matching network..4 Active Balun with Compensation Circuits Fully differential circuits are preferred in mixed-signal chip design as balanced circuits have advantages of keeping common mode substrate noise from high speed digital circuits at a minimum level. The direct conversion receiver suffers from the second-order distortion like low IF. To overcome those issues, fully differential RF circuit techniques have been employed in the following stages after the single-ended LNA. Baluns are basic elements required in RF components such as balanced mixers and phase splitters to convert single-ended input signal into differential output signal []. There are two different types of baluns: passive baluns by passive LC networks and active baluns by differential amplifiers. Since passive baluns occupy large chip area and are lossy, an active balun is adopted in this design while alleviating gain requirement in the LNA and NF requirement in the mixer. If a differential amplifier has infinite impedance at the drain

35 node of the tail current source M 7 in Figure -6, differential amplifier can provide equal amplitude and 80 phase difference. Due to finite impedance and parasitics at higher frequencies, good gain and phase balance are not achievable. In order to compensate gain and phase imbalance, a fraction of the single-ended signal is fed back to the input transistor M 4 through a series RLC network as shown in Figure -6. The detailed design is shown in the schematic of Figure -6. VDD 50Ω M5 64μ / 0.μ RF+ RF- 50Ω M6 64μ / 0.μ 88Ω 0.8pF nh LNAout M Rbias M4 μ / 0.μ 0KΩ μ / 0.μ VBS M7 0μ / 0.5μ Figure -6. A schematic of the active balun with compensation feedback circuit..5 Low-Voltage Folded Mixer This section presents the design and analysis of a low-voltage downconversion mixer in 0.-μm CMOS for wideband applications between 7 GHz. To facilitate low-voltage operation with 0.8.-V supply, the mixer employs a folded Gilbert cell topology with PMOS devices for LO switches and utilizes on-chip broadband RF chokes for biasing. The folded topology allows the transconductance and LO stages to have different bias

36 current. By setting the bias current in the PMOS switches near zero, the mixer DC offset due to device mismatch is greatly reduced. The effect of supply voltage on the mixer performance is studied. The wideband frequency responses of the mixer performance under different supply voltages are studied in detail. To achieve high performance with low power consumption, DC bias current density and LO amplitude are optimized based on experimental data. DC offsets due to different sources are measured methodically to analyze their relative importance..5. Folded Mixer Circuit Design The schematic of the folded, double-balanced mixer is shown in Figure -7. The NMOS differential pair, M and M, forms the input transconductance stage (g m -stage). The PMOS LO switches, M through M 6, are folded with respect to the g m -stage. VDD L=5.4 nh Rs=8.4 Ω L=5.4 nh Rs=8.4 Ω RF+ IF- RL 480Ω LO- RF- LO+ M M M M 4 M 5 M 6 6μ / μ / μ / 0.μ 0.μ 0.μ LO+ Vbias M7 0μ / IF+ 0.5μ RL 480Ω Rbias Rbias Rbias Rbias RFdc LOdc Figure -7. Simplified schematic of the folded Gilbert cell mixer. 4

37 This technique is effective in 0.-μm technology because PMOS devices with moderate W/L are sufficiently fast to completely steer the current from the gm-stage to the LO switches with reasonable LO amplitudes. The folded topology offers a key advantage over the standard stacked topology for allowing independent settings of the bias currents through the g m -stage and LO switches. The bias current for the gm-stage should be high enough to achieve the desired CG, NF, and IIP. However, the bias current through the LO switches should be minimized to suppress DC offset, thermal and /f noise. The V gs of the LO switches is set near V t to achieve a low bias current (~50μA) and at the same time ensure that the required LO amplitude remains at a reasonable level (~00 mv pp ) for complete current commutation. The small bias current in the LO switches also allows the usage of large load resistances (R L = 480 Ω) to increase the CG without consuming large IR drop from the limited voltage headroom. The RF chokes, L and L, present a high impedance from to 7 GHz such that the output AC currents of the gm-stage will flow into the LO switches. The RF chokes are realized using two inductors rather than one differential inductor to achieve higher self-resonance frequency (SRF) and hence wider operating bandwidth. The series inductance and resistance of the RF choke are 5.4 nh and 8.4 Ω, respectively. The RF choke has a SRF of 0.8 GHz due to its parasitic shunt capacitance which is 40 ff. The DC offset in mixers is a critical parameter for direct conversion receivers since most of the gain occurs after the downconversion of the input signal and the receiver can be saturated if the offset is too large. Static DC offset can be caused by device mismatch, LO self-mixing due to LO-to-RF leakage, and secondary nonlinearity. Mismatch in the LO switches and load resistances is usually a major contributor to DC offset in fully 5

38 balanced mixers. Figure -8 shows the simulated DC offset voltage at the IF output port versus the LO device mismatch percentage for both the proposed folded mixer and a standard Gilbert cell mixer. The folded mixer is simulated with two LO bias current levels at ~0 and 44 μa/μm. As expected, the DC offset voltage due to mismatch decreases with the low bias current level. Since the folded mixer can have nearly zero LO bias current and still functions properly, the IF output DC offset is suppressed to mv even with a 0% device mismatch. In contrast, a standard Gilbert cell mixer with the same device mismatch exhibits a DC offset of more than 40 mv. The higher DC offset voltages of the folded mixer at the same current density is caused by larger load resistance value. For example, the load resistance is around 50 Ω in the Gilbert cell mixer, but 480 Ω in the folded mixer, causing larger voltage drop across the load resistor. The detailed analysis of the different sources for static and dynamic DC offsets will be presented with measured data in the next section. DC Offset Voltage [mv] Device Mismatch Percentage [%] Figure -8. Simulated DC offset vs. LO device mismatch. 6

39 .5. Simulated and Measured Results of the Folded Mixer The chip micrograph and performance summary are shown in Figure -9. The active area is 60x80 μm. The layout of the mixer uses pre-characterized components from an in-house RF parameterized cell (P-cell) library for accurate device and interconnect model []. The layout is fully symmetrical in order to reject common-mode noise and to minimize phase and amplitude imbalance in the differential signal paths which can degrade CG, linearity, and port-to-port isolation. All signal paths are shielded from each other to improve port-to-port isolation. The measurements are performed using an Agilent E4440A spectrum analyzer. Cascade SGS probes with external 80 hybrids are used for supplying the RF and LO signals. A high-impedance differential active probe (Agilent N05A) is used for measuring the IF signals. Technology Active area Power Frequency CG NF IIP IIP DC offset 0.-μm CMOS 60 μm 80 μm 5.8 mw at. V GHz db db dbm. 0. dbm.4 4. mv Figure -9. Chip micrograph and performance summary 7

40 A. Frequency Response The measured frequency responses of the mixer CG, NF, and IIP under a.-v supply are shown in Figure -0 along with simulation results. The dotted line and solid line represent the simulated and measured performance, respectively. Good agreement between simulation and measurement is achieved due to the accurate modeling of the device and layout parasitics as well as the test setup including the off-chip hybrids. Both CG and NF exhibit the best performance, 7.8 db and 9.7 db, respectively, near 5. GHz where the effective choke impedance reaches its peak value. The IIP is recorded between. to 0. dbm and does not show a strong frequency dependency since it is predominately determined by the input transconsductance which does not vary significantly with frequency. CG [db] NF [db] IIP [dbm] CG IIP NF Frequency [GHz] Figure -0. Frequency response of CG, NF and IIP. B. Performance vs. Biasing and LO Amplitude Next, the effects of supply voltage on the mixer performance are studied. The frequency responses of the CG at 0.8-V, -V, and.-v supply are compared in Figure 8

41 -. As the supply voltage reduces from. V to 0.8 V, the CG is degraded by an average of.5 db. However, the NF and IIP remain relatively the same with less than db of degradation on average over the entire frequency range of 7 GHz. This illustrates that the folded mixer is a robust topology for low-voltage operation. CG [db] CG Measured at VDD=.V CG Measured at VDD=.0V CG Measured at VDD=0.8V Frequency [GHz] Figure -. Effect of supply voltage on CG. The biasing conditions for the input g m -stage have a major impact on the mixer performance and therefore must be optimized. Figure - shows that the CG, NF, and IIP improve with increasing bias current density and then saturate as the input transconductance starts to degrade due to velocity saturation at high current density. For this design, the optimal bias current density is 5 μa/μm and further increases merely consume more power without any performance improvements. The effect of LO amplitude on the mixer performance is also examined. Figure - shows that the CG, NF, and IIP degrade noticeably when the LO amplitude is below 00 mv pp because of insufficient voltage swing to completely steer the LO current. 9

42 CG [db] NF [db] IIP [dbm] CG NF IIP Current Density [ua/um] Figure -. Effect of input stage current density on CG, NF, and IIP CG NF IIP CG [db] NF [db] IIP [dbm] Single-ended LO Amplitude [Vpp] Figure -. Effect of LO amplitude on CG, NF, and IIP. C. DC Offset To measure the mixer DC offset due to the different mechanisms including device mismatch, LO self-mixing, and second-order intermodulation product, the testing 0

43 procedure described in [4] is adopted. In the first measurement, the RF and LO inputs are supplied with DC bias only and are terminated with precision 50-Ω terminations. As a result, the measured DC offset is due to device mismatch only (V os, mismatch ). In the second measurement, the LO signal is applied whereas the RF input is still with DC bias only. In this case, the measured DC offset (V os, LO ) includes the effect of both device mismatch and LO self-mixing owing to LO-to-RF leakage. The DC offset due to LO self-mixing (V os, self-mixing ) can be determined by taking the difference between V os, LO and V os, mismatch from the first measurement: Vos, self mixing = Vos, LO V. (.0) os, mismatch In the third measurement, two-tone signals at GHz and GHz are applied to the RF input while the LO frequency is set to.990 GHz. The two-tone RF signal strength is set at 0 dbm to model low-power interferers. It should be pointed out that the RF frequencies are chosen to be about 0 MHz away from the LO frequency so as to separate the effects of LO self-mixing and second-order nonlinearity. With this setup, the total static DC offset (V os, total ) is measured, which includes the effect of device mismatch, LO self-mixing, and second-order nonlinearity. Consequently, the contribution of second-order nonlinearity (V os, IM ) to the total DC offset can be extracted using V os, LO from the second measurement as follows: V = V V. (.) os, IM os, total os, LO As an attempt to estimate the dynamic DC offset which can be caused by strong inband interferers, the fourth measurement is performed with the two-tone RF signals increased from 0 dbm to 0 dbm. The excess DC offset due to the high-power

44 interferers (V os, strong IM ) can then be determined from the measured DC offset (V os, system ) as V = V V V. (.) os, strongim os, system os, IM os, LO The breakdown of DC offsets due to the different sources is summarized in Figure -4 based on the measurement results from 0 different samples. The measured offset ranges from.4 to 4. mv when LO amplitude of 450 mvpp is applied. LO self-mixing is the main contributor at 5 %. Device mismatch is responsible for 7 % of the offset. Typically, device mismatch is the dominant cause for mixer DC offset. The superior performance obtained is due to the folded topology which allows the LO bias current to be set at near zero. Even when the strong RF interferers at 0 dbm are applied, the DC offset due to second-order intermodulation contributes only % to the total DC offset. However, further measurements reveal that when the LO amplitude is reduced to optimal level at about 00 mvpp, the DC offset reduces to between.7.6 mv. The device mismatch becomes the main contributor at about 45 % whereas the LO self-mixing and high-power intermodulation have almost the same contributions at 9 % and 6 %, respectively. It is observed that the offset due to high-power intermodulation is higher at the lower LO amplitude. This result confirms that excessive LO amplitudes should be avoided for the proposed folded mixer to minimize DC offset due to LO self-mixing. Furthermore, within the bandwidth limitation, the LO switching PMOS devices should be made as wide as possible to reduce both mismatch and the required LO amplitude.

45 DC Offset Voltage [mv] Device Mismatch Self-mixing Low-power Intermodulation High-power Intermodulation Number of Samples Figure -4. DC offsets due to different contributors in the mixer. D. Linearity Figure -5 shows an extrapolation plot of IIP and IIP based on a two-tone test with RF inputs at 5.0 GHz and GHz and the IF output spectrum centered at 0.5 MHz. Over the 7 GHz wideband, the mixer achieves an IIP of 7. to 4.4 dbm, and an IIP of. to 0. dbm. IF Output Power [dbm] IIP=-.0dBm RF Input Power [dbm] (a) IIP=8.6dBm

46 (b) Figure -5. (a) IIP and IIP extrapolation plot and (b) IF output spectrum..6 Simulated and Measured Results of the Wideband Receiver The wideband front-end receiver including the LNA, active balun, and folded mixer is designed in a 0.-μm CMOS process and fabricated as shown in Figure -6. The active area is 00x400 μm. For measurement, the RF front-end portion is diced and attached on the designed PCB board with bondwire connectivity for signal and power supply. To convert a differential mixer output signal into a single-ended signal, an external receiver [5] is used on the PCB board. 4

47 Figure -6. The chip micrograph of the receiver with wirebond and COB. A. Conversion Gain, NF, and Nonlinearity The simulated and measured S are compared in Figure -7. The measured S including bondwire and PCB parasitics is less than 0 db over GHz without external matching networks on the PCB board. The measured frequency responses of the CG, NF, and IIP under a.-v supply are shown in Figure -8 along with simulation results. The line with circles and the line with triangles represent the simulated and measured performance, respectively. 5

48 0-5 S Measured S Simulated S [db] Frequency [GHz] Figure -7. Comparison of simulated and measured S-parameter S CG CG [db], NF [db], IIP [dbm] NF IIP Frequency [GHz] Figure -8. Frequency responses of CG, NF, and IIP. All the measured results include parasitics from the COB and PCB without external input matching networks. Both CG and NF exhibit the best performance,. db and 5.5 db, respectively, near GHz where the S has deep notch and the output load impedance of the LNA has peak impedance since the active balun and mixer are designed to have 6

49 relatively flat gain characteristic by having opposite gain slope over the frequency range. The IIP is recorded between 8. to.7 dbm over 5 GHz frequency. The lower nonlinearity comes from the load resistance of 50 Ω in the active balun since it causes around 0. V voltage drop across the load resistors. If the load resistors are replaced by inductors, linearity will be improved. The CG and IIP are de-embedded to get performance of the receiver itself, but the NF includes noise contribution of the external receiver. B. DC Offset and Nonlinearity The DC offset is a critical parameter for direct conversion receivers since most of the gain occurs after the downconversion of the input signal and the receiver can be saturated if the offset is too large. Static DC offset is caused by device mismatch, LO self-mixing due to LO-to-RF leakage, and secondary nonlinearity. To measure the receiver DC offsets due to the different mechanisms including device mismatch, LO self-mixing, and second-order intermodulation product, the testing procedure described in [5] is adopted. The measured DC offsets due to the different mechanisms are isolated and plotted in Figure -9 over the frequency range. The main contributor of the DC offset in the receiver is the self-mixing due to LO feedback to the input of the LNA, active balun, and mixer. The big change in the plot compared to the previous DC offset plot of the mixer itself is the increment of the DC offset due to selfmixing. It was less than mv in the mixer, but it increases a few tens of mv to a few hundreds of mv amplitude. Since the LO amplitude coupled at the LNA and active balun input is amplified as much as the gain of each block or the cascaded blocks. For example, 7

50 if the cascade gain of the LNA and active balun is greater than 0 db, the DC offset due to the self-mixing will be amplified by the amount of the gain as well. Abrupt change in the DC offset due to self-mixing over the operating bandwidth comes from amplitude and phase imbalance of the external hybrid and cable assembly to make differential LO signals. The maximum imbalance of amplitude and phase are 0.5 db and 4, respectively. As shown in Figure -9, the main contributor to the DC offset is LO selfmixing. In order to understand the effects of LO amplitude on the DC offset due to the self-mixing, LO signal is swept and DC offset due to the self-mixing term is measured and shown in Figure -0. The LO amplitude should be minimized to reduce DC offset from the self-mixing as long as complete commutation is achieved in the LO switching stage of the mixer. DC Offset Voltage [mv] Device Mismatch Intermodulation Self-mixing Frequency [GHz] Figure -9. DC offsets due to different contributors in the receiver. 8

51 Vos,SM [mv] LO Power [dbm] Figure -0. DC offset voltage due to self-mixing with different LO amplitude. RF linearity measurement requires expensive test facilities such as network analyzer, spectrum analyzer, signal generator, and so on. For nonlinearity measurement of IIP and IIP, two signal generators and one spectrum analyzer are mandatory equipments. Furthermore, it takes time since input signal amplitude needs to be swept by db step to pick appropriate extrapolation point up for accurate measurement. As an alternative way, DC offset can be utilized to get relatively accurate IIP and IIP as described below. Suppose that there is a static offset voltage in differential circuit arising from device mismatch or bias asymmetry, the offset voltage can be referred to the input of the differential circuit to model all internal offsets as shown in Figure - [6]. Vos,in Vin Differential Circuit (Av,diff or Gdiff) Vout Zeq Vos,IM Oscilloscope or Multimeter Figure -. Differential circuit with input-referred offset voltage for relationship between DC offset and nonlinearity. 9

52 The DC offset due to the second-order intermodulation (V os,im ) can be employed to evaluate the IIP. Because V os,im represents the amplitude of the second-order intermodulation product, IIP can be calculated as in Eq.(.) in, os IIP = P P + CG (.) where P in is the input power and P,os is the amplitude of the second-order intermodulation product (V os, IM ) in dbm, and CG is the conversion gain of the receiver in db. When P,os is calculated, the input impedance (Z eq ) of the multimeter or oscilloscope which measures the DC offset voltage as shown in Figure - should be taken into account. In this measurement, LeCroy 954L oscilloscope is used along with AP00 probe having -MΩ input impedance. If the input-referred offset voltage (V os,,in ) of the differential circuit and the calculated IIP from the output DC offset voltage are known, IIP can be calculated based on the following equation which is derived using power series V = a V + a V + a V + L as shown in [7] with two input tones including out in in the input-referred offset voltage, V + Acos( ω t ) + Acos( ω t ) ( os, in ( IIP os, in ) ) in Vin os,in =. IIP= 0log V V V / (.4) where VIIP is the input-referred second-order intercept voltage, VIIP the input-referred third-order intercept voltage. To calculate IIP based on the measured DC offset and calculated IIP, the measured output DC offset voltage should be referred to the input using the following equation V V os, IM os, in = (.5) Avdiff, 40

53 where A v,diff is the gain of the differential circuit as shown Figure -. The IIP and IIP are calculated with Eq. (.4) and Eq.(.5), respectively and compared to the simulated and measured results in Figure -. The line with circles represents the simulated results, the line with squares the calculated ones, and the line with triangles the measured ones. The measured results show relatively better matching with the calculated results from the measured DC offset voltage rather than the simulated results. This comparison proves promising usefulness of the DC offset in differential circuits to estimate nonlinearity by simply measuring DC offsets since the calculated IIP is placed in between the simulated and measured results. IIP & IIP [dbm] 0 5 IIP IIP Frequency [GHz] Figure -. Nonlinearity of simulated, measured, and calculated results..7 Summary The low-power wideband receiver with active balun is realized using 0.-μm CMOS technology. The compact LNA with transformer-based input matching is realized, followed by the active balun to provide fully differential circuit for the folded mixer. The 4

54 folded mixer topology utilizing PMOS devices in the switching stage and broadband RF chokes for biasing is shown to be an effective technique for both low-voltage and wideband operation. The key sources to the receiver DC offset are measured systematically using a multi-step procedure under different excitations. The usefulness of DC offset in the receiver is proven to estimate nonlinearity without measuring IIP and IIP which requires expensive RF equipments. The low-power, high-performance wideband down-conversion mixer is realized to suppress the impact of device mismatch on DC offset. The key sources to the mixer DC offset are measured systematically using a multi-step procedure under different excitations. 4

55 Chapter Equation Chapter (Next) Section Wideband Linearity Enhancement Techniques for LNAs. Introduction The linearity of an LNA using a Si bipolar junction transistor [7] was improved by low-frequency low-impedance base termination without degrading gain or noise figure (NF). This technique is not effective for FET amplifiers if a complementary metal oxide semiconductor (CMOS) is biased in a strong inversion region. The feed-forward linearization technique [8] was used to achieve very high linearity in a CMOS LNA. However, this technique is sensitive to device mismatch between the main and auxiliary devices as well as error in the signal scaling. Inherently an FET has a high IIP peak called a sweet spot in a moderate inversion region [9], [0]. This sweet spot can be reached by biasing the transistor gate such that the third-order derivative of its DC transfer characteristic crosses zero. The sweet-spot is utilized only for low-power mobile devices of short-range, less-sensitivity standards such as cordless phones and Bluetooth due to a low unity-gain frequency. The IIP peak is very sensitive to a gate bias voltage, making it difficult to bias accurately to achieve a high IIP due to bias variations. The linearity enhancement technique called a derivative superposition (DS) [] was proposed to reduce the IIP sensitivity to the gate bias voltage by extending zero crossing 4

56 points. This DS method was applied for an FET amplifier superposing two transistors in parallel, resulting in 0dB improvement of the IIP in []. This linearity improvement was limited by the IMD products and their feedbacks to the input, which were decreased substantially by reducing the source-degeneration inductance as well as cascoding the output of the linearizing amplifiers. The small degeneration inductance hinders a simultaneous power-noise input match resulting in a higher NF. To achieve a high linearity without degrading NF, two modified derivative superposition techniques [], [4] are proposed such that the composite vector sum of the IMD and IMD is cancelled out each other. However, all the linearity enhancement techniques addressed before are proposed for narrow-band amplifiers. Highly linear broadband LNA employing noise and distortion cancellation techniques [] is recently reported with an inductorless topology. It shows high linearity in both the 900 MHz and GHz bands but low gain even with two cascade stages while consuming 7.4 mw. There are several techniques to implement a wideband LNA by employing silicon transistors, in particular, in CMOS technology. At the expense of high power consumption and large area, distributed amplifiers [5], [6], [7], [8] achieve very wideband performance by absorbing circuit parasitics and these are suboptimal for mobile applications. Wideband inductor-less LNAs are proposed in [9], [8], based on resistive feedback. These LNAs achieve NF less than db and other performance comparable to their narrowband counterparts by utilizing deeply-scaled nanoscale CMOS transistors. Thus they have extremely small die area but consume a large amount of power. As an alternative wideband topology, the common-gate amplifier was employed and low NF was achieved with noise cancellation scheme in [9], [40]. For moderate die 44

57 area and power consumption, two wideband LNAs with a source-degeneration inductor [0], [0] are presented based on Chebyshev BPF input matching and ladder input matching networks, respectively. Both of topologies use a shunt-peaking technique [4] for a wideband output load network and show low linearity performance since the large peaking resistor reduces voltage headroom. In addition, a wideband LNA with a transformer-based input matching network [] is proposed as an alternative solution to implement the input matching network of compact size but still suffers from low linearity due to low voltage headroom caused by a large peaking resistor. While numerous techniques have been proposed for increasing LNA bandwidth (e.g., [0], []), there have been relatively few studies of linearity enhancement in wideband LNAs. For example, [] and [4] employ noise and distortion cancellation techniques to achieve an IIP of about 0 dbm for small frequency spacing at 0.8. GHz and GHz while consuming 7.4 mw and mw, respectively. For highly-linear wideband LNAs, linearity enhancement and wideband circuit techniques must be used simultaneously. In Section., nonlinearity analysis methods are introduced in order to provide some intuitive tools through the extracted and derived nonlinearity coefficients described later. In Section., the precedent linearity enhancement techniques are addressed in order to make the most of them for wideband linearity enhancement techniques described in Chapter 4.. Theory for Nonlinearity Analysis Several linearity enhancement techniques have been introduced in recent years: derivative superposition (DS) [], [4], modified derivative superposition (MDS) [], 45

58 and alternative derivative superposition [4]. The details of linearity enhancement techniques including the inherent IIP peak of a CMOS transistor are addressed below with conceptual diagrams and simulated results after defining several terminologies and expressions... DC Theory for Nonlinearity Analysis For RF applications, a MOSFET transistor in Figure - (a) is usually biased in saturation region and its small-signal equivalent circuit can be represented as shown in Figure - (b). (a) (b) (c) Figure -. (a) A MOSFET transistor, (b) its incremental model including back-gate effect, and (c) simplified equivalent circuit with the assumption that the nonlinearity is weak and memoryless. 46

59 One contributor to the distortion of the transistor arises from the nonlinearity of its transconductance in saturation. When the nonlinearity of the transistor is assumed to be weak and memoryless, its small-signal equivalent circuit gets simplified as shown in Figure - (c) by neglecting the other MOSFET model parameters such C gd, g mb, and so on. The nonlinearity of the transconductance is segmented into three nonlinear DC transfer functions, with the assumption that the three nonlinearity terms are sufficient. The drain current can be expressed in terms of its small-signal gate-source bias voltage vgs by a power series around the DC operating point gs gs i (v ) = g v + g v + g v +L (.) d gs gs where g is the small-signal transconductance, and g and g the higher order nonlinearities as defined in Eq. (.). I I I g g g D D D = = = VGS VGS 6 VGS (.) In particular, g should be carefully considered since it represents the IMD and thus determines the IIP. The g depending on a gate-source voltage V GS changes polarity from positive to negative when a device transitions from the weak and moderate inversion regions to the strong inversion region. The input amplitude at the IIP point is given by the following equation [4]. 4 g A IIP = (.) g If the circuit under consideration contains no capacitors or inductors or the frequencies of interest are so low that capacitors and inductors do not play a role yet, it is referred to as a memoryless circuit. 47

60 As we can see in Eq. (.), the A IIP depends on only the DC transfer characteristic of the transistor itself without including its own circuit parasitics and external circuit components such as source-degeneration inductance. It implies that the nonlinearity expression based on the DC transfer characteristic cannot provide a good IIP estimation since it does not account for the high frequency effects such as feedback and coupling. Therefore, a new approach that includes the effects of frequency and memory is inevitable to be introduced for RF applications... Frequency-Domain Theory for Nonlinearity Analysis The DC theory for the nonlinear analysis cannot capture memory effects in the frequency domain. As an alternative, the Volterra series [44] is introduced with the harmonic input method [45] not only to capture the memory effect of devices such as capacitors and inductors, but also to provide insight in a circuit design by derived analytical expressions before a numerical iteration in simulation is performed. The details of the Volterra series and harmonic input method are introduced in Appendix A, in addition to the convolution and Taylor series. Some details of the Volterra series will be revisited below both to provide fundamental understandings of the Volterra series briefly and to define a new Volterra coefficient as a consolidated parameter in the frequency domain. If a nonlinear device is in weakly nonlinear region, the Volterra series can be used to evaluate its nonlinearity. First of all, as used in the DC theoretical analysis, the power series in Eq. (.) for the output current holds. On the other hand, the gate-source voltage The Volterra series and Volterra theorem were developed in 887 by Vito Volterra, an Italian mathematician and physicist. 48

61 of each nonlinear device is modeled by truncated Volterra series in terms of an excitation voltage v s v = A() s ov + A ( s, s ) ov + A ( s, s, s ) o v (.4) gs s s s where A, A, A are the first-, second-, and third-order Volterra kernels in the frequency domain and is a Volterra operator. Thus the output current of a FET amplifier can be represented by the Volterra series in terms of excitation v s in the time domain: s s s i( v ) = C ( s ) o v + C ( s,s ) o v + C ( s,s,s ) o v (.5) where Cn( s,s, K,sn ) represents the frequency domain form of the nth-order Volterra kernel, s is the Laplace variable, and the operator represents the magnitude and phase change of the input spectral components of v s by the nth-order Volterra kernel, Cn( s,s, K,sn ), when multi-tone sinusoidal signals are excited as an input signal. With two-tone excitation, s v s [ ω t ) + cos( ω t )] = A cos(, (.6) a b the input amplitude A IIP at the IIP point is given by the following form in the frequency domain: A IIP = 4 C( sa ) C ( s, s, s ) b b a (.7) where C ( sa ) represents the Volterra kernel of the g at the frequency of ωa when only a single tone of the frequency ω a is excited and C (,, ) s s s does the Volterra kernel of b b a the g at the frequency of ω b ω a when three tones of the frequencies ωa, ω b, and ωb are excited theoretically. In practical simulation or measurement, only two-tone 49

62 sinusoidal signals, ω a and ω b, need to be excited to create the second-order IMD product. The IIP expression in Eq. (.8) represents the available power of the signal generator at the third-order intercept point with reasonable input impedance match. AIIP C( sa ) IIP = = 8Re Z ( s ) 6Re Z ( s ) C ( s, s, s ) [ ] [ ] a a b b a (.8) To extract the Volterra kernels C and C for the IIP calculation in the analytical expression of Eq. (.8), we need not only to model nonlinearities associated with the drain current of the FET amplifier by its gate-source voltage as written in Eq. (.), but also to capture the effects of memory and frequency given by the expression of Eq. (.4) through the input matching network. Then using the harmonic input method, the wanted Volterra kernels can be derived with the equivalent circuit of the FET amplifier. The whole IIP derivation procedure is summarized in the flow chart of Figure -. The expressions of the current and voltage in the chart refer specifically to the derivative superposition topology. However, the general procedure can be applied to any other topologies. Even though the IIP expression can take into account the memory and frequency effects of a capacitor and inductor in the circuit, it cannot capture those effects of a transistor itself since the transistor is modeled with only the gate-source capacitance and dependent drain current source. It means that when Eq. (.) is introduced for the IIP expression we have the following assumptions: ) The body effect is negligible, g mb 0. ) Except the gate-source capacitance C gs, all parasitic capacitances are zero. 50

63 ) The C gs is bias-independent. 4) The gate and source resistance of a transistor are ignored. 5) No channel length modulation, i.e., g. o Figure -. Flow chart for the derivation of an IIP derivation. 5

64 ω ω 0.. Frequency-Dependent Nonlinearity Coefficients To capture those effects excluded in the previous IIP derivation, a frequencydependent nonlinearity coefficient is newly introduced and defined. Before the frequency-dependent nonlinearity coefficient is defined in the frequency domain, the line spectrum due to the harmonic and intermodulation distortion is shown in Figure - when two sinusoidal signals are excited. When two sinusoidal signals are applied at the input of a nonlinear circuit, there are two, six, and ten different mixes, respectively, contained in the first-order, second-order, and third-order outputs [0]. The corresponding positive output spectrum is shown in Figure - with the order number. () () () () () () () () () () () () () () () ω ω ω ω ω ω ω ω +ω ω ω ω +ω ω + ω ω Frequency Figure -. Line spectrum of the positive frequency terms with two-tone input signals. Even though the Volterra kernels can capture the memory effects of external components such as a capacitor and inductor, they basically depend on the DC transfer characteristics of the nonlinear device, g, g, and g defined in Eq. (.). The frequency dependence of the device nonlinearity itself is not taken into account for the IIP calculation, resulting from neglecting the other device parasitic shown in Figure - The notation and relationship between the Volterra kernel and frequency-dependent nonlinearity coefficient are summarized in the Appendix D. 5

65 (b) except C gs and g m v gs. To include the frequency and memory effects on the IIP, a new RF transfer function called the frequency-dependent nonlinearity coefficients of a nonlinear device itself is introduced below in conjunction with a Harmonic Balance (HB) analysis. Based on the given spectrum components in Figure -, we obtain the phasor forms of the drain current and gate-source voltage in each spectrum of the nonlinear device. As an example, the frequency-dependent nonlinearity coefficients of the FET transistor M B in Figure - (a) will be first derived below with ac voltages and currents in the frequency domain. The ac gate-source voltage of the M B is defined in Eq. (.9) v = v v (.9) gsb, HB, f gb, HB, f sb, HB, f where the subscripts represent the node (g:gate, s:source) and device name (B:M B ), the order number of the HB ( HB : st order), and the chosen frequency. Likewise, the firstorder, second-order, and third-order frequency-dependent nonlinearity coefficients 4 are defined in a ratio of the ac drain current to the ac gate-source voltage at each output frequency drawn in with the assumption that f and f are very closely located. g g g i i =, g = db, HB, f db, HB, f BHB,, f BHB,, f vgsb, HB, f vgsb, HB, f i i =, g = db, HB, f f db, HB, f BHB,, f f BHB,, f vgsb, HB, f vgsb, HB, f i i + =, g = db, HB, f + f db, HB, f BHB,, f f BHB,, f vgsb, HB, f vgsb, HB, f (.0) (.) (.) 4 Frequency-dependent nonlinearity coefficient and Volterra kernel are used differently here to make difference between kernels for a device itself and for a circuit, respectively. The frequency-dependent nonlinearity coefficient is written in the form of g, g, and g with some added subscripts. The Volterra kernel is written in the form of A, B, C, and so on with some added subscripts as shown in Appendix B, C, and D. 5

66 i i i g =, g =, g = db, HB, f f db, HB, f f db, HB,f BHB,, f f BHB,, f f BHB,,f vgsb, HB, f vgsb, HB, f vgsb, HB, f i i i g =, g =, g = db, HB, f + f db, HB, f + f db, HB, f BHB,, f+ f BHB,, f+ f BHB,,f vgsb, HB, f vgsb, HB, f vgsb, HB, f (.) (.4) Using all the extracted frequency-dependent nonlinearity coefficients, the first-, second-, and third-order composite frequency-dependent nonlinearity coefficients are calculated by summing all the same order coefficients and dividing by the number of the coefficients as in Eq. (.5)-(.7). ( ) g g g B, HB = B, HB, f + B, HB, f / g = g + g + g + g 4 ( + ), BHB B, HB, f f B, HB, f B, HB, f f B, HB, f ( ) g g g /, HB =, HB, f f +, HB, f f (.5) (.6) (.7) With the newly defined frequency-dependent nonlinearity coefficients, the Eq. (.) is re-defined for the frequency-domain theory. i ( v ) = g ( s) ov + g ( s, s ) ov + g ( s, s, s ) o v (.8) dhb, gs, HB gs, HB gs, HB gs The frequency-dependent nonlinearity coefficients are used in the following section to show the frequency and memory effects on the IIP in dbv, in comparison with the IIP in dbv from the DC transfer characteristics. Let s look at linearity enhancement techniques and evaluate them based on the introduced frequency-dependent nonlinearity coefficients.. Linearity Enhancement Techniques 54

67 To implement a linearity-enhanced wideband LNA, both linearity enhancement techniques and wideband circuit design techniques need to be incorporated relevantly at the same time. Since the precedent linearity enhancement techniques are intended for a narrow-band LNA, two different approaches are developed in this proposal to achieve high linearity over a wide frequency range. In the first technique, a self-biasing currentreuse technique is proposed to overcome the limitation due to the peaking resistor in shunt-peaking techniques [0], [] which are generally utilized in a wideband output load network with relatively large resistance. The large resistor limits the voltage headroom in the main and cascode transistors. Thus the small voltage headroom does not only prevent achieving an IIP peak point, but also making the IIP very sensitive to process variation as well as bias variation. Using the proposed current reuse technique, a PMOS in conjunction with a RF choke inductor broadens the operating gate bias range which guarantees high linearity without impacting the voltage headroom. In the second technique, two IIP peaks can be realized by merging and modifying two different linearity enhancement techniques [], [4]. Each topology is optimized at the lower and upper frequency boundaries to get relatively flat linearity response over the designed frequency range. The proposed linearity enhancement technique is analyzed by using a Volterra series and verified by simulated results. To achieve a wide bandwidth in conjunction with enhanced linearity, a commonsource LNA topology with a source-degeneration inductor is preferred with proper input and output matching networks as the source-degeneration inductor should be used to cancel out the second- and third-order intermodulation distortion products with the 55

68 derivative superposition technique while providing the required real part of the input impedance at around 50 Ω... Sweet Spot A MOSFET has a sweet-spot of the IIP when it is in a transition condition from a weak and moderate inversion region to a strong inversion region. Since the drain current of a MOSFET depends exponentially on the gate and drain voltage in the weak and moderate inversion regions, these regions are not preferred for highly-linear circuits [46]. Furthermore, the cut-off frequency f T in the moderate inversion region is often too low to achieve high frequency operation. Interestingly, the third-order intercept point IIP of the drain current shows a significant peaking or sweet-spot in the moderate inversion region of a MOSFET amplifier where the third-order derivative term denoted as g in Eq. (.) crosses zero. This peaking occurs as the dominant mechanism of the drain current changes from diffusion, a largely exponential behavior, to drift, a slightly less than square-law behavior [47]. The simplified schematic of a common-source (CS) amplifier with a sourcedegeneration inductor is shown in Figure -4 (a) and the first-, second-, and third-order DC transfer characteristics are shown in Figure -4 (b). 56

69 IIP [dbm or dbv] (a) g m, g m, g m Simulated IIP HB w/ Cgd Calculated IIP DC w/ Cgd Calculated IIP HB w/ Cgd Calculated IIP HB w/o Cgd 0.8 g m 0.6 g m 0.4 g m Gate Bias Voltage [V] (b) Gate Bias Voltage [V] (c) Figure -4. (a) Simplified schematic of a CS amplifier, (b) its DC transfer characteristics, and (c) IIP plots. The calculated IIP in dbv shows the peaking at the zero-crossing point of the thirdorder DC transfer characteristic, g m. The simulated IIP peak at GHz is reduced and shifted due to the memory effects caused by the device parasitic and degeneration inductance. Using the DC transfer characteristics has difficulty in determining the transistor size and estimating the IIP since the simulated IIP in the circuit is deviated from the IIP calculated by the DC parameters. 57

70 To show the memory effect of the gate-drain capacitance C gd, the model files are modified, in other words, the C gd card is intentionally turned off. As we can see in Figure -4 (c), the simulated IIP curve with C gd matches well the calculated IIP from frequency-dependent nonlinearity coefficients extracted by using HB simulation. However, the calculated IIP curve without C gd doesn t match the simulated IIP curve, implying that the C gd affects the nonlinearity performance of the transistor itself, with respect to the gate bias voltage. However, the IIP peak without the C gd doesn t deviate that much from the IIP peak with the C gd. To see the effect of the source degeneration inductance on the IIP, the inductance is changed and the IIP values are calculated with the DC and frequency-domain transfer characteristics as shown in Figure -5. The black line represents the IIP calculated using the DC transfer characteristic and the blue and red lines do the IIP calculated using the frequency-dependent nonlinearity coefficients defined in Eq. (.9)-(.7) at 0. GHz and GHz, respectively. The IIP degradation is becoming critical due to larger feedback of intermodulation products as both inductance and frequency increase, resulting in no IIP peak at GHz with nh inductance as shown in the right-bottom graph of Figure -5. On the other hand, the IIP peak value in this moderate inversion region is very sensitive to bias variations and furthermore the IIP peaking can be achieved over a very narrow bias range, while limiting an operating frequency due to the low unity-gain frequency in the moderate inversion region. 58

71 IIP [dbv] IIPHB of CS Amplifier w/o Ls Gate Bias Voltage VgMT [V] IIP [dbv] IIPHB of CS Amplifier w/ Ls=0.nH 5 0 DC 5 0.GHz 0 GHz Gate Bias Voltage VgMT [V] IIP [dbv] IIPHB of CS Amplifier w/ Ls=0.5nH Gate Bias Voltage VgMT [V] Figure -5. IIP plots with different source degeneration inductances at 0. and GHz. IIP [dbv] IIPHB of CS Amplifier w/ Ls=nH Gate Bias Voltage VgMT [V].. Derivative Superposition To reduce the IIP sensitivity to bias variations as well as obtain the high unity-gain frequency f T of the FET amplifier, the derivative superposition method was proposed in [] as shown in Figure -6 (a). The DS topology utilizes the fact that the polarity of the third-order derivative term g changes from positive to negative when the gate bias voltage V GS changes from the weak and moderate inversion regions to the strong inversion region. If two common-source FETs are configured in parallel such that with proper offset voltage the positive and negative polarity regions are aligned to cancel out each other at a certain gate bias range, the corresponding g will be driven to zero. In other words, the third-order nonlinearity term becomes zero and the IIP does infinite. 59

72 IN OUT M A M B L B V gst V gmt (a) (b) V s Z (s) G V g i(v s )=i T D + V ga + i B (V gb ) C A C B V gb g B V gb i A (V ga ) g A V ga V Z in (s) L B (c) Figure -6. (a) Schematic of the derivative superposition method, (b) conceptual diagram of DS and (c) small-signal equivalent circuit. 60

73 At the IIP peak, the FET M A is in the weak inversion region with the positive g A and the FET M B is in the strong inversion region with the negative g B such that the composite g should be near zero as shown in Figure -7 (b). The improvement of IIP due to expanded zero-crossing range of the composite g can be obtained as shown in Figure -7 (d). Practically this IIP peak happens only at low frequencies where the parasitic doesn t contribute to nonlinearity significantly. At high frequencies, the source degeneration inductance provides a feedback path for the total drain current i T to the input gate-source voltage, resulting in additional high-order intermodulation products. Figure -7. Derivative superposition method. (a) st -, nd -, and rd -order power series coefficients of the auxiliary transistor, (b) st -, nd -, and rd -order power series coefficients of the main transistor, (c) rd -order power series coefficients and superposition, (d) Calculated IIP dbv. 6

74 To illustrate imperfect cancellation of the composite third-order intermodulation products, the conceptual diagram is drawn in Figure -6 (b). There is still the IMD component which contributes to the IMD through feedback to the input even though the IMD components cancel out each other perfectly. The analytical explanation for an imperfect cancellation is given in the Appendix B using Volterra series analysis and the derived IIP expressions are presented in Eq. (.9). In the derived IIP expression, the IIP represents the available power of the signal generator at the third-order intercept point with reasonable input impedance matching condition * Z ( ) ( ) s = Z s in AIIP C( sa ) IIP = = 8Re Z ( s ) 6Re Z ( s ) C ( s, s, s ) [ ] [ ] a a b b a (.9) where Z s sl B B in() = B + + sc ( A + CB) CA + CB g L. (.0) The IIP of the LNA in Figure -6 (a), obtained from the Volterra analysis of the equivalent circuit of Figure -6 (c), is given by IIP ( + ) 4ω gb LB CA CB = (.) ε where g ε = g + g g + g + jω g L B gb A B A B CA + CB g g ( ) ( ) B B + + j ω CA + CB + Z j ω jωlb LB B B. (.) As shown in Eq. (.) and (.), the IIP doesn t become infinite due to the contribution of the second-order IMD products in Eq. (.) even though the composite 6

75 third-order term g = g A + g B of the transconductance becomes zero. Using the DS linearity enhancement technique, the IIP is not able to be zero due to both the amplitude contribution of the second-order term and the phase change of the source degeneration inductor shown in the third-term of Eq. (.). The higher frequency ω and the larger inductance L B, the smaller IIP, as the IIP is inversely proportional to both of the parameters. As shown in Figure -8, the DS method does not provide IIP peaking at higher frequencies which the effect of the circuit reactance is not negligible as frequency increases. IIP [dbv] DC 0.GHz GHz GHz 4GHz 7GHz IIPHB of DS Amplifier w/ Ls=0.nH Gate Bias Voltage VgMT [V] Figure -8. IIP plots in different frequencies with 0. nh source inductance. The calculated IIP curve using the DC transfer characteristic doesn t capture any memory effect on the IIP. On the other hand, the calculated IIP curves using the frequency-dependent nonlinearity coefficients extracted from the HB analysis show the IIP degradation in the same circuit as the frequencies increase. As a result, the DS 6

76 method doesn t achieve a high IIP value at the high frequencies. Therefore, another linearity enhancement technique is inevitable... Modified Derivative Superposition [] The source degeneration inductance in a common-source amplifier provides a feedback path for the drain current to the gate-source voltage. The feedback becomes stronger with increasing frequency. The second-order harmonics are fed back to the input and mix with the fundamental input signal. Eventually the feedback of the second-order harmonics generates additional third-order intermodulation products. From Eq. (.), it is evident that Z ( ω ) should be increased to reduce the secondorder contribution to IMD. In order to enhance the IIP at higher frequencies, the second-order contribution to IMD can be utilized so that it makes the same amplitude and opposite phase with the third-order IMD contribution. To accommodate this concept, the modified derivative superposition (MDS) method was proposed as shown in Figure -9 (a) []. The sources in two parallel FETs are connected to different nodes of the source inductors to adjust the magnitude and phase of the composite third-order contributors including the second-order contributor. The source of the FET M A are connected to the common node of the two inductors L A and L B to adjust the magnitude and phase of its third-order term g A contribution to the IMD with respect to the g B and g B contributions of the FET M B. Graphically, the conceptual vector diagram is plotted in Figure -9 (b) to show how the composite third-order IMD terms cancel out each other. 64

77 IN OUT M A M B L B L A V gst V gmt (a) Composite rd -order contribution Im g B V gb g B V gb g A V ga θ=tan - (ωl B g B ) Re (b) Figure -9. (a) Schematic of the modified DS method and (b) conceptual vector diagram. As we can see in the first term of Eq. (.4), the g A magnitude and phase are mainly tuned by L B and g B. The second-order contribution is adjusted by L A, L B, and g B as shown in the denominator of the third term in Eq. (.4) IIP 4 g Bω [ L A ( C A + C B ) + L B C B ] (.) ε 65

78 ε = g A LBCB [ B B ] + L ( C + C ) ( + jωl g ) + ( ωl g ) B B A A B + L B C B + g B g g B B + jω ( LA + LB ) gb (.4) where the input impedance has the following expression while assuming a conjugate impedance matching, ( ) + sgb LA+ LB + s CBLB Zin() s = sla + sc C sg CL sccl ( A+ B + B A B + A B B). (.5) The modified superposition method basically intends to be used for a narrow-band LNA. In order to evaluate this technique for a wideband low-noise amplifier, the wideband LNA is designed and the IIP is simulated over the frequency range. It shows higher IIP values at the specific frequency but poor IIP values at other frequencies. Furthermore, the MDS shows that the IIP is very sensitive to the gate-source bias voltage as well as the power supply voltage since the big resistance in shunt-peaking technique limits voltage headroom...4 Alternative Derivative Superposition [4] The two main drawbacks of the MDS method are pointed out in [4]. The most important drawback is that the additional weak inversion transistor added in parallel to achieve linearity degrades NF due to its high gate induced current noise which is added to the input []. The other one is that the auxiliary NMOS adds more input parasitic capacitance and as a result reduces the operating frequency range. Furthermore, it changes the input matching. 66

79 As an alternative to minimize the side effects of the auxiliary NMOS, the sourcetapped auxiliary transistor is added to adjust the composite IMD term equal in magnitude and opposite in phase as shown in Figure -0 (a). (a) I D Ld V in G V out V s D β(i D +IM) L S f(v s )= IM (b) Figure -0. (a) Schematic of the alternative DS method and (b) conceptual diagram. The second-order nonlinearity coefficient g B appears in Eq. (.7) due to the feedback effect. The effect of g B on IIP has become independent of any circuit parameters, thus resulting in a constant value. The third-order derivative of the DC 67

80 transfer characteristic of the auxiliary transistor M A is adjusted to achieve higher IIP by choosing appropriate inductance values of L A and L B. B IIP = (.6) 6 Re( Z ( s )) A ( s ) ε s g g B + s L AC A ε = g B + g A n( s ) n( s ) (.7) g B ( + s L AC A ) n( s ) A ( sl B ( g B + sc B ) = (.8) + sc ( sl + sl ) s ) A A B + s C A ( L A + L B ) = (.9) s L B C B ( + s L C ) A A This linearity enhancement technique requires very large source inductance values to obtain higher IIP value to provide the same magnitude and opposite phase with the composite IMD products. The inductances of 5 nh and.05 nh are utilized for this topology at the 950 MHz operating frequency. These kinds of linearity enhancement techniques addressed in the section of. work only for a narrow band amplifier as the same amplitude and opposite phase can be achieved at a certain frequency. For highly linear wideband amplifiers, multiple IIP peaks over a wideband frequency range are inevitable for multi-standards communications due to different linearity requirements..4 Summary In the modified DS technique of [], an IIP peak occurs only at the operating frequency because the nd -order Volterra kernel of a main transistor has the same amplitude and opposite phase with respect to the composite rd -order Volterra kernel of 68

81 the main and auxiliary transistors at that frequency. The linearity enhancement technique of [4] taps an input signal of an auxiliary transistor from the source of the main transistor not only to achieve high linearity, but also to reduce NF degradation due to a gate induced current noise. These two linearity enhancement techniques [], [4] are proposed for the narrow band LNAs. Highly linear broadband LNA employing noise and distortion cancellation techniques [4], [] achieve an IIP of about 0 dbm for small frequency spacing at 0.8. GHz and GHz while consuming a large amount of power of 7.4 mw and mw, respectively. In the next chapter, low-power wideband linearity enhancement techniques are proposed with nonlinearity analysis by the Volterra series and newly introduced frequency-dependent nonlinearity coefficients. 69

82 Chapter 4 Equation Chapter (Next) Section Proposed Highly-Linear Wideband LNA To achieve a wide bandwidth in conjunction with high linearity, a common-source LNA topology with a source-degeneration inductor is chosen with proper input and output matching networks since the source-degeneration inductor should be used to cancel out the IMD and IMD products with the DS technique. To implement a linearityenhanced wideband LNA, both linearity enhancement techniques and wideband circuit design techniques need to be incorporated relevantly at the same time. Since the precedent linearity enhancement techniques are intended for a narrow-band LNA, two approaches (WBDS and SBCR) are proposed to achieve high linearity over a wide frequency range. First of all, two IIP peaks can be realized by merging and modifying two linearity enhancement techniques [], [4]. Linearity of each topology is optimized at the lower and upper frequency boundaries to get relatively flat linearity response over the designed frequency range, respectively. Second, the SBCR technique is proposed to overcome the limitation due to the peaking resistor in shunt-peaking techniques [4] which are generally utilized in a wideband output load network with relatively large 70

83 resistance. The large resistor limits the voltage headroom in the main and cascode transistors. The proposed linearity-enhanced wideband LNA topology is analyzed by the Volterra series with the newly introduced frequency-dependent nonlinearity coefficients. Two LNAs using the proposed topology are designed in a 0. um CMOS process and demonstrated with simulated and measured results to confirm the effectiveness of the proposed topology. 4. Introduction As a benchmark to implement a linearity-enhanced wideband amplifier, both wideband design techniques and linearity enhancement techniques are addressed in detail in the preceding chapter. Based on the limitations of the precedent designs, two different techniques are proposed and analyzed to achieve the linearity-enhanced wideband LNA in this chapter. For highly-linear wideband LNAs, linearity enhancement and wideband circuit techniques must be used simultaneously. This chapter starts with a source-degenerated topology with input and output matching networks. Two techniques, namely the WBDS and SBCR techniques are proposed to achieve high linearity over a wide frequency range. In the WBDS, two IIP peaks are realized by merging and modifying two linearity enhancement techniques [], [4]. Then linearity of each is optimized at the bandwidth boundaries to obtain a flat linearity response over the designed frequency range. The SBCR is then used to increase the headroom in a shunt-peaking load. The proposed linearity-enhanced wideband LNA topology is analyzed using a Volterra series and its distortion cancellation is visualized by frequency-dependent nonlinearity 7

84 coefficients, leading to a 6 GHz design in 0.μm CMOS. Measurement results show linearity is enhanced. 4. Self-biasing Current Reuse (SBCR) Technique For a linearity-enhanced topology, the cascode LNA with a source-degeneration inductor is preferred as the second- and third-order nonlinear terms cancel out each other through the degeneration inductors as shown in Figure -9 and Figure -0. In the LNA topologies with wideband input matching networks, a shunt-peaking load network is preferred in many cases [0], [0] to provide a wideband output matching. Due to the large shunt-peaking resistance, there is no enough voltage headroom to guarantee high linearity as supply voltage scales down. In these two cases mentioned above, around mv across the peaking resistors is necessary to provide moderate RF performance such as gain and IIP, regardless of the supply voltages. In a.-v power supply, only V voltages can be used to bias the main transistor and cascode transistor and thus they are not high enough to keep two stacked transistors in a highly linear region when a gate bias voltage is swept to control linearity depending on required IIP specifications in a certain operating condition. 7

85 I OUT V IN C V gs =0.47V M W=9um L=0nm Figure 4-. (a) Simplified common-source amplifier and (b) IIP vs. V ds. To verify the effect of limited voltage headroom itself on the linearity, a commonsource amplifier in Figure 4- (a) is designed and simulated without a sourcedegeneration inductor. The blue line with circle marks in Figure 4- (b) represents the calculated IIP in dbv at 0. GHz and the red line with triangle marks do the IIP in dbv at GHz. As the drain-source voltage increases, the IIP is improved continuously and then starts saturated beyond around 0.65 V due to velocity saturation and hot carrier effect even though more current is burning. Furthermore, in order to verify the effects of the limited voltage headroom in a practical circuit, the common-source amplifier with the linearity-enhanced topology shown in Figure -9 (a) is designed as shown in Figure 4- (a) and simulated. The effect of the drain-source voltage on the IIP in dbm is shown in Figure 4- (b). The current consumption is plotted with the straight red line. As we can see, approximately a 0.6-V drain-source voltage is necessary to obtain the IIP peaking. Therefore the techniques which can alleviate the supply requirement need to be implemented for a linearity-enhanced LNA. 7

86 (a) (b) Figure 4-. The effects of voltage headroom on IIP: (a) simplified schematic and (a) IIP vs. Vds plot. A current-reuse technique [48] is used for a mixer to enable a low-voltage operation and obtain better performance in comparison with a conventional Gilbert cell mixer [49]. In the current-reuse technique, some portion of the driver-stage bias current is bled through an additional PFET transistor to reduce the voltage drop across the load resistor, while keeping or increasing the bias current to get better performance under the same supply voltage as the IIP and conversion gain of the mixer are proportional to the square root of the bias current [50]. For a wideband LNA design, the current-reuse technique shown in the red-color portion of Figure 4- is employed to provide large enough voltage headroom without limiting the choice of load resistance by injecting approximately half the total current of the main input transistor through the PFET transistor M P. Furthermore, the current flowed through the device M P is controlled at the same changing rate as the total current due to 74

87 the bias voltage feedback from the drain node of the cascode transistor M C, called a selfbiasing current reuse technique. The appropriate amount of current through M P can be adjusted by the resistance ratio of two resistors in the voltage divider, R a and R b. Figure 4-. LNA schematic with the self-biasing current reuse technique of the redcolored portion. When the gate bias voltage of the main transistor M B is increased without the SBCR portion, the drain current i T of the M B is accordingly increased and then the increased whole current goes through the load resistor R d and cascode transistor M C. The larger load current increases the voltage drop across the load resistor R d and results in decreasing the drain voltages of the M B and M C. This causes difficulties in keeping M B and M C in saturation and thus degrades RF performance of the LNA. With the proposed SBCR technique, we can avoid a voltage headroom limitation since some portion of the drain current flows through the M P without degrading the behavior of the transistor M B. 75

88 Furthermore, the less current through the cascode transistor M C improves the performance of gain and NF by reducing parasitic capacitances at the drain of the transistor M B since the smaller size of the cascode transistor is required to handle less current. To prevent an ac current from flowing into the M P, the inductor L pm is employed as an RF choke. Another advantage of this SBCR circuit is that the fed-back voltage smoothes the current increment rate through the load resistor to hold the similar voltage at the output node and thus makes the IIP peaks less sensitive to the gate-source bias voltage due to the small change of the drain-source voltages of M B and M C. Voltage [V] Vd, Vo [V] V o V d Gate Bias Voltage VgMT [V] Current IpT, Iss [ma] w/o SBCR w/ SBCR I P Gate Bias Voltage VgMT [V] (a) (b) Figure 4-4. (a) Node voltages and (b) currents in the LNA with the SBCR technique. I T The simulated output voltage V o and drain voltage V d are plotted in Figure 4-4 (a) with the total current i T and the current i P from the PMOS current source in Figure 4-4 (b). The solid line represents the voltage and current with the SBCR technique and the dotted line does those without the SBCR. The variation of the voltage V o with the SBCR is about 0. V within the main gate-bias point of V and thus 0.8 V less than that without the SBCR. It means that the nonlinearity effect due to the drain-source voltage variation of 76

89 the devices of M B and M C is reduced since the transconductance is less modulated by the voltage difference between the gate and the drain, predicted by the following expression. g m = ( W ) μ C I L + λv n ox D DS (4.) 4. Wideband Derivative Superposition (WBDS) Method Only one IIP peak at the operating frequency can be achieved with narrow band topologies []-[4], [], [4] shown in Figure -6, Figure -9, and Figure -0 since the IIP peaks occurs only when the third-order Volterra kernel of the drain current of the auxiliary transistor has the same amplitude and opposite phase in the main transistor with respect to the composite Volterra kernel of its drain current. Since this cancellation occurs at a single frequency, these linearity enhancement techniques are effective for only a narrow-band LNA. Assuming that two narrow-band linearity-enhanced topologies [], [4] are optimized independently to obtain IIP peak at the low frequency corner in Figure 4-5 (a) and to obtain IIP peak at high frequency corner in Figure 4-5 (b) and then are merged together, two independent IIP peaks over the wide frequency range can be achieved as shown in Figure 4-5 (c). 77

90 IIP IIP IIP + = f L f f H f f L f H f (a) Aparin s topology (b) Ganesan s topology (c) Proposed topology Figure 4-5. Conceptual diagram of linearity behavior over an operating frequency (a) at the low-frequency optimized topology, (b) at the high-frequency optimized topology, and (c) the resulting IIP plot. Two different cancellation techniques [], [4] are adopted and modified to achieve a linearity-enhanced wideband LNA as shown in Figure 4-6, with reducing the number of an inductor simultaneously. The MDS technique is employed as shown inside the black dotted box (A) for the lower frequency IIP optimization at the operating frequency range and the alternative DS technique is modified and added up as shown inside the blue dotted box (B) for the higher frequency IIP optimization. To minimize the number of source inductors, L A is shared for two different topologies while providing the functionality of adjusting the IMD term out of phase at two different frequencies. The circuit functionality is analyzed by the Volterra series to show how high linearity can be achieved over the wide operating frequency. The frequency-dependent nonlinearity coefficients from the HB analysis are introduced below based on the definitions of the HB frequency-dependent nonlinearity coefficients given in Eq. (.9)-(.7). 78

91 V DD V IN Input Matching Network R d L d M C V OUT M A M B M F L B (A) L A (B) Figure 4-6. LNA schematic with wideband derivative superposition (WBDS) method. As defined in Eq. (.9)-(.7), using the extracted frequency-dependent nonlinearity coefficients of each device in Figure 4-6, the first-, second-, and third-order composite frequency-dependent nonlinearity coefficients are derived by summing all the frequencydependent nonlinearity coefficients of all the devices M A, M B, and M F as in Eq. (4.)-(4.4). g = g + g + g, HB A, HB B, HB F, HB g = g + g + g, HB A, HB B, HB F, HB g = g + g + g, HB A, HB B, HB F, HB (4.) (4.) (4.4) To observe the frequency-dependent nonlinearity coefficients as a function of frequency, the size of the main and auxiliary transistors is first determined. The gate bias voltage and offset voltages are applied properly by evaluating the DC transconductance characteristics so that the third-order derivatives of the DC transconductance sum up to zero within a certain gate bias voltage. Then the frequency-dependent nonlinearity coefficients of the M A and M B in the HB simulation are extracted and shown in Figure

92 from GHz to 7 GHz. In this HB simulation, the gate bias voltage of the main device M B is 560 mv and that of the auxiliary device is 48 mv, with the size 9 um/0 nm and 64 um/0 nm, respectively. st -order g B_HB nd -order g B_HB rd -order g B_HB g A_HB g A_HB g A_HB Figure 4-7. Polar plot of the frequency-dependent nonlinearity coefficients as a function of frequency. The first-, second-, and third-order frequency-dependent nonlinearity coefficients revolve to the clockwise direction in the polar plot while the amplitude is shrinking as frequency increases. As observed in Figure 4-7, the amplitude of the third-order Volterra coefficient is much less than one of the second-order frequency-dependent nonlinearity coefficients because most of the IMD terms are cancelled out with the proper device sizing and biasing, based on the DC transfer characteristics of the input transistors. As 80

93 expected, the IMD terms become the main contributions on the IMD due to feedback to the input side and mixing up with the two first-order terms. The mechanism of the frequency-dependent nonlinearity coefficients depending on frequency can be redrawn in the conceptual vector diagram as shown in Figure 4-8. If we can use the fact that all the Volterra kernels revolve to the clockwise direction as frequency increases, two independent topologies having the IMD cancellation techniques can be employed to provide two IIP peak points at two different frequencies. The f L and f H in Figure 4-8 (a)-(b) represent the lower frequency and higher frequency with respect to the center frequency in a wide operating frequency range. g B,HB V f L Im g B,HB V f L Composite rd -order contribution of M A & M B g A,HB V f L Re Im g B,HB V f H g B,HB V f H Composite rd -order contribution of M F & M B Shrunk and rotated due to frequency Re g F,HB V f H M B & M A M B & M F (a) (b) Figure 4-8. Conceptual vector diagram with SBCR and WBDS techniques (a) at low frequency and (b) at high frequency. 4.4 Derivation of IIP Expression Using Volterra Series The simplified LNA schematic with the SBCR technique and WBDS method is shown in Figure 4-9 (a). To verify how the proposed topology can achieve wideband linearity at high frequencies, the detailed analysis is done in Appendix C using the Volterra series with the equivalent circuit in Figure 4-9 (b). 8

94 V DD V IN Input Matching Network R d L d M C V OUT M A M B M F L B (A) L A (B) (a) (b) Figure 4-9. (a) Simplified LNA schematic with SBCR and WBDS techniques and (b) its equivalent circuit. In the IIP derivation using the Volterra series, we have the assumptions described below: ) The body effect is negligible, g bm 0. ) Except the gate-source capacitance C gs ) The C gs is bias-independent., all parasitic capacitances are zero. 8

95 4) The gate and source resistance of a transistor are ignored. 5) The series resistance of an inductor is ignored as well. 6) No channel length modulation, i.e., g. o 7) Very week input signals so that higher-order IMD terms than third-order ones are negligible. 8) ω a ω b ω, i.e., Δω 0. 9) The input is conjugately matched. 0) g 0, g 0, g 0, g 0. A A F F The final IIP expression derived by the Volterra series is given by Eq. (4.5)-(4.6). As shown in the simplified expression of Eq. (4.6), the IMD term becomes independent of the other circuit components. Instead, the two IMD terms can be adjusted by changing the two source inductances L A & L B, parasitic capacitances C A & C B, transconductance g B, and frequency ω. IIP = 6 Re 4g = B [ Z( sa )] C( sb,sb, sa ) w [ L ( C + C ) + C L ] A A ε C ( s B a ) B B ( ω ) [ jω ] g ( ) ga g B B B A A BLB gbl L C + jω g C L B B + + ε = gb g + + L ( C C ) C L B A B B B B jω g L g g g L + + B B A ω + + B F B g = g + g m(,g,c,c,l,l ) + (,g,c,c,l,l ) g B B A B A B A B B A B A B B gb [ ω jnω ] + g [ q( ω,g,c, C,L,L ) + jrω (,g,c,c,l,l ) g ] F B A B A B B A B A B B (4.5) (4.6) where the input impedance has the following expression while assuming a conjugate impedance matching, Z in ( s ) = sl A + + [ ga + gb + ( ga + gf )( gb + scb ) Z m ] sla + ( gb + scb ) s [ C + C + C ( g + sc ) Z ] A B A B B m Z m. (4.7) 8

96 In Eq. (4.5), the functions, m( ω, gb, CA, CB, LA, LB), n( ω, gb, CA, CB, LA, LB), q(, g, C, C, L, L ) ω B A B A B, and r ω gb CA CB LA LB (,,,,, ), represent the simplified functions of the circuit components including parasitic capacitances and DC transfer characteristics. By choosing the DC transfer characteristics and two inductances properly, the nonlinear coefficient ε becomes close to zero so that the IIP gets larger. 4.5 Summary For highly-linear wideband LNAs, linearity enhancement and wideband circuit techniques must be used simultaneously. The basic LNA topology starts with a sourcedegenerated topology with input and output matching networks. Two techniques, namely the WBDS and SBCR techniques are proposed to achieve high linearity over a wide frequency range. In the WBDS, two IIP peaks are realized by merging and modifying two linearity enhancement techniques [], [4]. Then linearity of each is optimized at the bandwidth boundaries to obtain a flat linearity response over the designed frequency range. SBCR is then used to increase the headroom in a shunt-peaking load. The proposed linearity-enhanced wideband LNA topology is analyzed using a Volterra series and its distortion cancellation is visualized by frequency-dependent nonlinearity coefficients. The proposed linearity enhancement techniques can be applied to the folded mixer to achieve high linearity such that an overall IIP meets a system-level linearity requirement in a multi-standard front-end receiver. For this, the tail current source of the folded mixer must be removed and replaced by two source-degeneration inductors along with two additional auxiliary transistors. Thanks to the folded mixer topology, the SBCR technique is not necessarily required to accommodate the large voltage headroom. 84

97 Chapter 5 Equation Chapter 5 Section LNA Design, Simulated and Measured Results 5. Circuit Design of the Proposed LNA The LNAs with SBCR technique and WBDS method are designed to verify the effects of the proposed topology on the IIP over a wide frequency range in a 0. μm CMOS process. The LNAs using the aforementioned linearity enhancement techniques are designed with two different input matching networks: one with a Chebyshev BPF input matching network and the other with a transformer-based input matching network. 5.. Input Matching Network In Figure 5- (a), the embedded third-order Chebyshev BPF input matching is used to resonate out the reactive part of the input impedance over a wide frequency range. On the other hand in the transformer-based matching network whose equivalent circuit is shown in Figure 5- (b), additional resonant tanks are used to extend the operating bandwidth. The component values of the two matching networks are summarized in Table. 85

98 (a) (b) Figure 5-. Input matching network (a) Chebyshev BPF matching (b) transformerbased matching. Table. Component values of the Chebyshev BPF and transformer-based matching networks. Chebyshev BPF Transformerbased Chebyshev BPF Transformerbased C 55 ff 56 ff L 0.5 nh.9 nh C 775 ff 60 ff L or L P.47 nh. nh C 50 ff 750 ff L S -. nh L.69 nh.9 nh L g.9 nh.6 nh 5.. Noise Models One of the key design goals is to minimize the noise figure while maximizing the gain and linearity of an LNA. Since the noise performance of the LNA is so critical, an accurate noise model in a MOS transistor is essential, which implies that a long-channel MOS noise model doesn t hold any longer as process scales down. More accurate noise models have been proposed for short-channel MOS devices: one includes high-field effects [5] and the other one includes induced gate current noise [5], [5]. The most significant noise sources of a MOS transistor at high frequencies are the drain current noise and the induced gate noise. The traditional MOS noise model is modified to include an increased drain current noise resulting from high-field effects in short-channel devices. In this case, the drain noise current is expressed as in (5.) 86

99 i = 4kTΔfγ g nd d 0 (5.) where γ is a bias-dependent noise coefficient, k is the Boltzmann s constant, T is the absolute temperature, f is the bandwidth, and g d0 is the zero-bias drain conductance of the device. The coefficient γ is equal to / for long-channel devices in strong inversion, but is to for short-channel devices due to hot electron effects [5]. The drain conductance g d0 for short-channel devices is given by W g = μ C V V. (5.) ( ) d0 eff ox GS th Leff where μ eff is the effective electron mobility, C ox is the gate-oxide capacitance per unit area, W is the channel width, L eff is the effective channel length, V GS is the gate-source bias voltage, and V th is the device threshold voltage. At high frequencies, an induced gate noise becomes significant, which arises from the distributed gate capacitance and channel resistance of the device as shown in Figure 5-. The induced gate noise current is expressed i = 4kTΔ fγ g (5.) ng g g g ( C ) oxwleff 4ω = (5.4) 45g d 0 where δ is the bias-dependent noise coefficient which has value of 4/ in long-channel devices and increases in short channel devices and at high gate-source and drain-source voltages. Since the induced gate noise is partially correlated with the drain channel noise current, a correlation coefficient is defined as shown in (5.5) [5]. c = i i ng i * nd i ng nd (5.5) 87

100 c can be predicted theoretically as j0.95 in long-channel devices and is purely imaginary, reflecting the capacitive coupling between the drain channel and induced gate noise sources. Figure 5-. Distributed gate capacitance and channel resistance at high frequencies. The noise model in [5] can be extended for an MOS transistor in weakly inversion (WI) region [], resulting in γ=/, δ=45/6, c=j0.707, and g d0, WI I D = (5.6) ( kt / q) where I D is the drain saturation current of the weakly inversion transistor and q is the electron charge. From the equations of (5.)-(5.6), we can get the following equation (5.7) and make an interesting observation. While the weakly inversion transistor draws a small amount drain current, its induced gate noise becomes significant since it is inversely proportional to the drain current. ( ox eff ) ( ) 6 Δ γω / ng 45ID i kt f C WL kt q = (5.7) 5.. Circuit Design Two LNA prototypes employing the WBDS and SBCR techniques are designed in a 0. μm CMOS process to verify the effectiveness of the proposed topology. One LNA 88

101 uses a Chebyshev matching network while the other uses a transformer-based matching network. The simplified LNA is shown in Figure 5- with a buffer amplifier added for test purposes. Shunt-peaking is used to widen the output bandwidth of the load network and a buffer amplifier is added for test purposes. The component values are summarized in Table. Figure 5-. Simplified schematic of linearity-enhanced wideband LNAs. Table. Component values of the designed wideband LNA prototypes. Common Chebyshev BPF Transformer-based M A W u /L=.0um/0.um, m= L A 0.4 nh 0.50 nh M B W u /L=.0um/0.um, m=96 L B 0.69 nh 0.69 nh M C W u /L=.0um/0.um, m= L pm.90 nh.90 nh M F W u /L=.0um/0.um, m= R d 49 Ω 54 Ω M P W u /L=.0um/0.um, L d.4 nh.4 nh m=480 M W u /L=.0um/0.um, m= R a 0 KΩ 0 KΩ M W u /L=.0um/0.4um, m=96 R b 40 KΩ 40 KΩ 89

102 In the first design step, the width of the three transistors M A, M B, and M F is determined to achieve the highest IIP in dbv based on the DC transfer characteristics with a.v supply voltage so that the composite rd -order DC characteristic is set to near zero as done in the narrow band DS topologies. The IIP in dbv with the size of the determined transistors is simulated in DC analysis option and the IIP curve shows three peaks around at the gate voltage of 50 mv as shown in Figure 5-4 (d). But the coupling and frequency effects are not taken into account in the IIP curve. To estimate a gate bias voltage and two inductances more accurately, the frequency-dependent nonlinearity coefficients extracted from the frequency-domain analysis are used. The two inductance values of L A and L B are optimized with the lab-customized MATLAB program using the frequency-dependent nonlinearity coefficients of the transistors themselves extracted from the HB analysis. In the proposed topology, the size of the cascode transistor M C is one third of the main transistor M B since the smaller device reduces parasitic capacitance limiting bandwidth and minimizes nonlinearity of the transconductance of the cascode device M C. It can be achieved due to the SBCR technique without sacrificing gain. The PMOS device M P and two voltage-divider resistors R a and R b are chosen to make approximately half the total current flow through the main device M B and two auxiliary devices M A and M F, while maintaining the drain voltage of the main device at around 0.6 V. The RF choke inductance L pm prevents an ac current from flowing reversely through the PMOS device, resulting in reducing the gain. 90

103 ga/f, ga/f, ga/f gb, gb, gb Gate Bias Voltage VgMT [V] (a) Gate Bias Voltage VgMT [V] (b) ga, gb, gf, g IIP [dbv] Gate Bias Voltage VgMT [V] (c) Gate Bias Voltage VgMT [V] (d) Figure 5-4. First-, second-, and third-order DC transfer coefficients of (a) the auxiliary and (b) main transistors, (c) third-order coefficients and superposition, (d) calculated IIP dbv in the proposed topology. The source-follower buffer amplifier is designed to drive an external 50-Ω load and biased by a current mirror independently to de-embed the power consumption. The tail current source of the buffer amplifier has twice the unit length, i.e., 40 nm, to provide high output impedance. In nominal condition, the gate bias voltage of the main transistor M B, V gmt, is 560 mv and those of two auxiliary transistors, V gst, V gft, are 400 mv, 60 mv smaller than V gmt. This offset voltage of 60 mv drives the main device in saturation and the auxiliary devices in weak inversion, resulting in the opposite polarities of the IMD terms. 9

104 The micrographs of two designed LNA prototypes are shown in Figure 5-5: (a) LNA with transformer-based input matching network and (b) LNA with Chebyshev BPF input matching network. In the layout, ground-guard ring and substrate taps are used to reduce substrate noise coupling. All signal grounds are connected with a thick top metal to reduce connection resistance such that traces have a low return resistance. The same layout strategy is applied to all power grounds as well. (a) (b) Figure 5-5. Chip micrographs of the proposed LNAs with (a) transformer-based and (b) Chebyshev BPF input matching networks. 9

105 5. Simulated and Measured Results A. Frequency Response The simulated and measured results of gain, S, and NF are shown in Figure 5-6 (a) and Figure 5-6 (b) show the simulated and measured S, gain, and NF of the two prototypes. The dotted and solid lines represent the simulated and measured performance, respectively. The LNA with the Chebyshev matching network shows the db bandwidth from. GHz to 6 GHz with the maximum gain of.7 db and the minimum NF of 4.8 db. The LNA with the transformer-based matching network shows the db bandwidth from GHz to 5. GHz with the maximum gain of.4 db and the minimum NF of 4.9 db. Both LNAs show S>-0dB at some frequency bands. The poor S comes from the complexity of the linearity-enhanced topology and design procedure to achieve high linearity, i.e., first the size of the three transistors is determined and then two degeneration inductors are chosen. More analytical analysis is necessary to address the input matching issue. S, Gain, NF [db] 0 5 Gain 0 NF 5 0 S Frequency [GHz] S, Gain, NF [db] y y 0 5 Gain 0 NF S Frequency [GHz] (a) (b) Figure 5-6. Simulated and measured results of the designed LNA (a) with transformerbased matching network and (b) with Chebyshev BPF matching network. 9

106 The overall stage transconductance G m does not benefit from deeply scaled CMOS technologies due to matching constraint. Bode-Fano limit [5] for a parallel RC network as shown in Figure 5-7 is ln ( ) d π ω (5.8) Γ ω RC 0 where Γ(ω) is input reflection coefficient, R input parallel resistance, and C input parallel capacitance. The in-band reflection coefficient is represented by /ΔfRC Γ( ω) e (5.9) inband where f is the bandwidth of the lossless input matching network. In the proposed linearity-enhanced LNA topologies, the parallel R and C are fixed for linearity enhancement. Under the given bandwidth of the input matching network, the input reflection coefficient is determined. Figure 5-7. Parallel RC load impedance for Bode-Fano limit. Furthermore, since the equivalent G m is inversely proportional to frequency, large NF at high frequencies is inevitable as frequency increases in the LNA with filter-type input matching network. Some amount of the NF degradation is caused by the input matching. For example, the Chebyshev input matching network has around.5 db insertion loss over the operating bandwidth, directly resulting in the NF degradation. To observe how much NF degradation is caused by an input matching network, the optimum NF (NF opt ) is simulated without the matching network and compared to the measured NF in the LNA 94

107 with the Chebyshev input matching network as shown in Figure 5-8. With some limitation on the input matching due to the linearity-enhanced topology, if a linearityenhanced wideband LNA is properly designed, NF less than 4 db over 6 GHz bandwidth can be achieved. NF [db] Measured NF Simulated NF opt Frequency [GHz] Figure 5-8. NF and NF opt of the LNA with Chebyshev matching network. The NF performance of the LNA with transformer-based matching network is compared with and without the SBCR technique in Figure 5-9. Without the SBCR, the LNA shows a little better NF. In order to observe noise contributions from the circuit devices, the noise summary plots are shown in Figure 5-0. Figure 5-0 (a) shows the percentage of the noise contribution and Figure 5-0 (b) shows the absolute amount of the noise contribution in V. Without the SBCR, larger current flows through the cascode device MC causing more noise contribution. However, the overall noise spot noise 95

108 without the SBCR is a little smaller than that with the SBCR, the same as the NF simulation results as shown in Figure Measured w/ CR Measured w/o CR 8 NF [db] Frequency [GHz] Figure 5-9. NF comparison of the LNA with transformer-based matching with or without the SBCR. Noise Percentage w/ Noise Percentage w/o (a) 96

109 Noise Voltage V^ w/ Noise Voltage V^ w/o (b) Figure 5-0. Noise summary of the devices in the LNA with Chebyshev BPF matching. B. Linearity: IIP The IIP of two linearity-enhanced wideband LNA prototypes is simulated and measured in a 0. μm CMOS process. For IIP measurement, two tone signals are applied as an input signal after combining two sinusoidal signals from two signal generators with an external wideband power combiner. The output fundamental tones and third-order tones are monitored using the Agilent Spectrum Analyzer E4440A with the settings of KHz SPAN, 9. Hz RBW, and 90 Hz VBW to measure their amplitude more accurately. The IIP is measured with 500 KHz frequency spacing in two input tones for most of the cases, as done in the simulation. To minimize the linearity degradation due to the buffer amplifier, large current of around 4 ma is consumed. The IIP of the LNA circuit itself is de-embedded by system level simulation with the measured stand-alone results of the buffer amplifier such as gain and linearity. 97

110 First of all, to verify the IIP peak versus the gate bias voltage of the main transistor, the LNA with Chebyshev BPF input matching network is measured at 4GHz which has the highest IIP peak over the frequency range. As we can see in Figure 5-, the IIP has the peak value of +.5 dbm at the gate bias voltage of 560 mv which has the offset voltage of 60 mv with respect to two auxiliary transistors. The simulated offset voltage was mv to obtain the highest IIP peak in this LNA at 4 GHz. Figure 5- shows the IIP extrapolation plot at 4 GHz in the same LNA with Chebyshev BPF matching network. As shown in Figure 5-, the input power range having a -db slope in the IMD output signal is relatively narrow, compared to the IIP extrapolation plot of the LNAs without linearity enhancement techniques. More research needs to be performed in the future to analyze why this happens. 5 0 IIP [dbm] Gate Voltage [V] Figure 5-. IIP vs. gate bias voltage at 4GHz in the LNA with Chebyshev BPF input matching network. 98

111 60 p 0 0 IIP [dbm] Pin [dbm] Figure 5-. IIP extrapolation plot at 4GHz in the LNA with Chebyshev BPF input matching network. On the other hand, to show the extent of IIP improvement with the SBCR technique, the IIP versus the frequency range is simulated and measured as shown in Figure 5- in the LNA with transformer-based input matching network. The blue line represents the IIP curve with the SBCR technique and the black line represents the IIP curve without the SBCR. The dotted and solid lines show the simulated and measured results, respectively. With the SBCR, the LNA achieves around 0 db greater IIP value under the same gate bias condition. 99

112 0 5 0 IIP [dbm] Frequency [GHz] Figure 5-. IIP plot over frequency range in the LNA with transformer-based input matching network. The IIP is simulated and measured over the operating frequency range to confirm the effectiveness of the proposed linearity-enhanced wideband topology with two LNAs. The simulated and measured results in Figure 5-4 show high linearity over the wide frequency range. The LNA with the transformer-based matching network shows the maximum IIP of +5.6 dbm and relatively flat IIP response of + dbm on average from GHz to 5. GHz. The LNA with the Chebyshev matching network has the maximum IIP of +.5 dbm at 4 GHz and shows the IIP of +0.6 dbm on average from. GHz to 6 GHz. 00

113 Meas.@Chebyshev Meas.@Xfmr 5 0 IIP [dbm] IIP [dbm] Frequency [GHz] Frequency Spacing [Hz] (a) (b) Figure 5-4. Simulated and measured IIP (a) vs. frequency range and (b) vs. frequency spacing plots in the wideband LNAs with transformer-based matching and with Chebyshev BPF matching. An interesting issue in a wideband LNA is the IIP performance when differently spaced interferers exist within the multiple standard bands. To observe this important measure for a multi-standard wideband LNA, two test tones with different frequency spacing are applied. The resulting IIP performance is shown in Figure 5-5. The IIP holds steady for small frequency spacing and starts to degrade for larger frequency spacing since the linearity enhancement techniques lose their effectiveness. This explains that the highest IIP can be obtained in the proposed linearity enhancement technique when two test tones are closely placed. For multi-standard wideband LNAs, the IIP measurement setup should be taken into account carefully depending on a field environment having multiple coexisting in-band interferers which are not out-of-band interferers any longer. 0

114 Meas.@4G Meas.@G Meas.@5G y q y p g q Meas.@4G Meas.@G Meas.@5G IIP [dbm] IIP [dbm] Frequency Spacing [Hz] Frequency Spacing [Hz] (a) (b) Figure 5-5. IIP vs. frequency spacing plots of (a) transformer-based matching and (b) Chebyshev BPF matching LNAs at different reference frequencies. C. Linearity: IIP The IIP performance of two LNA prototypes is measured at four different IMD frequencies as shown in Figure 5-6 (a)-(b). The IIP curve at the lowest IMD frequency f -f shows the highest value, which is caused by high-pass filtering effects of ac coupling capacitors at the LNA and buffer outputs. IIP [dbm] Meas.@f-f Meas.@f Meas.@f+f Meas.@f Frequency [GHz] Frequency [GHz] (a) (b) Figure 5-6. IIP vs. frequency plots of (a) transformer-based matching and (b) Chebyshev BPF matching LNAs at different nd -order IMD frequencies. IIP [dbm] Meas.@f-f Meas.@f Meas.@f+f Meas.@f 0

115 For multi-standard RF front-end receivers, some issues should be brought up to address IIP measurement setup and falling frequency shift by changing frequency spacing within a wide bandwidth. In general, when the IIP is measured in a narrow-band or wideband LNA, the frequency spacing of two input tone signals are small so that two tones experience the similar gain and nonlinear behavior. Furthermore, even the frequency spacing between interference signals in wideband applications is not far away, compared to the multi-standard applications. On the other hand, the spacing for multistandard applications can be larger than the bandwidth of one of the multiple standards. To emulate the effects of the second-order intermodulation distortion in multi-standard applications, different IIP measurement setups are visualized in Figure 5-7. As we can see in Figure 5-7 (a), when two tones are assigned at the low-edge frequency and are put closely, we have three IMD tones at f, f +f, and f which can deteriorate IIP performance due to the feedback to the input and re-mixing with the fundamental signals. However, when we address and measure the IIP, most of the IMD tones fall out of band, but they fall in band, deteriorating nonlinearity of the receiver. As the frequency f increases with the f fixed, the f falls out of band but the f -f is about to fall in band as shown in Figure 5-7 (b). Finally, the f -f comes in band and three higher IMD tones are going out of band as shown in Figure 5-7 (c), with further increasing the spacing. The similar nonlinear behavior will occur when two tones are assigned at the center or at the high-edge frequency. 0

116 (a) (b) (c) Figure 5-7. Mechanism of IMD tones depending on frequency spacing. To observe the effects of IMD on the IIP, three different measurements are set up: ) The f is fixed at GHz and the f is shifted up. ) The f and f are centered at the center frequency of the bandwidth (i.e. 4 GHz in this case), and each is shifted down and up. ) The f is shifted down and the f is fixed at 5 GHz. With these three measurement setups, the IIP of two LNA prototypes is measured at four different IMD frequencies to show the amount of IIP degradation as shown in 04

117 Figure 5-8 (a)-(f). As the frequency spacing increases, the IIP value at f -f is degraded rapidly since the attenuation of the f -f term by ac coupling capacitors is decreasing. On the other hand, device and layout parasitic starts to get involved in the IIP degradation as the frequency f -f increases. IIP [dbm] IIP [dbm] Frequency Spacing [Hz] q y p g q (a) (b) Meas.@G f-f Meas.@G f Meas.@G f+f Meas.@G f Meas.@4G f-f Meas.@4G f Meas.@4G f+f Meas.@4G f Frequency Spacing [Hz] IIP [dbm] IIP [dbm] y q y p g q Frequency Spacing [Hz] (d) (e) Meas.@G f-f Meas.@G f Meas.@G f+f Meas.@G f Meas.@4G f-f Meas.@4G f Meas.@4G f+f Meas.@4G f Frequency Spacing [Hz] 05

118 IIP [dbm] Meas.@5G f-f Meas.@5G f Meas.@5G f+f Meas.@5G f Frequency Spacing [Hz] IIP [dbm] Frequency Spacing [Hz] (c) (f) Figure 5-8. IIP vs. frequency spacing plots of transformer-based matching (a)-(c) and Chebyshev BPF matching (d)-(f) LNAs at different nd -order IMD frequencies with different reference frequencies Meas.@5G f-f Meas.@5G f Meas.@5G f+f Meas.@5G f 5. Summary Two LNA prototypes are designed and fabricated in a 0. μm CMOS process. The circuit design procedure for the proposed LNA topologies are described to achieve high linearity. Their simulated and measured frequency responses are demonstrated and show good match. The IIP and IIP are measured with several measurement setups to address the issues brought up for multi-standard applications in this research. This new approach can help what kind of performance and measurement setup should be carefully taken into account in future research for multi-standard applications or software-defined radios. These approaches emphasize the importance of the second-order linearity in the wideband receiver under the co-existence environment of in-band strong interference signals. 06

119 Chapter 6 Conclusions The goal of this dissertation was to implement both a wideband RF front-end receiver and a linearity-enhanced wideband LNA. The details of the research scope were: ) Designed a wideband RF front-end receiver. ) Demonstrated DC offset mechanisms, partitioned different DC offsets depending on the mechanisms, and showed the relationship between DC offset and nonlinearity. ) Proposed and analyzed a linearity-enhanced wideband LNA topology. 4) Designed linearity-enhanced wideband LNA prototypes and verified the effectiveness of the proposed topology. As a part of research goals, the wideband RF front-end receiver including the LNA, active balun, and folded mixer is designed. It shows reasonable performance except linearity. DC offsets are segmented by different mechanisms and quantified by the measured results. Furthermore, the relationship between DC offset and linearity is derived and demonstrated by simulated, calculated and measured results in the wideband RF front-end receiver which has a differential topology from the active balun to the mixer. 07

120 To achieve high linearity in a wideband LNA, two linearity enhancement techniques are proposed: the wideband derivative superposition method to obtain two IIP peaks over a wide frequency range and the self-biasing current reuse technique to provide sufficient voltage headroom. The effectiveness of the proposed topology is analyzed by the Volterra series and then supported by conceptual diagram inspired from the behavior of the extracted frequency-dependent nonlinearity coefficients. The simulated and measured results in two LNA topologies show high IIP over the wide frequency range. Furthermore, the IIP performance as a function of frequency spacing of two test tones is demonstrated to estimate IIP performance variation when differently spaced interferers are received. Figure 6-. IIP comparison plot with narrowband and wideband LNAs. The IIP performance depending on the frequency spacing is characterized to emulate blocker environment for multi-standard applications. The measured results are shown. Furthermore, the IIP performance is also characterized to observe the effects of the second-order intermodulation distortion terms on linearity. 08