Design of envelope amplifier based on interleaved multiphase buck converter with minimum time control for RF application

Transcription

1 Design of envelope amplifier based on interleaved multiphase buck converter with minimum time control for RF application Universidad Politécnica de Madrid P. M. Cheng

2 Introduction Complex signal and non-constant envelope in new wireless standards High efficiency PA architectures are needed for high peak to average power ratio envelope. D.Brubaker, Optimizing Performance and Efficiency of PAs in Wireless Base Stations: Digital pre-distortion reduces signal distortion at high power levels, White Paper, Texas Instruments, February

3 Power amplifer architectures Envelope Tracking (ET) DC-DC converter with output Voltage in proportion to RF envelope Envelope elimination and restoration (EER) 3

4 Envelope amplifier solutions Switching dc-dc converter High efficiency of power amplifier low Bandwidth or low power applications High switching losses for wide envelope bandwidth Envelope reference Switching DC- DC converter PA RF OUT V. Pinon, F. Hasbani, A. Giry, D. Pache, C. Gamier, "A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply," Solid-State Circuits Conference, ISSCC Digest of Technical Papers. IEEE International, vol., no., pp , 3-7 Feb

5 Envelope amplifier solutions Linear Regulator in parallel with Switching dc-dc converter High efficiency Fast dynamic response (Wide Bandwidth) Envelope reference Switching DC- DC converter Linear Regulator PA RF OUT F.Wang, D.F.Kimball, J.D.Popp, A.H.Yang, D.Y.Lie, P.M.Asbeck, L.E.Larson, An Improved Power-Added Efficiency 19-dBm Hybrid Envelope Elimination and Restoration Power Amplifier for g WLAN Applications, IEEE Transactions on Microwave Theory and Techniques, Volume 54, Number 12, December 2006, pages

6 Envelope amplifier solutions Multilevel DC-DC converter in series with a linear regulator V IN dc-dc converter Multilevel converter V A Linear Reg. Control V O V R Control Power saved Voltage V R V O Voltage nth level nth level V R High efficiency V A V O nd 2 level nd 2 level st 1 level st 1 level High system bandwidth time time 6

7 Multilevel converter Proposed solution voltage d=1 d=0.75 d=0.5 d=0.25 Minimum time control time Minimum time control PWM d=50% PWM d=25% 7

8 Multiphase buck converter Operates in open loop Without current and voltage senses Only has discrete duty cycles d=i/n, i=1, 2 n (n is the number of phases) Inductor design trade off Small L for fast transition Small L leads to high losses 8

9 Minimum time control A single on-off action of power switches for each phase Control parameters (t on and t off ) are stored in look-up table Minimum time control Charge balance Z. Zhao, A. Prodic, Continuous-Time Digital Controller for High-Frequency DC-DC converters, IEEE Transactions on Power Electronics, vol. 23, no. 2 March 2008, pp t Minimum transition time is fixed by filter and the voltage before and after the transition ON, i t i = = f ( L, C, V f ( L, C, V I 9 I, V, V F F ) )

10 Multilevel converter Multiphase buck converter Minimum time control Very fast voltage transition No need to know the load current for transition The currents unbalance does not have influence during the transition 10

11 Control strategy in 4 phases buck converter phase1 phase2 phase3 phase4 90 delay 180 delay 270 delay Minimum time control t t t t t Transition is synchronized with rising or falling edge of PWM Different t ON,i and t OFF,i but the same t for each phase After the transition the phases maintain the synchronization 11

12 Control implementation in FPGA The change of the duty cycle memory t ON,1, t ON,2, t ON,3, t ON,4, Δt Input data quantization Duty cycle reset reset PWM1 counter1 PWM2 counter2 PWM3 register Counter Pwm_state PWMA PWMB PWMC reset counter3 PWM4 Non_pwm_ state PWMD counter4 reset Initial value 12

13 Multilevel converter experiment result V IN = 12V f sw = 1MHz 3V t on1 6V Output voltage t on2 Current unbalance t on3 t on4 Phase currents transient around 1.5 switching period 13

14 Envelope amplifier experiment result V IN = 12V f sw = 1MHz Output of envelope amplifier Output of multilevel converter 14

15 Conclusion Solution for the wide bandwidth envelope amplifier Based on multiphase buck converter with minimum time control Multiphase buck converter works in open-loop V IN Without voltage and current feedback Multiphase dc-dc converter buck converter Linear Reg. Minimum time control algorithm for multiphase buck converter is V based on R Minimum time Control charge balance Without over-shoot and oscillation after transition The proposed solution can track fast envelope change with relatively low switching frequency and it also can be used for DVS application It is necessary to improve design for higher frequency envelope and optimize the efficiency in the future V A Control V O 15