Non-linear Control for very fast dynamics:

Transcription

1 (CEI) Non-linear Control for very fast dynamics: Tolerance Analysis and System Limitations Universidad Politécnica de Madrid Madrid

2 DC-DC converter for very fast dynamics Current steps 5 V VRM 1V - 2 V I o = 20 A max. 0 A 20 A 100 A/µs I o Switching frequency Switching losses Robustness at very high frequency V o Limit Bandwidth 0.2 V max. - Noise - Parasitic influence - Plant variation Bandwidth Limit NON Linear + Linear Control

3 Combination of NON-Linear + Linear Control NON Linear Control Fast transients Load steps 0 A + - Δ IL 2 Δ I 2 L - K e K c *I Cout - + V ref v out SLOW Linear Control LOAD Accurate regulation

4 Non-linear control for current steps: Minimum voltage drop Sw_control I o ΔI o I Cout LOAD Trip point 1 I Cout 0 A Trip point 2 This strategy produces minimum drop I L ΔI o

5 Experimental results: 5MHz integrated Buck 1V-2V 1A 4 µf 100nH 90% A linear control would require 800kHz bandwidth

6 Experimental results: 5MHz integrated Buck

7 Current sensor: design goals To design a parallel RLC network A I Cout Scaled impedance magnitude Scaled impedance magnitude t I s Equal phases and/or same time constants Same phases Cout current (I Cout ) Sensor Measurement (I s )

8 System overview: Current sensor Capacitor current sensing method: RLC network Output capacitor 2 I Cout Cout Cs ΔV O Z Cout 1 ESL I s R1 ESR Rs - + R1 I s Vs

9 Limitations: Ceramic capacitor aging Aging data from different manufacturers -20% C and ESL. f res 1.25 times (From 1.59MHz to 1.98MHz) -25% C and ESL. f res 1.32 times (From 1.59MHz to 2.1MHz) Best aging variation case Worst aging variation case

10 Influence of C out tolerance: System overview MLC Capacitor tolerances: C depends on dielectric: Dielectric Tolerance % Cout Current Load X7R +/- 10 Converter Cout (MLCC) Sensor X5R +/- 20 Y5V +80, -20 ESR no manufacturer data ESL no manufacturer data

11 Limitations: System operation Design specifications: Switching frequency: 5MHz Cout resonant frequency: 1.5MHz (approx.) Cout dielectric: X7R (Thermic variation +/- 15%) System operates in inductive side Cout ESR ESL Cout MLCC Capacitive side Inductive side Cout Resonant Frequency Switching Frequency

12 Measurement Failure If sensor is designed for inductive side, but ESL reduces drastically and system changes from inductive to capacitive side: Incorrect performance 0 AM1.I u 17.50u 18.00u 18.27u As a result: C out changes phase, impedance and time constant drastically Real and measured current are no longer in phase Different amplitudes C out actual current C out sensed current Current sensor limitation: Assure by design that system always operates in the same side

13 Sensitivity Analysis (inductive side) C out = 4 uf ESR = 7 mω ESL = 2.5 nh F sw = 5.15 MHz Z = Ф =90º Nominal Case (NC)

14 Proposed solutions: Frequency loop to adapt hysteretic band Frequency loop

15 Simulation of the whole system: Voltage step 2.09 Voltage step 2 µs (1 switching period)!! 1.50 V OUT_STEP V OUT 1.96V 2V m 1V Ttrack = 2.12us 78.00u 80.00u 82.00u 83.00u Voltage step (V OUT_STEP ) Output voltage - System works properly! - Frequency loop does not interact with non-linear loop! - Frequency changes from 5MHz to 7.10 MHz (voltage step 1V to 2V)

16 Simulation of the whole system: Load step 1.50 Load step I LOAD V OUT m 0.5A 1.5A 100 A/us u u u Output voltage Load current

17 Simulation of the whole system: Frequency step Frequency step 5.50Meg 5.40Meg f STEP f SW 5.20Meg 5.00Meg 95.00u u u Switching frequency Frequency step (f STEP ) -System works properly! - Frequency loop adjust the switching frequency to the new nominal value (from 5 MHz to 5.5 MHz on approx. 600 us)

18 Simulation of the whole system: Frequency step 6.00Meg Frequency step 5.50Meg V OUT f STEP 5.00Meg 4.50Meg u u u Frequency step Output voltage -System works properly! - Frequency loop adjust the switching frequency to the new nominal value (from 5 MHz to 5.5 MHz -Frequency loop does not interact with linear loop! -Output voltage does not change in a frequency step

19 Summary: Tolerance Analysis Influence of C out tolerance A 20% deviation of C or ESL can produce a 20% deviation in f SW, affecting the output voltage ripple Design must guarantee for maximum tolerance that the system is always in the same side (capacitive or inductive side) Adding external C out External C out can drastically affect f SW converter Proposed solution Frequency loop to keep converter operation around nominal f SW Frequency adjustment adapting hysteretic band Effective solution to reduce C OUT influence: C OUT tolerance or external C OUT Validated by simulations