A Modified All-Digital Polar PWM Transmitter

Transcription

1 A Modified All-Digital Polar PWM Transmitter Muhammad Touqir Pasha a, Muhammad Fahim Ul Haque a,b, Jahanzab Ahmad c, Ted Johansson a a Linköping University, Linköping, Sweden b NED University of Engineering and Technology, Karachi, Pakistan c Intel Corporation, High Wycombe HP2 4XF, United Kingdom

2 Outline 2 Introduction Transmitters for high data rate communication and high efficiency Transmitter architectures using SMPAs The All-Digital Modified Polar PWM Transmitter Principle FPGA implementation Results Simulations Measurements Summary and conclusions

3 3 Introduction Baseband Encoder & Modulator RF Modulator PA Filter Modern wireless data communication requires flexible transmitter architectures for multi-rate, multi-band signals. Possible to implement both baseband and RF using digital CMOS circuits. For R&D and small-volume products, this may be in the form of high-performance Field Programmable Gate Arrays, FPGAs. Modulation techniques, such M-QAM and OFDM, generate signals with non-constant amplitudes of wide range. To improve transmitter high efficiency, switch-mode PAs (SMPAs) has gained popularity, but use constant amplitude (on/off). We need special transmitter architectures to include the amplitude information.

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5 5 Introduction Baseband Encoder & Modulator RF Modulator PA Filter Modern wireless data communication requires flexible transmitter architectures for multi-rate, multi-band signals. Possible to implement both baseband and RF using digital CMOS circuits. For R&D and small-volume products, this may be in the form of high-performance Field Programmable Gate Arrays, FPGAs. Modulation techniques, such M-QAM and OFDM, generate signals with non-constant amplitudes of wide range. To improve transmitter high efficiency, switch-mode PAs (SMPAs) have gained popularity, but use constant amplitude (on/off). We need special transmitter architectures to include the amplitude information.

6 Introduction 6 Outphasing: two constant-envelop signals with varying phase difference. V PA V in Signal Decomposer Signal Combiner V out PA 2 R L V 2 Issues: lification paths mismatch, combiner implementation.

7 Introduction 7 RF-PWM: pulse-train with varying duty cycle at RF. Issues: Small dynamic range at high carrier frequency.

8 Introduction 8 Polar PWM: amplitude PWM at IF, phase-shifted carrier

9 Introduction 9 Polar PWM issues: image distortion

10 Introduction Polar PWM issues: image distortion enhanced by non-linear SMPA

11 An All-Digital Polar PWM Transmitter Modified Digital PWM (MD-PWM) Combines digital PWM and outphasing Increased efficiency (SMPAs) Outphasing eliminates image and alias distortion => improved ACLR and EVM compared to a D-PWMT. T MC x(nt LC ) C O R D I C a(nt LC ) (nt LC ) Quant a (nt LC ) PWM x PWM v PWM e(nt LC ) PA Cos - PPM v v PA v comb PPM v 2PWM v 2 PA v PA2 Combiner Isolator Filter R L T HC MD-PWMT

12 M. T. Pasha, M. F. U. Haque, J. Ahmad, T. Johansson A Modified All-Digital Polar PWM Transmitter IEEE Transactions on Circuits and Systems-I, Vol. 65, Issue 2, pp , 28.

13 An All-Digital Polar PWM Transmitter 3 T MC x(nt LC ) C O R D I C a(nt LC ) (nt LC ) Quant a (nt LC ) PWM x PWM v PWM e(nt LC ) PA Cos - PPM v v PA v comb Combiner v 2PWM v PA2 PPM PA v 2 Isolator Filter R L T HC (a).5 5 Time(ns) 2 25 (b).5 5 Time(ns) 2 25 (c).5 5 Time(ns) 2 25 (d).5 5 Time(ns) 2 25 (e).5 5 Time(ns) 2 25 (f).5 5 Time(ns) 2 25 (g)

14 An All-Digital Polar PWM Transmitter (c) 4 T MC C a(nt LC ) a (nt LC ) x Quant PWM PWM O Time(ns) x(nt LC ) R (d) v PWM D e(nt LC ) PA I Cos - PPM v v PA.5 v comb Isolator Filter C Combiner (nt LC ) v 2PWM 5 Time(ns) v PA2 2 R L 25 PPM(e) PA v 2.5 T HC 5 Time(ns) 2 25 (f).5 5 Time(ns) (g) 5 Time(ns) 2 25 (h). 5 Time(ns) 2 25 (i). 5 Time(ns) 2 25

15 FPGA implementation 5 Intel/Altera Stratix IV GT FPGA with integrated.3 Gbps TRXs. PWM + high speed multipliers: FPGA core logic. PPM: FPGA core logic + TRX. Baseband Processing Software PWM Look-Up Table PWM T LC PWM Register FPGA Core T MC S E R I A L Zero Register Multiplier Multiplier Zero Register M U X M U X PPM Look-Up Table PPM PPM Look-Up Table PPM Transceiver Register Transceiver Register S E R I A L S E R I A L T HC FPGA Transceivers

16 Simulation results 6 Circuit simulations using Cadence SpectreRF and Keysight ADS, 3 nm PDK. LTE 2 MHz uplink signal, PWM freq = 64 MHz, different phase resolutions. Normalized Output litude MD PWMT 34 Phase MD PWMT 6 Phase MD PWMT 86 Phase D PWMT Normalized Input litude litude linearity AM-AM EVM and ACLR

17 Measurement setup 7 LTE 2 MHz uplink signal Software Hardware Transceiver PA MATLAB FPGA Core Combiner Attenuator Spectrum Analyzer Transceiver2 PA Altera Stratix IV GT ASIC MATLAB: CORDIC FPGA PA chips Discrete lab components + instrument

18 Measurement setup 8 Measurement setup: FPGA, PAs 3 nm class-d PAs, area.6 mm 2

19 Measurement results 9 Normalized Output litude D PWMT MD PWMT Normalized Power (db) D PWMT MD PWMT Normalized Input litude AM-AM linearity Frequency (MHz) Output spectra, fc = 64 MHz

20 Summary and conclusions 2 All-digital PWM with improved dynamic range, combining PWM, outphasing, and switch-mode PAs, has been presented. litude: digital PWM. Phase: digital PPM of carrier frequency + quant error. Two PAs => needs combiner (space, losses). Measurement results, 2 MHz LTE uplink: 6.3 dbc improved ACLR compared to D-PWM. No aliasing or image distortion => improved EVM. Somewhat reduced efficiency (-2 %, combiner)

21 Thanks for your attention! Questions?