Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and

Transcription

1 CMOS Sigma-Delta Converters From Basics to State-of-the-Art Circuits and Errors Angel Rodríguez-Vázquez Barcelona, / Septiembre / 2010 Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and Angel Rodríguez-Vázquez 1

2 CT- Ms : Overview of CT- M non-idealities CT- M Non-Idealities Building-block Errors Architectural Timing Errors Opamp finite (non-linear) DC gain Integrator transient response Element tolerances Time-constant error Non-linearity (Front-end V-I and DAC) Noise Quantizer metastability Excess loop delay Clock jitter 2

3 CT- Ms : Basic building blocks Basic building blocks CT Integrators A Gm-MC implementation - 2nd-order single-loop M - 1-bit switched-current DAC - 1-bit (latch) comparator 3

4 CT- Ms : Non-ideal integrator transfer function Integrator Transfer Function (ITF) degraded by circuit non-idealities 4

5 CT- Ms : Effect of finite DC gain error Opamp p finite DC gain (I) RC integrators [Gerf03] - Same IBN degradation as in SC Ms 5

6 CT- Ms : Effect of finite DC gain error Opamp finite DC gain (II) Gm-C integrators Power Spectral Density of an Lth-order M Relative increase of P Q in a 2nd-order M 6

7 CT- Ms : Integrator transient response Integrator transient response se (I) Less critical than in DT Ms Need to be taken into account, specially in broadband applications Influence of GBW [Gerf03] 3rd-order single-loop loop RC CT- M Other dynamic effects 2nd-order poles Slew-rate Complex analysis Simulation-based study [Ruiz03] 7

8 CT- Ms : Integrator transient response Model of GBW for RC-active based CT- Ms [Ortm04] Modeled as a gain error (GE) and extra loop delay Each delay is different for each feeback path 8

9 CT- Ms : Circuit element tolerances Element tolerances Scaling coefficients accuracy limited by random errors in resistors/capacitors Especially critical in: High-order single-loop architectures (instability) Cascade architectures (analog/digital coefficient ratios) Two types of random errors: Absolute tolerances: variations from chip to chip (10-20%) Relative mismatches: variations from device to device on one chip (0.5-1%) Electrical control of frequency tuning System-level l optimization i and synthesis method gm (%) c (%) 0 9

10 CT- Ms : Circuit element tolerances Direct synthesis method of CT cascade architectures [Tort06]: Optimum placement of poles/zeroes of the NTF Synthesis of both analog and digital part of the cascade CT Modulator Reduced number number of analog components Reduced sensitivity to element tolerances DT-to-CT Method Direct Method 10

11 CT- Ms : Circuit element tolerances Direct synthesis of cascade architectures (I) [Tort06] Sensitivity to mismatch (gm,c) A2-1-1 example SNR Lo oss (db) gm (%) c (%) gm (%) c (%) c 0 DT-to-CT synthesis method Direct synthesis method 11

12 CT- Ms : Circuit element tolerances Direct synthesis of cascade architectures (II) [Tort06] 12

13 CT- Ms : Circuit element tolerances Synthesized cascaded CT SDMs to cope with 12-bit@20-MHz CT M CT M 3-2 CT M 13

14 CT- Ms : Synthesis methods Acasestudy:A12-bit@20MHz study: A bit@20mhz, 4-b, CT M (RC/Gm Integrators) 14

15 CT- Ms : Integrator time-constant error Integrator time-constant error (I) 15

16 CT- Ms : Integrator time-constant error Integrator time-constant error (II) Optimum SNR for: 16

17 CT- Ms : Non-linear errors Causes of Non-linearity Intrinsic non-linearity of the resistor material Modulation of thickness of the conductive layer with resistor voltage V-I transformation in RC integrators V-I transformation in Gm-C integrators 17

18 CT- Ms : Non-linear errors Effect on Non-linearity in Gm-C CT- Ms [Bree01] Linearization strategies 18

19 CT- Ms : Nonlinearities and noise Typical Nonlinear-Tolerant Architecture RC-active front-end integrator Gm-C subsequent integrators Other sources of non-linearity Multi-bit DACs Linearity must be the same or lower than the required resolution Corrected by same techniques as those employed in SC Ms DEM Calibration Circuit noise Dominated by noise sources from the front-end integrator and DAC Flicker noise reduced by proper sizing and/or chopper techniques Unsampled noise effect of sampling reduced by the loop gain 19

20 CT- Ms : Comparator metastability Signal-dependent Delay Can be cancelled by using additiona latches [Dagh04] Modeled as a jitter noise [Cher00] 20

21 CT- Ms : Excess loop delay DAC transient t response delay Adds additional poles to STF/NTF Causes instability Stability condition: 2nd-order Lth-order 21

22 CT- Ms : Excess loop delay Raising Instability 22

23 CT- Ms : Excess loop delay Cancellation Extra feedback paths (DACs) with tunable gains [Cher00] Using only one additional DAC and two latches [Yan04] Y(n) (without DAC_B and latches) Edge trigered DAC_B output Level trigered Y(n) 23

24 CT- Ms : Excess loop delay Compensation Digital compensation [Font05] Implemented in a 3rd-order single loop architecture with 5-level quantizer 90nm CMOS 74-dB SNDR-peak, 600kHz bandwidth 6.0mW, 1.5V Excess loop delay compensated in the digital domain Half-a-clock-cycle delay Relax comparators speed Provide maximum isolation between quantizer and DAC switch events 24

25 CT- Ms : Clock jitter error Clock jitter (I) S/H Shaped by the modulator NTF Can be neglected DAC Directly adds with the input Increases the in-band noise power DT DAC waveform CT DAC waveform CT Ms M are more sensitive to clock jitter than DT Ms White noise model approximation (NRZ DAC) [Cher00][Zwan96] Standard deviation of jitter error: SNR degradation: 25

26 CT- Ms : Clock jitter error Clock Jitter (II) White noise model approximation (NRZ/RZ DAC) [Tao99a] Lowpass CT- Ms Bandpass CT- Ms 26

27 CT- Ms : Clock jitter error Clock Jitter (III) lingering effect [Olia03a] Jitter-induced noise includes both white and shaped components State-space analysis of CT- Ms with RZ DAC shows that: Multi-bit NRZ DACs Commonly used in CT- Ms for brodband telecom applications Less sensitive to clock jitter RZ DAC NRZ DAC 27

28 CT- Ms : Clock jitter error Clock Jitter (IV) Multi-bit NRZ DACs [Tort05] [Ris94] - Using state-space formulation of NTF: 28

29 CT- Ms : Clock jitter error Clock Jitter (V): Comparison of [Tort05] with previous approaches This work Assuming that SNR jitter is dominated by the signal-dependent term: [Zwan96] 2nd d-order r single e-bit [Hern04] [Bose88] [Boser, JSSC, 1988] If the modulator-dependentdependent term dominates (single-bit quantization): [Van der Zwan, JSSC, 1996] 29

30 CT- Ms : Clock jitter error Clock Jitter (V) Multi-bit NRZ DACs [Tort05] Two cases: - CT M1: B=2bit, f s =400MHz -CT M2: B=5bit, f s =160MHz CT M1 CT M2 30

31 CT- Ms : Clock jitter error Clock Coc Jitter (VI) Compensation o techniques Multi-bit quantization (non-linear DAC) Switched-capacitor DAC [Veld03] Voltage-mode operation (proper p for active RC integrators) Slower than switched-current (current steering) DAC FIRDAC to generate a multilevel signal [Putt04] 31

32 CT- Ms : Case studies A case study: A Gm-C 12-bit@20MHz, 4-b, 3-2 CT M 130nm mixed-signal CMOS, 1P8M Cascade 3-2 multi-bit (4b) CT M Gm-C loop-filter implementation Current-steering feedback DACs + DEM 12-bit effective resolution 40MS/s output rate (20MHz bandwidth) 240MHz clock frequency 1.2V ± 10% analog/digital power supply On-chip tuning of analog components Estimated power consumption is 45mW Loop-filter coefficients Building-block specifications 32

33 CT- Ms : Case studies Transconductors o s Resistive source degenerated front-end transconductor Loop-filter transconductors based on quadratic term cancellation Transistor-level performance 33

34 CT- Ms : Case studies Current-steering DACs A P-type gain-boosted current sources 15 N-type regulated-cascode current cells Worst-Case Transistor-level performance 34

35 CT- Ms : Case studies Chip implementation Front-End Transconductors M-i-M Capacitors DAC1s Transimpedance s Clock Latches &DEM DAC2s Loop-Filter Transconductors Quantizers 35

36 CT- Ms : Case studies Transistor-level simulation results SNDR = 75.3 db ( MHz bandwidth 36

37 CT- Ms : Case studies A case study: A 1.2-V 13-bit@20MHz, 4-b, CT M E 1 x(s) CT M 1 E 2 CT M 2 y 1 (z) CL1 y 2 (z) CL2 x(s) DAC y(z) DT-to-CT E m Direct Synthesis CT M 1 y m (z) CLm x(s) k 1 1 k 3 1 st k 2 k 4 st DAC x(s) CL 1 k 1 1 k 3 1 st st k 2 k 4 DAC CL 1 k 5 k 6 k 7 k 9 k 10 1 st CL 2 k 8 k 11 k 12 k 13 k 14 1 st DAC DAC CL 3 k 5 k 6 1 st k 7 1 st k 8 DAC DAC CL 2 CL 3 37

38 CT- Ms : Case studies Jitter optimization Input-dependent Term Filter-dependent Term 38

39 CT- Ms : Case studies Modulator Simplified feedforward paths RC-Amp Integrator High linearity Virtual ground High Power GBW dependent delay 4b Quantizers NRZ scheme Low jitter sensitivity Optimized combination of number of bits, fs, and signal bandwidth Gm Cells Tunable Reasonble Linearity High frequency Operation Multiple of a Unitary Transconductor Low Output Impedance Optimum Cancellation Logic Sinthesized taking into acount inter-stage continuous-time time integrating paths 39

40 CT- Ms : Case studies Pibias1 CMFB Pibias1 Input OpAmp Pbias1 Out+ Vin+ Vin- Out- Amplifier Characteristics Pbias2 GB 600MHz DC Gain 71dB Pbias1 Phase Margin 80º Out- Vin+ Vin- Out+ Parasitic Input Capacitance 0.36pF Parasitic Output Capacitance 0.4pF Differential Output Swing 0.7V CMFB Nbias2 Power Consumption 20mW 40

41 CT- Ms : Case studies Unitary Transconductor Vff Pbias3 Pbias3 Vff Pbias4 Pbias4 Vref Vref Cff Vin+ Vin+ Cff Iout- Itune Iout+ Nbias3 Nbias3 CMFB CMFB Vff Itune Transcoductor Characteristics DC Gain 58dB Diff. Input Amp. 0.3V Diff. Output Amp. 0.3V HD3-57dB gm /g m <1.5% 15% Power 350 W 41

42 CT- Ms : Case studies Simulation Results SNDR Power 80dB 65mW 85 Magnitude (db B) 0 Minimum SNDR -20 due to mismatch Signa Bandwidth Jitter requirements Sampling Frequency 77dB 20MHz <5ps 240MHz Frequency (Hz) 90% SNR gm (%) c (%) 1 42

43 CT- Ms : References [Bree00] [Bree01] L.J. Breems, E.J. Van der Zwan and J. Huijsing, A 1.8-mW CMOS SD Modulator with Integrated Mixer for A/D Conversion of IF Signals. IEEE Journal of Solid-State Circuits, Vol. 35, pp , April L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, [Cher00] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, [Font05] [Gerf03] [Olia03a] [Olia03b] [Ortm01] [Ortm04] P. Fontaine, A. N. Mohieldin and A. Bellaourar, A Low-Noise Low-Voltage CT DS Modulator with Digital Compensation of Excess Loop Delay. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp , F. Gerfers, M. Ortmanns and Y. Manoli, A 1.5-V 12-bit Power-Efficient Continuous-Time Third-Order SD Modulator. IEEE Journal of Solid-State Circuits, Vol. 38, pp , August O. Olieai, State-Space Analysis of Clock Jitter in Continuous-Time Oversampling Data Converters. IEEE Transactions on Circuits and Systems I, Vol. 50, pp , 37 January O. Olieai, Design of Continuous-Time Sigma-Delta Modulators With Arbitrary Feedback Waveform. IEEE Transactions on Circuits and Systems II, Vol. 50, pp , August M. Ortmanns, F. Gerfers, and Y. Manoli, On the synthesis of cascaded continuous-time Sigma-Delta modulators. Proc. of the 2001 IEEE Int. Symp. on Circuitsit and Systems, Vol. 5, pp , 422 May M. Ortmanns, F. Gerfers and Y. Manoli, Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 51, pp , June [Ortm05] M. Ot Ortmanns, F. Gerfers and Y. Manoli: A Case Study on Cascaded d Continuous-Time Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 52, pp , August

44 CT- Ms : References [Tao99a] H. Tao, L. Toth and M. Khoury, Analysis of Timing Jitter in Bandpass Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 46, pp , August [Tao99b] H. Tao and J.M. Khoury, A 400MS/s Frequency Translating BandPass Delta-Sigma Modulator. IEEE Journal of Solid-State Circuits, Vol. 34, pp , December [Tort05] R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández, Analysis of Clock Jitter Error in Multibit Continuous-Time SD Modulators with NRZ Feedback Waveform. Proc. Of the 2005 Int. Symposium on Circuits and Systems (ISCAS), May [Tort06] [Tort07] R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma-Delta modulators. IEEE Trans. On Circuits and Systems II: Express Briefs, pp , August R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: A 12-bit@40Ms/s Gm- C Cascade 3-2 Continuous-Time Sigma-Delta Modulator. Proc. Of the 2007 Int. Symposium on Circuits and Systems (ISCAS), May [Yan04] S. Yan and E. Sánchez-Sinencio, A Continuous-Time SD Modulator With 88-dB Dynamic Range and 1.1- MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, pp , January