Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847

Transcription

1 ; Rev 0; 7/93 General Description The are dual, 12-bit, multiplying, voltage-output digital-to-analog converters (DCs). Each DC has an output amplifier and a feedback resistor. The output amplifier is capable of developing 0V across a 2kΩ load. The amplifier feedback resistor is internally connected to V OUT on the MX7847. No external trims are required to achieve full 12-bit performance over the entire operating temperature range. The MX7847 has a 12-bit parallel data input, whereas the MX7837 operates with a double-buffered 8-bit-bus interface that loads data in two write operations. ll logic signals are level triggered and are TTL and CMOS compatible. Fast timing specifications make these DCs compatible with most microprocessors. pplications Small Component-Count nalog Systems Digital Offset/Gain djustments Industrial Process Control Function Generators utomatic Test Equipment utomatic Calibration Machine and Motion Control Systems Waveform Reconstruction Synchro pplications Pin Configurations TOP VIEW CS R FB V OUT DB0/DB8 DB1/DB9 DB2/DB10 DB3/DB11 GND 5 20 DB4 MX DB5 GNDB V OUTB DB6 DB7 0 V REFB 10 DGND 11 R FBB LDC Complete, Dual, 12-Bit Features Two 12-Bit with Buffered Voltage Output Specified with 2V or 5V Supplies No External djustments Required Fast Timing Specifications 24-Pin DIP and SO Packages 12-Bit Parallel Interface (MX7847) 8-Bit + 4-Bit Interface (MX7837) Ordering Information Ordering Information continued on last page. * Contact factory for availability and processing to MIL-STD-883. V REFB PRT TEMP. RNGE PIN-PCKGE MX7837JN 0 C to +70 C 24 Narrow Plastic DIP MX7837KN 0 C to +70 C 24 Narrow Plastic DIP MX7837JR 0 C to +70 C 24 Wide SO MX7837KR 0 C to +70 C 24 Wide SO MX7837C/D 0 C to +70 C Dice* Typical Operating Circuits DB0 DB7 LDC CS 0 CONTROL LOGIC MSB LSB INPUT INPUT LTCH LTCH 4 8 DC LTCH 12 DC DC B 12 DC LTCH B 4 8 MSB LSB INPUT INPUT LTCH LTCH MX7837 ERROR (LSB) /2 /2 R FB V OUT GND R FBB V OUTB GNDB MX7847 on last page. DIP/SO DGND MX7847 on last page. Maxim Integrated Products 1 Call toll free for free samples or literature.

2 BSOLUTE MXIMUM RTINGS to DGND, GND, GNDB V to +17V to DGND, GND, GNDB (Note 1) V to -17V, V REFB to GND, GNDB.. ( - 0.3V) to ( + 0.3V) GND, GNDB to DGND V to ( + 0.3V) V OUT, V OUTB to GND, GNDB...( - 0.3V) to ( + 0.3V) R FB, R FBB to GND, GNDB...( - 0.3V) to ( + 0.3V) Digital Inputs to DGND V to ( + 0.3V) Continuous Power Dissipation (T = +70 C) Narrow Plastic DIP (derate 13.33mW/ C above +70 C) mW SO (derate 11.76mW/ C above +70 C)...941mW Narrow CERDIP (derate 12.50mW/ C above +70 C)..1000mW ELECTRICL CHRCTERISTICS Operating Temperature Ranges: MX78_7J_/K_...0 C to +70 C MX78_7_/B_ C to +85 C MX78_7SQ/TQ C to +125 C Storage Temperature Range C to +150 C Lead Temperature (soldering, 10sec) C Note 1: If is open-circuited with and either GND applied, the pin will float positive exceeding the bsolute Maximum Ratings. If this possibility exists, a Schottky diode connected between and GND ensures the maximum ratings will be observed. Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( = 11.4V to 16.5V, = -11.4V to -16.5V, GND = GNDB = DGND = 0V, = V REFB = +10V, R L = 2kΩ, C L = 100pF, V OUT connected to R FB (MX7837), T = T MIN to T MX, unless otherwise noted.) (Note 2) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS STTIC PERFORMNCE (Note 3) Resolution N 12 Bits Relative ccuracy INL MX78_7J//S MX78_7K/B/T /2 LSB Differential Nonlinearity DNL Guaranteed monotonic LSB T = +25 C ±2 Zero-Code Offset Error Loaded with all 0s, MX78_7J/ ±4 tempco = ±5µV/ C typ T = T MIN to T MX MX78_7K/B ±3 mv MX78_7S/T ±5 Gain Error MX78_7J//S ±5 T = +25 C Loaded with all 1s, MX78_7K/B/T ±2 tempco = ±2ppm of FSR/ C typ MX78_7J//S ±7 T = T MIN to T MX MX78_7K/B/T ±4 LSB REFERENCE INPUTS V REF Input Resistance kω, V REFB Resistance Matching ±0.5 ±3 % DIGITL INPUTS Input High Voltage V INH 2.4 Input Low Voltage V INL 0.8 V Input Current Digital inputs at 0V and µ Input Capacitance (Note 4) 8 pf NLOG OUTPUTS DC Output Impedance 0.2 Ω Short-Circuit Current V OUT connected to GND 15 m 2

3 ELECTRICL CHRCTERISTICS (continued) ( = 11.4V to 16.5V, = -11.4V to -16.5V, GND = GNDB = DGND = 0V, = V REFB = +10V, R L = 2kΩ, C L = 100pF, V OUT connected to R FB (MX7837), T = T MIN to T MX, unless otherwise noted.) (Note 1) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS POWER REQUIREMENTS Range V Range V Positive Supply Current I DD Output unloaded 5 10 m Negative Supply Current I SS Output unloaded 4 6 m Gain/ = 15V ±5%, V REF = -10V ±0.01 Power-Supply Rejection Gain/ = -15V ±5%, V REF = 10V ±0.01 Gain/ = 12V ±5%, V REF = -8.9V ±0.01 % per % Gain/ = -12V ±5%, V REF = 8.9V ±0.01 C CHRCTERISTICS Voltage-Output Settling Time t S Settling time to within /2LSB of final DC value; DC latch alternately loaded will all 0s and all 1s 4 µs Slew Rate 7 V/µs Digital-to nalog Glitch Impulse Channel-to-Channel Isolation ( to V OUTB, V REFB to V OUT ) Multiplying Feedthrough Error Unity-Gain Small-Signal Bandwidth Q DC latch alternately loaded with and V REF = 20p-p, 10kHz sine wave, lternate DC Latch Loaded with all 0s 60 nv-s -95 db V REF_ = 20V p-p, 10kHz sine wave, latches loaded with all 0s -90 db V REF = 100mV p-p sine wave, DC latch loaded with all 1s 1 MHz Full-Power Bandwidth V REF = 20V p-p Sine wave, DC latch loaded with all 1s 125 khz Total Harmonic Distortion THD V REF = 6V RMS, 1kHz, DC latch loaded with all 1s -88 db Digital Crosstalk Code transition from all 0s to all 1s; see Typical Operating Characteristics graphs 10 nv-s Output Noise Voltage at +25 C (0.1Hz to 10Hz) mplifier noise and Johnson noise of R FB 2 µv RMS Note 2: Note 3: Note 4: The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, and V REFB must be at least 2.5V lower than and. Tests done with supply voltages below 2.5V are done with = V REFB = ±8.9V. Static performance tested at = +15V, = -15V. Performance over supplies guaranteed by PSRR test. Guaranteed by design. 3

4 TIMING CHRCTERISTICS ( = 11.4V to 16.5V, = -11.4V to -16.5V, GND = GNDB = DGND = 0V, T = T MIN to T MX, unless otherwise noted.) (Note 5) PRMETER SYMBOL CONDITIONS MX78_7J/K//B MIN MX MX78_7S/T MIN MX CS to Setup Time t ns CS to Hold Time t ns Pulse Width t ns Data to Setup Time t ns Data to Hold Time t ns ddress to SetupTime t 6 MX7837 only ns ddress to Hold Time t 7 MX7837 only ns LDC Pulse Width t 8 MX7837 only ns Note 5: ll input signals are specified with t R = t F 5ns. Logic swing is 0V to 5V. UNITS Typical Operating Characteristics (T = +25 C, = 15V, = -15V, R L = 2kΩ, C L = 100pF, unless otherwise noted) V OUT (V p-p ) OUTPUT VOLTGE SWING vs. RESISTIVE LOD V REF = 20V p-p at 1kHz NOISE SPECTRL DENSITY (nv/ Hz) NOISE SPECTRL DENSITY V REF = 0V DC CODE = GIN = -1 GIN (db) SMLL-SIGNL FREQUENCY RESPONSE V REF = 100mV p-p DC CODE = GIN = k 10k LOD RESISTNCE (Ω) k 10k 100k FREQUENCY (Hz) k 10k 100k 1M 10M FREQUENCY (Hz) TTENUTION (db) MULTIPLYING FEEDTHROUGH ERROR = 20V p-p V REFB = GNDB DC CODE = THD (db) TOTL HRMONIC DISTORTION + NOISE vs. FREQUENCY (BNDWIDTH = 80kHz) V REF = 6V RMS DC CODE = THD (db) TOTL HRMONIC DISTORTION + NOISE vs. FREQUENCY (BNDWIDTH > 500kHz) V REF = 6V RMS DC CODE = k 10k 100k 1M FREQUENCY (Hz) k 10k FREQUENCY (Hz) k 10k 100k FREQUENCY (Hz) 4

5 Typical Operating Characteristics (continued) (T = +25 C, = 15V, = -15V, R L = 2kΩ, C L = 100pF, unless otherwise noted.) GND SMLL-SIGNL PULSE RESPONSE GND LRGE-SIGNL PULSE RESPONSE = V OUT, 50mV/div TIMEBSE = 2µs/div = 00mV SQURE WVE = V OUT, 5V/div TIMEBSE = 2µs/div = 0V SQURE WVE Pin Description PIN MX7837 MX7847 NME FUNCTION 1 CS Chip Select active-low logic input 1 CS Chip-Select Input for DC active-low logic input 2 R FB mplifier Feedback Resistor for DC 2 CSB Chip-Select Input for DC B active-low logic input 3 3 Reference Input Voltage for DC 4 4 V OUT nalog Output Voltage from DC 5 5 GND nalog Ground for DC 6 6 Positive Power Supply 7 7 Negative Power Supply 8 8 GNDB nalog Ground for DC B 9 9 V OUTB nalog Output Voltage from DC B V REFB Reference Input Voltage for DC B DGND Digital Ground 12 R FBB mplifier Feedback Resistor for DC B 12 DB11 Data Bit 11 (MSB) Write Input active-low logic input (MX7837); positive-edge-triggered input used with CS and CSB (MX7847) 14 LDC synchronous Load DC input, active-low DB10-DB0 Data Bit 10 to Data Bit 0 (LSB) 15 ddress Input most significant address input for input latches 16 0 ddress Input least significant address input for input latches DB7-DB4 Data Bit 7 to Data Bit DB3/DB11- DB0/DB8 Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8 5

6 V REF R R R 2R 2R 2R 2R 2R 2R 2R C B S9 S8 S0 SHOWN FOR LL 1s ON DC Figure 1. D/ Simplified Circuit Diagram Detailed Description D/ Section Figure 1 shows a simplified circuit diagram for one of the DCs and the output amplifier. Using a segmented scheme, the two MSBs of the 12-bit data word are decoded to drive the three switches ( to C). The remaining 10 bits drive the switches (S0 to S9) in a standard R-2R ladder. Each switch ( to C) directs 1/4 of the total reference current, and the remaining current passes through the R-2R section. The output amplifier and feedback resistor convert current to voltage as follows: V OUT_ = (-D)(V REF_ ), where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The output amplifier is capable of developing 0V across a 2kΩ load. It is internally compensated and settles to 0.01% FSR (1/2LSB) in less than 4µs. V OUT on the MX7837 is not internally connected to R FB. R/ 2 GND V OUT Interface Logic Information (MX7847) Figure 2 shows the MX7847 input control logic. The device contains two independent DCs, each with its own CS input and a common input. CS and control data loading to the DC latch, and CSB and control data loading to the DC B latch. The latches are edge triggered so that input data is latched to the respective latch on 's rising edge. The same data will be latched to both DCs if CS and CSB are low and is taken high. Table 1 shows the device control-logic truth table, and Figure 3 shows the writecycle timing diagram. Table 1. MX7847 Truth Table CS CSB Function X X 1 No Data Transfer 1 1 X No Data Transfer 0 1 Data Latched to DC 1 0 Data Latched to DC B 0 0 Data Latched to Both DCs 1 0 Data Latched to DC 1 0 Data Latched to DC B 0 Data Latched to Both DCs X = Don't Care = Rising Edge Triggered Interface Logic Information (MX7837) The MX7837 input loading structure is configured for interfacing with 8-bit-wide data-bus microprocessors. Each DC has two 12-bit latches: an input latch, and a DC latch. Each input latch is subdivided into a leastsignificant 8-bit latch and a most-significant 4-bit latch. The data held in the DC latches determines the outputs. Figure 4 shows the MX7837 input control logic, and Figure 5 shows the write-cycle timing diagram. CS DC LTCH CS, CSB t 1 t 3 t 2 CSB DC B LTCH t4 t 5 DT VLID DT Figure 2. MX7847 Input Control Logic Figure 3. MX7847 Write-Cycle Timing Diagram 6

7 LDC CS 0 CS,, 0, and control data loading to the input latches. The eight data inputs accept right-justified data, which can be loaded to the input latches in any sequence. If LDC is held high, loading data to the input latches will not change the analog output. 0 and determine which input latch will receive the data when CS and are low. Table 2 shows the control logic truth table. Table 2. MX7837 Truth Table CS 0 LDC Function 1 X X X 1 No Data Transfer X 1 X X 1 No Data Transfer DC LS Input Latch Transparent DC MS Input Latch Transparent DC B LS Input Latch Transparent DC B MS Input Latch Transparent 1 1 X X 0 Updated Simultaneously from the Respective Input Latches X = Don't Care DC LTCH 4 DC MS INPUT LTCH Figure 4. MX7837 Input Control Logic 8 DC LS INPUT LTCH DC B LTCH DC B MS INPUT LTCH DC B LS INPUT LTCH The LDC input controls 12-bit data transfer from the input latches to the DC latches. When LDC is taken low, both DC latches (thus, both analog outputs) are updated simultaneously. When LDC is low, the DC latches are transparent; DC data is latched on the rising edge of LDC. The LDC input is asynchronous 8 4 DB7 DB0 8 0/ CS DT LDC DDRESS VLID t 6 t 7 t 1 t 3 t 2 VLID DT Figure 5. MX7837 Write-Cycle Timing Diagram and independent of. This is useful in many applications, especially in updating multiple MX7837s simultaneously. However, be careful when exercising LDC during a write cycle; if an LDC operation overlaps a CS and operation, invalid data may be latched to the output. To avoid this, LDC must remain low after CS or have returned high for a period equal to or greater than t 8, the minimum LDC pulse width. Unipolar Binary Operation Figure 6 shows DC () connected for unipolar binary operation. Similar connections apply for DC B. When V IN is an C signal, the circuit performs 2-quadrant multiplication. Table 3 shows the code table for this circuit. On the MX7847, the R FB feedback resistor is internally connected to V OUT. Table 3. Unipolar Code Table DC Latch Contents nalog Output, V MSB LSB OUT Note : 1LSB VIN = 4096 t 4 t V IN V 2048 = 1 IN 2 V IN V IN V t 8 7

8 Bipolar Operation (4-Quadrant Multiplication) Figure 7 shows the connected for binary operation. The offset-binary coding is shown in Table 4. When V IN is an C signal, the circuit performs 4-quadrant multiplication. R1, R2, and R3 resistors should be 0.01% ratio matched to maintain gain-error specifications. On the MX7847, the R FB feedback resistor is internally connected to V OUT. Table 4. Bipolar Code Table DC Latch Contents nalog Output, V MSB LSB OUT V IN V IN V V IN V IN 2048 = VIN pplications Information Ground Management The use of an uninterrupted ground plane is strongly recommended. C or transient voltages between analog and digital grounds (between GND/GNDB and DGND) can inject noise into the analog circuitry. Connect the GNDs and DGND directly to the ground plane or to a star ground to ensure that they are at the same potential. In complex systems with separate analog and digital ground planes, connect two diodes (1N914 or equivalent) in inverse parallel between the GND and DGND pins. Power-Supply Decoupling To minimize noise, decouple the and lines to DGND using a 10µF capacitor in parallel with a 0.1µF ceramic capacitor. Minimize capacitor lead lengths for best noise rejection. Operation with Reduced Power-Supply Voltages The are specified for operation with / = 1.4V to 6.5V. However, the output amplifier requires 2.5V of headroom, so the reference input should not come within 2.5V of / in order to maintain accuracy at full scale. Note : 1LSB VIN = 2048 R1 20k R2 20k V IN DC R FB * V OUT * V OUT V IN R FB * R3 10k MX427 V OUT DGND GND MX7837 MX7847 DC V OUT * INTERNLLY CONNECTED ON MX7847 DGND GND MX7837 MX7847 * INTERNLLY CONNECTED ON MX7847 Figure 6. Unipolar Binary Operation Figure 7. Bipolar Offset Binary Operation 8

9 Pin Configurations (continued) TOP VIEW CS CSB V OUT DB0 DB1 DB2 DB3 GND 5 20 DB4 MX DB5 GNDB V OUTB DB6 DB7 DB8 V REFB 10 DGND 11 DB DB9 DB10 DIP/SO Typical Operating Circuits (continued) Ordering Information (continued) PRT TEMP. RNGE PIN-PCKGE MX7837N -40 C to +85 C 24 Narrow Plastic DIP MX7837BN -40 C to +85 C 24 Narrow Plastic DIP MX7837R -40 C to +85 C 24 Wide SO MX7837BR -40 C to +85 C 24 Wide SO MX7837Q -40 C to +85 C 24 Narrow CERDIP ERROR (LSB) /2 /2 MX7837BQ -40 C to +85 C 24 Narrow CERDIP /2 MX7837SQ -55 C to +125 C 24 Narrow CERDIP MX7837TQ -55 C to +125 C 24 Narrow CERDIP /2 MX7847JN 0 C to +70 C 24 Narrow Plastic DIP MX7847KN 0 C to +70 C 24 Narrow Plastic DIP /2 MX7847JR 0 C to +70 C 24 Wide SO MX7847KR 0 C to +70 C 24 Wide SO /2 MX7847C/D 0 C to +70 C Dice* MX7847N -40 C to +85 C 24 Narrow Plastic DIP MX7847BN -40 C to +85 C 24 Narrow Plastic DIP /2 MX7847R -40 C to +85 C 24 Wide SO MX7847BR -40 C to +85 C 24 Wide SO /2 MX7847Q -40 C to +85 C 24 Narrow CERDIP MX7847BQ -40 C to +85 C 24 Narrow CERDIP /2 MX7847SQ -55 C to +125 C 24 Narrow CERDIP MX7847TQ -55 C to +125 C 24 Narrow CERDIP /2 DC LTCH DC VOUT V REFB GND DB0 DB11 DC B V OUTB CS CSB CONTROL LOGIC DC LTCH B GNDB MX7847 DGND 9

10 Chip Topographies V OUT GND R FB CS MX7837 DB0/DB8 DB1/DB9 DB2/DB10 DB3/ DB11 DB4 DB " (6.35mm) V OUT GND CSB MX7847 CS DB0 DB1 DB2 DB3 DB4 DB " (6.35mm) GNDB DB6 DB7 GNDB DB6 DB7 V OUTB 0 V OUTB DB8 DB9 V REFB DGND R FBB LDC V REFB DGND DB11 DB " (3.56mm) 0.140" (3.56mm) TRNSISTOR COUNT: 1240; SUBSTRTE CONNECTED TO. TRNSISTOR COUNT: 1240; SUBSTRTE CONNECTED TO. 10

11 Package Information L 2 D1 e D B B1 3 α E E1 e e B DIM 2 3 B B1 C D D1 E E1 e e e B L α C MIN INCHES MX BSC BSC MILLIMETERS MIN MX BSC 7.62 BSC PIN PLSTIC DUL-IN-LINE (NRROW) PCKGE E H DIM B C D E e H h L α MIN INCHES MX BSC MILLIMETERS MIN MX BSC D h x 45 α e B 0.127mm 0.004in. C L 24-PIN PLSTIC SMLL-OUTLINE PCKGE 11

12 Package Information (continued) S1 D S E1 E DIM B B1 C D E E1 e L L1 Q S S1 α MIN INCHES MX BSC MILLIMETERS MIN MX BSC B L Q e B B1 L1 α C 24-PIN CERMIC DUL-IN-LINE (NRROW) PCKGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, C (408) Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products.