CONTROL OF STATIC SERIES COMPENSATOR MITIGATION OF POWER QUALITY PROBLEMS FOR THESIS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY HILMY AWAD

Transcription

1 THESIS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY CONTROL OF STATIC SERIES COMPENSATOR FOR MITIGATION OF POWER QUALITY PROBLEMS by HILMY AWAD Department of Electric Power Engineering CHALMERS UNIVERSITY OF TECHNOLOGY Göteborg, Sweden 24

2 Control of Static Series Compensator for Mitigation of Power Qality Problems HILMY AWAD ISBN HILMY AWAD, 24 All rights reserved Doktorsavhandlingar vid Chalmers Tekniska Högskola Ny serie nr 288 ISSN X School of Electrical Engineering Chalmers University of Technology Technical Report No. 475 CHALMERS UNIVERSITY OF TECHNOLOGY Department of Electric Power Engineering S Gothenbrg, Sweden Telephone: +46 () Fax: +46 () Chalmers Bibliotek, Reproservice Göteborg, Sweden 24

3 ABSTRACT Power Electronics and Advanced Control technologies have made it possible to mitigate power qality problems and maintain the operation of sensitive loads. Among power system distrbances, voltage dips, swells, and harmonics are some of the severe problems to the critical indstrial loads. The static series compensator (SSC) is best sited to protect sch loads against those distrbances. This thesis focses on the control of the SSC in order to improve the transient and the steady-state responses and increase its injection capability. To mitigate voltage dips, the thesis proposes a vector-controlled based algorithm to improve the transient and the steady-state responses of the SSC. The developed algorithm incorporates both crrent and voltage controllers with an inner crrent loop and oter voltage loop. Ths, it is referred to as the Doble Vector Control (DVC) algorithm. To cope with nbalanced dips, a fast techniqe to detect the positive and the negative seqences is employed. Then the two seqences are controlled separately. Also the inflence of the switching freqency on the controller performance is stdied. A Software Phase Locked Loop with a PI controller is proposed in order to obtain the phase and the freqency information of the grid voltage. The tning of the PI controller is made according to a developed criterion based on the freqency reqirements of the loads. A nmber of power system events are stdied and the behavior of the SSC is tested against each event. These events inclde short-circit falts, capacitor-bank energizing, transformer energizing and load switching (linear and non-linear loads). Recommendations regarding the SSC operation for each event are given. The possibility of employing the SSC to mitigate voltage swells and overvoltages is investigated. An overvoltage protection scheme is proposed, based on a combination of a dc resistor with a chopper and the SSC. The design eqations of the dc resistor together with the chopper are provided. In order to mitigate voltage harmonics, a new controller is developed and implemented. In the proposed controller, a moving average filter is implemented in the synchronos reference frame to extract the fndamental component of the measred voltages and crrents. Also, an active filtering capability is added by sing the resonant filters for the 5 th and the 7 th harmonics. After the extraction of the fndamental component, it is controlled by the DVC. The operation of the SSC nder distorted tility conditions and voltage dips is discssed. The thesis also proposes two control techniqes to charge the energy storage capacitor of the SSC. One of the techniqes is based on a shnt diode rectifier, which is placed either on the load side or the grid side (both configrations are stdied). The other techniqe exploits the voltage sorce converter of the SSC in combination with a proper control algorithm to charge the capacitor. A design gide for the energy storage capacitor is given. III

4 To minimize the reqired active power, this thesis discsses and compares for different compensation strategies: 1) Voltage Difference Compensation; 2) In-Phase Compensation; 3) Phase Advance Compensation; 4) Progressive Phase Advance Compensation. The effect of the load power factor on the different strategies is investigated. A control algorithm based on a combination of the for strategies is proposed taking into accont the minimization of the active power and keeping the injected voltage within the ratings of the SSC. The validity of the developed controllers is verified by simlations and experiments. The simlation models are developed and implemented in the PSCAD/EMTDC package. A 1 kv SCC prototype is exploited to carry ot the experiments with varios load types. KEYWORDS: Cstom Power, Dynamic Voltage Restorer, Energy Storage, Power Electronics, Power Qality, Static Series Compensator, Vector Control, Voltage Dips, Voltage Swells, Voltage Harmonics. IV

5 PREFACE This work has been done at the Department of Electric Power Engineering, Chalmers University of Technology, Gothenbrg, Sweden. The project is fnded by ABB Power Systems, Elforsk and Energimyndigheten nder the Elektra program. I am obliged to express my gratitde to those withot whom my work wold have been mch more difficlt, or even impossible, to accomplish. I wold like to thank professor Jaap Daalder for being my examiner. Thanks to professor Math Bollen and Dr. Jan Svensson for their gidance, spport and encoragement. Thanks go to Dr. Ambra Sannino who has helped and spported me also. I have learnt a lot from them. I wold like to thank Prof. Essam Hamdi for being willing to help. My acknowledgements also go to all present members of the department for their help and providing a good working environment. Thanks go to Per Halvarsson and Dr. Tomas Larsson, the steering committee of the research project, for their beneficial inpts and consideration. Ulf Grape and Bengt-Rne Wallstrom are also members of the steering grop, thanks to them. The experimental work involved in this thesis was carried ot at the Institte of Energy Technology, Aalborg University, Denmark. Dring my work there, many colleages have contribted to perform the experimental work sccessflly. Particlarly, Professor Frede Blaabjerg has spervised me and provided all the facilities. Mr. Hans Nilsen and Mrs. Birthe Johansson have also helped me. Thanks to them and to all the staff at Aalborg University who have been involved with my work there. Special thanks go to my roommate Lcian Asiminoaei. I wold like to express my apologies to those whom I may have inadvertently failed to mention. Last, bt certainly not least, they are my mother, father, my great wife Hanaa and my snshine Maryam and Amina who I am highly indebted to. Their endrance, encoragement and continos spport made it possible to finish this thesis. V

6

7 LIST OF PUBLICATIONS PUBLISHED PAPERS [1] H. Awad, F. Blaabjerg, Transient performance improvement of static series compensator by doble vector control, in Proc. of IEEE Applied Power Electronics Conference, APEC, Febrary, 24, California, USA. [2] H. Awad, J. Svensson, M.H.J. Bollen, Phase-locked loop for static series compensator, in Proc. of Eropean Power Electronics Conference, EPE 23, Tolose, France, Sep. 23. [3] H. Awad, J. Svensson, M.H.J. Bollen, Static series compensator for voltage dips mitigation, in Proc. of the IEEE PowerTech Conference, 23, Bologna, Italy. [4] H. Awad, J. Svensson, M.H.J. Bollen, Testing static series compensator against capacitor bank energizing, in Proc. of the IEEE PowerTech Conference, 23, Bologna, Italy. [5] H. Awad, M.H.J. Bollen, Power electronics for power qality improvements, in Proc. of IEEE International Symposim on Indstrial Electronics, ISIE 23, Jne 9-12, 23, vol. 2, pp [6] H. Awad, J. Svensson, Compensation of nbalanced voltage dips sing vectorcontrolled static series compensator with LC-filter, in Proc. of the Indstry Applications Conference, th IAS Annal Meeting, vol. 2, pp [7] H. Awad, J. Svensson, Charging techniqes of dc capacitor for static series compensator, in Proc. of the IEEE International Symposim on Indstrial Electronics, ISIE 22, University of L Aqila, Italy, Jly 8-11, vol. 3, pp [8] H. Awad, J. Svensson, Self-startp of static series compensator, in Proc. of the IEEE International Symposim on Indstrial Electronics, ISIE 22, University of L Aqila, Italy, Jly 8-11, vol. 4, pp [9] H. Awad, J. Svensson, Doble vector control for series connected voltage sorce converters, in Proc. of the IEEE Power Engineering Society Winter Meeting 22, New York, USA, vol. 2, pp ACCEPTED PAPERS-AWAITING PUBLICATION [1] H. Awad, J. Svensson, M.H.J. Bollen, Mitigation of nbalanced voltage dips sing static series compensator, IEEE Trans. on Power Electronics, accepted. [11] H. Awad, J. Svensson, M.H.J. Bollen, Energy flow control between static series compensator and distribtion systems, Jornal of Circits, Systems, and Compters, Special Jbilee Isse: POWER ELECTRONICS CIRCUITS, accepted. [12] H. Awad, J. Svensson, M.H.J. Bollen, Tning software phase-locked loop for static series compensator, IEEE Trans. on Power Delivery, accepted. VII

8 [13] H. Awad, M.H.J. Bollen, Energy optimization control techniqes by static series compensator for constant power factor loads, in Proc. of the IEEE Power Engineering Society General Meeting, PES GM 24, accepted. [14] H. Awad, F. Blaabjerg, Mitigation of voltage swells by static series compensator, in Proc. of the IEEE Power Electronics Specialist Conference, PESC 24, accepted. [15] H. Awad, F. Blaaberg, Operation of static series compensator nder distorted tility conditions, IEEE Trans. on Power Systems, accepted. VIII

9 CONTENTS 1. INTRODUCTION BACKGROUND AND MOTIVATION CONTRIBUTIONS Modeling and Simlation of SSC Doble Vector Controller for Balanced Dips Mitigation of Unbalanced Dips Software Phase Locked Loop Control and Optimization of Energy Flow Startp of SSC Minimization of Active Power Reqirements Controller for Mitigation of Voltage Dips and Harmonics Mitigation of Voltage Swells and Overvoltage Protection Inflence of Power System Events on SSC Performance THESIS OUTLINE SYSTEM DESCRIPTION AND DEVELOPMENTS INTRODUCTION VOLTAGE DIPS STATIC SERIES COMPENSATOR Operational principle of Static Series Compensator Layot and Design of SSC Converter Topologies for SSC Half Bridge Topology Fll Bridge Topology Mltilevel VSC CONTROL OF STATIC SERIES COMPENSATOR DOUBLE VECTOR CONTROL FOR MITIGATION OF BALANCED DIPS AND SWELLS Derivation of Doble Vector Controller Stability Analysis Freqency Response of DVC Step Response of DVC MODIFIED DOUBLE VECTOR CONTROLLER FOR MITIGATION OF UNBALANCED DIPS AND SWELLS IX

10 Separation of Positive and Negative Seqence Components Control of Positive and Negative Seqences Higher Switching Freqencies PHASE LOCKED LOOP FOR STATIC SERIES COMPENSATOR Hardware PLL Software PLL SPLL Operational Principle SPLL Modeling SPLL Linearized Model Stability of SPLL TUNING SPLL Tning First-order SPLL Tning Second Order SPLL CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID Control of active and reactive powers Charging Control of Energy Storage Operation Modes of SSC Self-charging Techniqe Compensation Strategies Voltage Difference Compensation In-Phase Compensation Phase Advance Compensation Progressive Phase Advance Compensation Proposed Control Algorithm to Optimize SSC Performance STATIC SERIES COMPENSATOR AS AN ACTIVE FILTER Voltage Harmonics Moving Average Filter Resonant Filter Block Diagram of Proposed Controller for Mitigation of Voltage Dips and Harmonics MITIGATION OF VOLTAGE SWELLS AND OVERVOLTAGE PROTECTION Voltage Swells Overvoltage Protection Scheme Online protection X

11 Offline protection Design of dc resistor SUMMARY OF CHAPTER RESULTS AND ANALYSIS INTRODUCTION SIMULATION MODEL EXPERIMENTAL SETUP GENERATION AND MITIGATION OF VOLTAGE DIPS Generation of Voltage Dips Mitigation of Balanced Voltage Dips Mitigation of Unbalanced Voltage Dips PERFORMANCE OF SOFTWARE PHASE LOCKED LOOP CAPABILITY OF SSC TO MITIGATE VOLTAGE SWELLS MITIGATION OF HARMONICS CONTROL OF ENERGY FLOW Startp Minimization of Active Power PERFORMANCE OF SSC DUE TO POWER SYSTEM EVENTS SUMMARY OF CHAPTER CONCLUSIONS AND RECOMMENDATIONS INTRODUCTION CONCLUSIONS RECOMMENDATIONS REFERENCES...77 PAPER A POWER ELECTRONICS FOR POWER QUALITY IMPROVEMENTS...A.1 PAPER B STATIC SERIES COMPENSATOR FOR MITIGATION OF VOLTAGE DIPS...B.1 PAPER C TRANSIENT PERFORMANCE IMPROVEMENTS OF STATIC SERIES COMPENSATOR BY DOUBLE VECTOR CONTROL...C.1 XI

12 PAPER D MITIGATION OF UNBALANCED VOLTAGE DIPS USING STATIC SERIES COMPENSATOR...D.1 PAPER E TUNING SOFTWARE PHASE-LOCKED LOOP FOR STATIC SERIES COMPENSATOR...E.1 PAPER F TESTING STATIC SERIES COMPENSATOR AGAINST CAPACITOR BANK ENERGIZING... F.1 PAPER G1 ENERGY FLOW CONTROL BETWEEN STATIC SERIES COMPENSATOR AND DISTRIBUTION SYSTEMS... G1 PAPER G2 ENERGY OPTIMIZATION CONTROL TECHNIQUES BY STATIC SERIES COMPENSATOR FOR CONSTANT POWER FACTOR LOADS... G19 PAPER H OPERATION OF STATIC SERIES COMPENSATOR UNDER DISTORTED UTILITY CONDITIONS... H.1 PAPER I OPERATION OF STATIC SERIES COMPENSATOR UNDER DISTORTED UTILITY CONDITIONS... I.1 XII

13 CHAPTER 1. INTRODUCTION 1.1. BACKGROUND AND MOTIVATION Modern indstrial processes are based on a large amont of electronic devices sch as programmable logic controllers and adjstable speed drives. Unfortnately, electronic devices are sensitive to distrbances, and ths, indstrial loads become less tolerant to power qality problems sch as voltage dips, voltage swells, and harmonics. Voltage dips are considered the most severe distrbances to the indstrial eqipment [1,2]. A paper machine can be affected by distrbances of only 1 % voltage drop lasting for 1 ms [3]. A voltage dip of 75 % (of the nominal voltage) with dration shorter than 1 ms can reslt in material loss in the range of thosands of US dollars for the semicondctors indstry [4]. Swells and overvoltages can case overheating, tripping or even destrction of indstrial eqipment sch as motor drives, srge arrestors and control relays. From the reference [5], the following statement is qoted: There are abot 1 million US Dollars direct losses of damaged electronic devices cased by lightning overvoltage in Shanghai, China, So, adopting effective measrements and devices to protect these electronic systems from being damaged by electromagnetic implse and overvoltage is very rgent. Harmonic contamination has become a problem to sensitive loads. The effect of harmonic distortion on eqipment and power system operation is docmented in many textbooks sch as [6] and [7], and in research pblications, for instance [8] and [9]. The electronic eqipment is a very sensitive load against harmonics becase their control depends on either the peak vale, or the zero crossing of the spplied voltage, which are all inflenced by the harmonic distortion.

14 1.2 CONTRIBUTIONS To overcome the mentioned problems, the concept of cstom power has been introdced recently [2,1]. Cstom power is a strategy, which is designed primarily to meet the reqirements of indstrial and commercial cstomers. The concept of cstom power is to se power electronics or static controllers in the medim voltage distribtion system aiming to spply reliable and high-qality power to sensitive sers. Power electronic valves are the basis of those cstom power devices sch as the static transfer switch, active filters and converter-based devices. Converter-based power electronics devices can be divided into two main grops: shnt-connected and seriesconnected devices. Both shnt- and series-connected devices have been proposed in literatre for the medim-voltage applications. The shnt-connected device is known as the Distribtion Static Compensator (DSTATCOM) [11,12] and the series device is known as the Static Series Compensator (SSC), commercially known as the dynamic voltage restorer [3, 13, 14, 15]. It has also been reported in literatre that both the SSC and DSTATCOM have been sed to mitigate the majority of the power system distrbances sch as voltage dips, swells, flicker, nbalance and harmonics [11-15]. The SSC is best sited to mitigate voltage dips and nbalanced grid voltages, where it can inject a voltage in series with the spply voltage to keep the voltage constant at the load. The dynamic performance of the SSC is important since the load shold not be exposed to voltage dips at all in order to maintain a reliable operation. The thesis focses on the control of the SSC in order to improve the transient and the steady-state responses and the injection capability. The injecting capability of the SSC is not only inflenced by the control algorithm bt also limited by the size of the energy storage device employed. Ths, a stdy of the energy storage is carried ot when sing a capacitor bank as the energy storage device. Three power qality isses are mainly investigated in the thesis: 1) voltage dips; 2) voltage swells; 3) voltage harmonics. For each problem, a control algorithm is developed and implemented in order to ensre the sccessfl operation of the SSC CONTRIBUTIONS Modeling and Simlation of SSC A simlation model incorporating the SSC, the grid and different load types is developed and implemented in PSCAD/EMTDC. The model combines both the existed component models and the ser-defined models. User-defined models are designed sing the FORTRAN langage and they are mainly bilt in the controller of the SSC Doble Vector Controller for Balanced Dips A control algorithm is developed and implemented in order to mitigate the balanced voltage dips. It is based on the vector control approach and consists of two control loops. Ths, the developed control algorithm is referred to as the Doble Vector Control (DVC) algorithm. 14

15 1. INTRODUCTION The DVC incorporates both voltage and crrent controllers and it has improved the transient performance of the SSC. The response time of the DVC is considerably fast. Ths, the load voltage is restored within this response time (less than 4 ms) in case of balanced voltage dips Mitigation of Unbalanced Dips Two control strategies have been proposed and implemented in order to mitigate nbalanced voltage dips by the SSC. The first strategy ses a fast techniqe for separating positive and negative seqence components of the spply voltage, which are then controlled separately. Ths, two controllers are implemented for the two seqences, each based on the vector control. The second strategy is based on sing only a positive seqence controller and increasing the switching freqency Software Phase Locked Loop A software phase-locked loop (SPLL) with a PI controller has been proposed for the SSC applications. A criterion to tne the SPLL is developed and the gains of the PI controller are determined to obtain the desired transient performance and moreover filter ot the harmonics of the grid voltage. The proposed SPLL plays an important role to control the flow of the electrical energy between the SSC and the grid. The proper gains of the PI controller are selected in order to obtain the correct phase information of the grid voltage for the different compensation strategies Control and Optimization of Energy Flow Startp of SSC Dring startp of the SSC, the voltage sorce converter (VSC) of the SSC is sed to charge its energy-storage capacitor. Ths, the proposed charging procedre is called the selfcharging techniqe. Two options have been proposed: 1) the phase angle of the load voltage is constant; 2) the magnitde of the load voltage is constant. A charging control algorithm has been proposed and implemented in each case. The factors affecting the design of the energy storage-capacitor have been investigated and a design gide for the energy-storage capacitor is given. Minimization of Active Power Reqirements Minimization of the injected active power is realized by injecting a voltage with the proper phase shift with respect to the load crrent. This idea has been proposed in literatre and referred to as the Phase Advance Compensation (PAC). However, in some cases, the PAC may fail to minimize the active power becase of the power factor of the load. Ths, for different compensation strategies have been stdied in order to ensre the minimization of the active power: 1) Voltage Difference Compensation; 2) In-Phase Compensation; 3) Phase Advance Compensation; 4) Progressive Phase Advance Compensation. The effect of the load power factor on the compensation techniqes has been investigated. A control algorithm based on a combination of the for strategies is proposed taking into accont the 15

16 1.2 CONTRIBUTIONS isses: 1) minimization of the active power; 2) keeping the injected voltage within the ratings of the SSC; 3) smoothing the load voltage waveform Controller for Mitigation of Voltage Dips and Harmonics A control algorithm to mitigate the voltage dips and harmonics has been developed and implemented experimentally. A moving average filter is employed to extract the fndamental components of the measred voltages and crrents. Those are needed to control the performance of the SSC. Also, an active filtering capability is added by sing the resonant filters for the 5 th and the 7 th harmonics. With this algorithm both the fndamental component and harmonics are accrately detected and controlled Mitigation of Voltage Swells and Overvoltage Protection The possibility of employing the SSC to mitigate voltage swells/overvoltages has been investigated theoretically and experimentally. An overvoltage protection scheme has been proposed to protect the SSC online and offline. The online overvoltage protection is based on sing a dc chopper with a resistor. The design of the dc resistor has been discssed Inflence of Power System Events on SSC Performance A nmber of power system events have been described and simlated. The simlated events are: short-circit falts; capacitor-bank energizing; transformer energizing; load switching (indction motor start, diode rectifier start). The performance of the SSC with the DVC algorithm has been examined for each event. Moreover, the case of capacitor bank energizing was stdied in more details becase the capacitor bank switching reslts in a sstained overvoltage and a voltage transient THESIS OUTLINE The thesis is composed of this introdctory chapter, three chapters, and ten papers (pblications) arranged as follows: Chapter 2 presents the system description and the developments of the research work. General description of the SSC is given and different converter topologies are explored. All the developed controllers are explained and the investigated topics are discssed. The reslts of the simlations and experiments are analyzed in Chapter 3. Chapter 4 introdces the conclsions of the research work and proposes frther research topics based on the achievements of this work. Paper A presents an overview of the power electronics controllers sed for power qality improvements. The definitions and examples of the power qality problems are given. The focs was given on the voltage dips, as they are the most severe problem to indstrial loads. 16

17 1. INTRODUCTION Some soltions to mitigate the power qality problems by sing the power electronics apparats are explored. The operational principle, configration, design criteria, and rated power estimation of the SSC are explained in Paper B. The sed control techniqes are discssed aiming to compromise among them based on their sitability with the SSC reqirements. In Paper C, the principle and verification of the DVC algorithm are presented. The loop gains are determined according to the system stability analysis, carried ot on the closed loop system. Experiential reslts on a 1 kv SSC setp are shown with different load types: static linear; dynamic linear and nonlinear loads. Mitigation of nbalanced voltage dips is investigated in Paper D. Two control strategies to improve the dynamic performance of the SSC are presented. The first strategy ses a fast techniqe for separating positive and negative seqence components of the spply voltage, which are then controlled separately. The second strategy is based on sing only a positive seqence controller and increasing the switching freqency. Paper E proposes a software phase-locked loop (SPLL) with a PI controller for the SSC applications. A tning criterion for the SPPL is developed to satisfy the freqency reqirement of most of the loads. It is also discssed that by sing proper selection of the gains, the SPPL behaves as a low pass filter. Ths, the harmonics in the grid voltage may not affect the steady-state performance of the SPLL. In Paper F, the performance of the SSC de to pstream capacitor bank energizing is stdied. Upstream capacitor-bank energizing leads to a transient at the terminals of the SSC followed by a sstained overvoltage. Simlation reslts of a PSCAD/EMTDC system model with pstream capacitor bank energizing are presented. The control and optimization of the power flow between the SSC and the grid is described in Paper G1 and Paper G2. This part consists of two main parts: 1) startp of the SSC; 2) minimization of the active power reqirements. The first part considers the charging of the energy storage by either a shnt diode rectifier or by the voltage sorce converter of the SSC itself. The second part proposes a control algorithm based on different compensation strategies in order to minimize the reqired active power and also keeps the injected voltage by the SSC within its ratings. Paper H discsses the capability of the SSC to mitigate voltage swells. The conseqences of the voltage swells on the SSC are identified. Simlations and experiments are carried ot to show the ability of the SSC to mitigate voltage swells. Also an overvoltage protection scheme is proposed and designed. The overvoltage protection of the SSC is realized either online to mitigate voltage swells or offline to bypass the SSC. 17

18 1.3 THESIS OUTLINE In Paper I, the fnctionality of the SSC is extended to work as a series active filter. A control algorithm is developed and implemented to mitigate voltage dips and harmonics. The developed controller consists of three main parts: 1) extraction of the fndamental component by a moving average filter; 2) control of fndamental component by the DVC; 3) extraction and control of the voltage harmonics by the resonant filters. The operation of the SSC nder distorted tility conditions is discssed and some recommendations are given. 18

19 CHAPTER 2. SYSTEM DESCRIPTION AND DEVELOPMENTS 2.1. INTRODUCTION Power qality problems encompass a wide range of distrbances that can disrpt the operation of sensitive indstrial loads and case a loss of prodction. The following power qality problems have been identified in a nmber of standards sch as [16,17] and textbooks sch as [18, 19]: short interrptions; voltage dips; voltage swells/overvoltages; voltage and crrent transients; voltage and crrent harmonic distortion; voltage flicker; nbalance; power freqency variations. A description of most of the mentioned power qality problems is given in Paper A. To many consmers of electrical energy, especially indstrial consmers, voltage dips are the most important power qality distrbance in the power systems [2, 3]. The otage costs associated with poor power qality are docmented and serve as an argment to stdy the possibility of sing power conditioning eqipment [4]. The effects of voltage dips, swells and flickers on end-sers have been formlated in the literatre sch as [1-6]. Dips, depending on the severity and dration, can case compter resets, memory loss, tripping of adjstable speed drives, loss of motor loads, and this in trn leads to serios disrption of the prodction process. The fast development and continos innovation of valves and controllers for power electronics have made it possible to solve the power qality problems by sing gridconnected voltage sorce converters (VSCs). The VSC, connected in series with the grid as a static series compensator (SSC), also known (commercially) as the dynamic voltage

20 2.2. VOLTAGE DIPS restorer (DVR), is best sited to protect the sensitive loads against the voltage dips. In principle, the SSC injects by means of three single-phase transformers three voltages in the grid, synchronized in sch a way that the load voltage magnitde and phase are constant at any instant to garantee contined operation for the load. On Agst 26, 1996, the world s first SSC was installed on the Dke Power distribtion system to protect a sensitive textile cstomer from voltage dips [13]. As mentioned in Chapter 1, the control of the SSC is the main isse of the thesis. This Chapter introdces the motivation and presents the developments of the research work. A brief description of the SSC is given. The controllers to mitigate three power qality problems (dips, swells and harmonics) are derived. Also other related sbjects sch as the software phase-locked loop and energy flow are discssed VOLTAGE DIPS A voltage dip is a decrease in the RMS voltage from.1 to.9 p at the power freqency for dration from.5 cycles to 1 minte [17]. A synonym for the voltage dip is the voltage sag, which is widely sed in the United States [19]. The voltage dips have the potential to disrpt the operation of the sensitive loads and case a loss of prodction. It is worth to mention that the voltage dips are the main topic of the textbook [18]. The mean cases of voltage dips are the short-circit falts in the transmission and distribtion systems [19]. Also the large indction motors when starting and the transformers when being energized reslt in voltage dips. In some networks, switching on large loads may case voltage dips. The voltage dips de to short-circit falts are characterized by a dip magnitde, a dip dration, and a phase-angle jmp. The voltage dip magnitde is the retained voltage after the initiation of the dip. It can be determined by either the RMS voltage or the peak voltage over half a cycle or one cycle of the fndamental freqency. An example of a voltage dip de to short circit falt is shown in Fig.2.1 and an example de to motor start is shown in Fig.2.2. In the case of voltage dips de to motor start, the characterization needs to be slightly different: other terms are involved sch as recovery time and steady state drop (as illstrated Fig.2.2). The dration of the dip is the time at which the system voltage remains nder a threshold vale, for instance 9% of the pre-dip voltage. If the dip is de to a short-circit falt, the dip dration is mainly determined by the falt clearing time, which is affected by the speed of the protection and the speed of the circit breakers. The phase-angle jmp is a shift in the zero crossing of the instantaneos voltage. Becase the system voltage is a complex qantity consisting of a magnitde and phase angle, an event like a short-circit falt may not only affect the voltage magnitde bt also its phase angle. Normally, voltage dips originated becase of short-circit falts are associated with a phase-angle jmp. 2

21 2 SYSTEM DESCRIPTION AND DEVELOPMENTS RMS voltage in V Maximm drop Steady-state drop Recovery time or time-constant Time in Cycles Fig.2.1. Example of voltage dip de to shortcircit falt. Fig.2.2. Example of voltage dip de to motor start STATIC SERIES COMPENSATOR Operational principle of Static Series Compensator The SSC is a power-qality device that protects highly sensitive loads, mainly indstrial loads, against the common distrbances of the power system sch as voltage dips and swells. Normally, the SSC is connected in series with the distribtion feeder at the medim voltage levels [3]. In principle, the SSC can be installed at any voltage level, bt for the low voltage applications, the SSC may be cost-ineffective compared to the ninterrptible power spply. To be able to mitigate voltage dips/swells, the SSC shold be capable of generating and absorbing active and reactive power to or from the grid. Basically, the SSC is designed to dynamically inject a voltage inj into the power system as shown in Fig.2.3. Fig.2.3a shows a simplified single-phase eqivalent circit of a distribtion feeder with an SSC where the spply voltage g, the injected voltage inj and the load voltage L are in series. So, the SSC is considered to be an external voltage sorce where the amplitde, the freqency and the phase of inj can be controlled. The prpose is to maintain the amplitde of the load voltage fixed and prevent phase jmps. A phasor diagram of a voltage dip with a phase jmp is shown in Fig.2.3b. From Fig.2.3, the load voltage is dedced: L = g + inj. If the spply voltage g has dropped de to a voltage dip or increased de to a voltage swell, the injected voltage by the SSC ( inj ) shold be controlled so that the load voltage L remains the same as dring no-distrbance conditions. In Fig.2.3a, the SSC is modeled as an ideal voltage sorce while it is composed of many components in practice. The layot of the SSC is presented in Sbsection and the description of its individal components is given in Paper B. 21

22 2.3 STATIC SERIES COMPENSATOR + + g inj a) φ L * L i g inj g b) Fig.2.3. Illstrative diagram of operational principle of Static Series Compensator: a) grid, Static Series Compensator and load are in series, b) phasor diagram of voltage dip with phase angle jmp Layot and Design of SSC The SSC components (shown in Fig.2.4) are the VSC, the modlation nit, the control nit, the otpt filter, the injection transformer, the energy storage and the bypass switch. The measred voltages and crrents are the inpts to the distrbance identification, which gives signals to the control nit to fnction when the measred qantities differ from the settings of the controller. The distrbance identification modle triggers the start of the compensation when the spply voltage comes otside of a pre-defined range. Then the control nit generates the voltage references. The voltage references are the inpts to the modlation nit to generate the modlating signals for the valves of the VSC. The energy storage provides or absorbs the reqired active power to compensate the identified voltage dip/swell. Installing an otpt filter between the VSC and the injection transformer redces the dv/dt effect on the windings of the injection transformer. Ths the filter converts the plse-modlated voltage of the VSC into a sinsoidal voltage. The filtered voltage is injected into the distribtion system by the series-injecting transformer. The bypass switch is normally closed to short-circit the SSC. When the distrbance identification nit detects a voltage dip/swell, the bypass switch is opened and the SSC starts the compensation process. Becase the VSC is the basic component of the SSC, it is treated in this Chapter while a detailed description of the SSC is presented in Paper B Converter Topologies for SSC The VSC is the core element of the SSC design since the main fnction (generating the injected voltage) is performed throgh it. Different topologies of the VSC have been proposed in literatre with the SSC applications. Among those are: 1) the half-bridge topology; 2) the fll bridge topology; 3) the mlti-level VSC. 22

23 2 SYSTEM DESCRIPTION AND DEVELOPMENTS + L g R g g i g thy inj i L L c R F LF C F C Fig.2.4. Single-line diagram of Static Series Compensator inclding details of VSC, LC-filter and measred signals for control. Half Bridge Topology The half bridge topology is the basic configration of the VSC, which is known as the sixplse forced-commtated converter. For simplicity, a single-phase half-bridge circit is displayed in Fig.2.5. Each phase of the ac side, which is connected to one of the three legs of the converter, is modeled as a crrent sorce (I g ) since the SSC is connected in series with the grid. The circit contains six valves; each valve may consist of a nmber of semicondctor devices in series or in parallel. For instance, the semicondctor device sed in Fig.2.5 is the inslated gate bipolar transistor (IGBT), with an anti-parallel diode. The restriction is that three valves are condcting at the same time, bt only one valve in each bridge-leg. Hence the phase potentials v a, v b, and v c at each phase leg, referred to the midpoint of the dc-voltage spply m, are determined by the condcting states of the valves. Each phase potential is either U dc /2 or U dc /2. Fll Bridge Topology In the Fll-bridge topology of the VSC, the converter has six legs (12 valves) and each phase of the ac side is connected to two of these legs. For instance, the circit of the phase a is shown in Fig.2.6. The voltage of the phase a is the difference between the potentials v a1 and v a2. This topology has the advantages: 1) the injected voltage is doble of the injected voltage by the half-bridge topology; 2) it enables the control of the zero seqence voltage (if the injection transformer is not delta-connected). The disadvantage is that the nmber of valves is the doble compared to the half-bridge circit. 23

24 2.3 STATIC SERIES COMPENSATOR Mltilevel VSC The mlti-level VSC has been proposed to redce the harmonic content [2], even with a sqare wave modlation, becase it provides the possibility to have different voltage levels. A mlti-level VSC can be realized either by the netral point clamping (as shown in Fig.2.7) or by sing a mlti-bridge VSC as illstrated in Fig.2.8 [21]. In the case of a threelevel, VSC, netral point clamped (NPC), the otpt voltage of the VSC can have one of the three vales +U dc /2,, and -U dc /2. A scheme of the NPC VSC is shown in Fig.2.7. The NPC VSC converter (shown in Fig.2.7) is an alternative to the two-level converter in high power applications. Each phase can be connected to the positive dc terminal by firing S 1n and S 2n simltaneosly while S 3n and S 4n are off. Firing S 3n and S 4n while S 1n and S 2n are off connects the negative dc terminal to the phase n (n = a, b, and c). If S 2n and S 3n are on and S 1n and S 4n are off, the phase n is connected to the midpoint of the dc side, zero potential. The three-level converter reqires six extra diodes if it is compared to the two-level converter to clamp the phases to the zero potential CONTROL OF STATIC SERIES COMPENSATOR The reported control techniqes that have been implemented to control the injected voltage by the SSC may be classified into two main categories: 1) the scalar; 2) the vector control. By the scalar control, it is meant that only the voltage magnitde is controlled by applying the concept of phasors as in [22,23]. Techniqes based on the synchronos reference frame [24-31] are referred to as vector control where the magnitde and the phase of the injected voltage are controlled. The scalar control involves the RMS calclation of the fndamental voltage [22,23], which reqires at least one half period of the fndamental freqency. A block diagram (single-phase) of the scalar control is shown at Fig.2.9, where the inpt to the controller is the instantaneos phase voltage of the grid ( a ). Then the RMS calclations are made online to determine the RMS grid voltage (U a ), which is then sbtracted from the reference of the load voltage (U a * ). U dc 2 S 1 U dc 2 S 1 S 3 v a1 m v a I g m I g U dc 2 S 2. U dc 2 S 2 S 4 v a2 Fig.2.5. Half-bridge topology (single-phase) of voltage sorce converter. Fig.2.6. Fll-bridge topology (single-phase) of voltage sorce converter. 24

25 2 SYSTEM DESCRIPTION AND DEVELOPMENTS S1a S1b S1c U dc 2 D 1a S2a v a D1b S2b D1c S2c m v b U dc 2 D 2a S3a D2b S3b D2c v c S3c S4a S4b S4c Fig.2.7. Three-level Netral Point Clamped Voltage Sorce Converter. + S 1 S 3 + S 1 S 3 I g U dc U dc S 2 S 4 S 2 S S 1 S 3 S 1 S 3 U dc U dc S 2 S 4 S 2 S Fig.2.8. Mlti-bridge Voltage Sorce Converter. The amplitde reference of the injected voltage is obtained by mltiplying this difference by 2 to obtain the magnitde of the injected voltage. It shold be stated that the phase of the voltage reference is obtained by a phase detector, which is synchronized to the grid voltage. The scalar control works fine in the steady state, bt it slows the dynamic performance of the SSC and only the fndamental voltage can be controlled nless an FFT algorithm is inclded and harmonic components are detected. To improve the transient response of the SSC and control the injected active and reactive powers separately, the vector control has been implemented in a way similar to the control of variable speed drives. Both the feedforward/open-loop [24] and feedback/closed loop [25-31] techniqes have been reported. A block diagram of the basic feedforward control of 25

26 2.4 CONTROL OF STATIC SERIES COMPENSATOR the SSC is depicted at Fig.2.1. The grid voltages ( a, b, c ) are measred and transformed to the stationary reference frame ( αβ ). A phase locked loop (PLL) is exploited to calclate the transformation angle (θ), which is reqired to transform the grid voltage from the stationary reference frame to the synchronos reference frame ( dq ). Then the grid voltage is sbtracted from the reference of the load voltage ( *dq L ) to calclate the reference of the injected voltage ( *dq inj ). A backward transformation from the synchronos reference frame to the three-phase is performed in order to obtain the reference of the injected voltage ( * ia, * ib, * ic ) that shold be generated by the VSC. The feedforward control is fast bt does not garantee the system stability and may exhibit a steady-state error. Feedback control of the SSC has been proposed in [25] where the injected voltage by the SSC is measred and sed in a single-loop [25,31] or a mlti-loop [29,3] control system. A block diagram of a single-loop feedback control system is displayed in Fig In feedback control systems (applied to the SSC), an error signal ( ) is generated by sbtracting the actal injected voltage ( inj ) from the reference of the injected voltage ( inj * ). This error signal is fed to a PI controller to obtain the reference of the voltage that shold be generated by the VSC. When designing a control algorithm for the SSC, the LC-filter, monted at the otpt of the VSC as shown in Fig.2.4, is important to consider since it affects the dynamic performance of the SSC. Moreover, the LC-filter cases a voltage drop on the choke branch, which redces the injection capability of the SSC and introdces a phase shift in the injected voltage. Sch effect has been considered in [26,27,28,29]. In [26,27], a simple back calclation of the filter inpt voltage is applied. The algorithm proposed in [27] compensates for the steady state voltage drop de to the LC-filter bt it gives poor transient performance and it is sensitive to variations of the LC-filter parameters. a RMS U a Phase Detect U * a 2 cos(ω t) U * ia * ia To PWM Fig.2.9. Scalar control of Static Series Compensator. PLL θ a b c abc αβ αβ αβ dq *dq L dq *dq inj dq αβ *αβ inj αβ abc * ia * ib * ic Fig.2.1. Feedforward vector control of Static Series Compensator. 26

27 2 SYSTEM DESCRIPTION AND DEVELOPMENTS * inj PI- Controller VSC LC-Filter inj inj Fig Feedback vector control of Static Series Compensator. To overcome this problem of voltage drop across the LC-filter and improve the performance of SSC, the voltage and crrent controllers are incorporated as in [29] and [3]. In [29], the crrent control loop is formed by measring the capacitor crrent and feeding it back to the controller. While in [3] the crrent loop is formed by the indctor crrent. As the indctor crrent shold be measred for the overcrrent protection and it may help in actively damping the resonance between the LC-filter indctor and capacitor, then the indctor crrent is sed in the crrent loop feedback as discssed in [3] DOUBLE VECTOR CONTROL FOR MITIGATION OF BALANCED DIPS AND SWELLS Derivation of Doble Vector Controller The dynamic performance of the SSC may be improved by controlling both the indctor crrent and the capacitor voltage of the LC-filter. Ths, a two-loop control algorithm is proposed in this thesis and it is referred to as Doble Vector Control (DVC). To redce the complexity of the system while deriving the DVC eqations, the injecting transformer (Fig.2.4) is assmed ideal i.e., having zero magnetizing crrent and zero leakage indctance, with trns ratio of 1:1. Also the transformer, the grid and the load are replaced by an eqivalent crrent sorce. Conseqently, the injected voltage by the SSC, inj is the same as the voltage across the LC-filter capacitor c. Hence, the capacitor voltage c is controlled to reglate the load voltage. The crrent throgh the LC-filter indctor is controlled by an inner control loop. To derive the controllers, the LC-filter is modeled in the stationary αβ-frame and transformed into the synchronos reference frame as in (2.1). d x( t) = ALC x( t) + BLC( t), y( t) = CLCx( t) dt (2.1) where x ( t ) = ( i i ) T, ( t ) = ( i ) T d q cd cq, d i d, i q are the d- and q-components of the indctor crrent, cd, cq are the d- and q-components of the injected voltage, d, q are the d- and q-components of the VSC voltage, i gd, i gq are the d- and q-components of the grid crrent. The aim of the controller is to keep the load voltage constant. Ths, the SSC shold inject *dq the voltage c sch that *dq *dq dq = (2.2) c L q g gd gq 27

28 2.5 DOUBLE VECTOR CONTROL FOR MITIGATION OF BALANCED DIPS AND SWELLS where *dq L is the reference voltage demanded by the load and dq g is the grid voltage in the *dq dq-frame. The missing voltage c is injected throgh the injecting transformer. The inpts to the controller are the grid voltages, the grid crrents, the indctor crrents and the capacitor voltages of the LC-filter. The proposed controller is a discrete controller and ses a sampling time of T s. Hence the sampling freqency f s eqals to 1/ T s. The switching freqency f sw is the same as the sampling freqency. The state-space eqation of the LCfilter, (2.1) is discretized sing the forward Eler method [32] and is then integrated from kt s to ( k + 1)T s (one sample period), as given in (2.3). x( k + 1) = ALCD x( k) + BLCD( k), y( k) = CLCDx ( k) (2.3) The following assmptions are made to derive the controller: The grid crrent is constant independently of the variations in the crrents and voltages of the LC-filter; The capacitor voltage and the indctor crrent change linearly dring one sample; The controller ses a dead-beat gain; the otpt vector y (k) changes linearly and is eqal to the reference otpt vector y * ( k ) after one sample; The average vales of the capacitor voltage and the indctor crrent over the sample period kt s to ( k + 1) T s are each eqal to half of the smmation of the real vale and the reference vale at the sample k. The controlled variables are the indctor crrent i dq dq and the capacitor voltage c. Based on the above assmptions and after algebraic maniplation of (2.3), the eqations of the controller are obtained as: Voltage Controller Oter *dq dq ωcf *dq dq *dq dq i = ig ± j { c + c } + K{ c c } Loop 2 (2.4) Crrent Controller Inner Loop where *dq i and *dq = *dq c + R F i dq ωl ± j 2 F *dq dq *dq dq { i + i } + K { i i } p (2.5) *dq are the reqired reference crrents and voltages to track the reference of the injected voltage. The gains K and K p are the dead-beat gains and they are calclated in terms of the LC-filter parameters (R F, L F, and C F ) and the sampling time; K = C F /T s, K p = L F /T s + R F /2. In (2.4) and (2.5), j means a 9 o phase shift which implies the cross copling between the d- and the q-components. A block diagram of the DVC is depicted in Fig In Fig.2.12, voltage and crrent limits are set in the controller in order to avoid overmodlation and limit the indctor crrent. To stabilize the system, the gains K and K p are altered from the dead-beat gains by the factors K s and K ps, respectively. In other words, the gains of the two loops are given by: K = K s C F /T s and K p = K ps (L F /T s + R F /2) Ths, selecting the vales of the two factors K s and K ps determines the system stability. 28

29 2 SYSTEM DESCRIPTION AND DEVELOPMENTS abc g i abc g abc c i abc abc αβ abc αβ abc αβ abc αβ αβ g i αβ g αβ c i αβ θ αβ θ αβ θ αβ θ αβ dq dq dq dq dq g i dq g dq c i dq *dq L *dq c i *dq Crrent Limit *dq c i dq Fig Block diagram of doble vector control. sw *dq αβ Voltage Limit θ dq αβ αβ abc *abc Stability Analysis To perform a stability analysis for the system, the closed-loop model of the system with the proposed controller is derived. The closed loop system implies the relation between the system inpts and the controlled variables. In this case, the system inpts are the reference *dq of the capacitor voltage c and the grid crrent i dq g, which is considered as a distrbance. dq While the controlled variables are c and i dq. A block diagram of the derived closed loop system is displayed at Fig.2.13, where G inv is the transfer fnction of the VSC. In the dq *dq derived model, G inv is a linear fnction with a nity slop ( = ) and satrates if the reference voltage is otside the range 1 p (1 p = rated dc voltage of the VSC, for a fllbridge topology of VSC). The closed-loop model is written in a state-space form as: x( k + 1) = Φ x( k) Γ ( k) (2.6) LC + d q cd cq ( k ) = cd cq igd igq. The matrices Φ LC and Γ LC are calclated after discretizing the filter model (2.1) and combined with the controller (2.4) and (2.5). The stability of Linear Time Invariant (LTI) systems is determined by the location of the eigenvales of the matrix Φ LC with respect to the nit-radis disk [32]. The LTI system is asymptotically stable if all the eigenvales of the matrix Φ LC are located inside the nit disk. If λ i is an eigenvale of the matrix Φ LC, then the system is asymptotically stable if and only if: λ i < 1 i = 1 to 4. The stdy of the system stability is eqivalent to variation of the factors K s and K ps sch that the ineqality λ i < 1 i = 1 to 4 is satisfied. To calclate the eigenvales of the matrix Φ LC, the determinant of the matrix ( λ I Φ LC ) is set to zero. This yields a forth-order eqation in λ. So the complex vector fnction λ K s, K ) is calclated. The stability margin is obtained Where: x( k ) = ( i i ) T * * and ( ) T ( ps by solving the eqation: λ ( Ks, Kps) = 1. Solving this gives the vales of K s and which make the system marginally stable. LC K ps, 29

30 2.5 DOUBLE VECTOR CONTROL FOR MITIGATION OF BALANCED DIPS AND SWELLS i dq *dq g c K K i + z-1 dq c Voltage Controller i *dq dq i Kip K p+ z-1 Crrent Controller *dq c *dq G inv VSC dq c dq T s/ LF z-1 Indctor dq i dq i g T s/ CF z-1 Capacitor dq c Fig Closed-loop model of doble vector controller. Fig.2.14 shows the absolte-vale contors of the eigenvales 1 and 2, when the stabilization factors vary from. to 2.5. The plotted contors in Fig.2.14 are.2-most thin,.4,.6,.8,1.-most thick. The inclined dashed line represents the ineqality K s <K ps while the horizontal dashed line represents the ineqality K s < 1. The system is marginally stable when K = ps 2, which means that the inner-loop gain can be increased p to twice the deadbeat gain. K can vary from. to 1. and the system is stable provided that ineqality s K s < K ps is satisfied. Fig.2.15 shows the absolte-vale contors of the eigenvales 1 and 2, when the stabilization factors vary from. to 2.5. The plotted contors are.2-most thin,.4,.6,.8,1.-most thick. The eigenvales 3 and 4 are high for low gains and decreases as the gains increase (in the plot range). The conclsion is that the system is stable when K ps < 2, which means that the inner-loop gain can be increased p to twice the dead-beat gain and K can vary from to less than 1.. s Freqency Response of DVC After the derivation of the closed-loop (2.6), the system-freqency response can be investigated. The system parameters are given in Paper C. In Fig.2.16, the freqency response from the reference d-voltage of the capacitor * cd to the d- and q-voltages of the capacitor, cd and cq, is presented. As seen from Fig.2.16, the cross copling between and cq is very low for low freqencies and increases for high freqencies * cd K s K s. K ps K ps Fig Absolte-vale contors of eigenvales 1 and 2, stability margin (most-oter, thick). Fig Absolte-vale contors of eigenvales 3 and 4, stability margin (most-oter, thick). 3

31 2 SYSTEM DESCRIPTION AND DEVELOPMENTS 1 1 gain [db] phase [deg] Freqency [Hz] Fig Freqency response from d-voltage reference to d- (solid) and q- voltage (dashed) of LCfilter capacitor. The gain from * to cd cd is eqal to db, nity in the linear scale, p to 37 Hz, which implies that cd tracks * accrately p to 37 Hz. For higher freqencies, the gain cd decreases and the phase shift increases. Ths, the system behaves as a low-pass filter. More details regarding the freqency response are given in [3] Step Response of DVC The step response of the SSC with the DVC is investigated by applying voltage dips and swells at the grid voltage. Voltage dips and voltage swells imply that the injected voltage by the SSC is stepped p or down to keep the load voltage constant. The reslts of the step response are analyzed in Chapter MODIFIED DOUBLE VECTOR CONTROLLER FOR MITIGATION OF UNBALANCED DIPS AND SWELLS If the three-phase voltage of the grid is balanced, a transformation into the synchronos reference (dq) frame reslts in dc qantities. Hence, the SSC can se a conventional PI controller to control the injected voltage. However, if the grid or the load voltages are nbalanced, a ripple of twice the grid freqency occrs in the dq-frame. The positive seqence components appear as dc qantities in the dq-frame, which rotates positively with the grid anglar freqency ω, while the negative seqence components appear as 2ω rad/s components in the dq-frame. Conseqently, the DVC algorithm shold be modified to 31

32 2.6 MODIFIED DOUBLE VECTOR CONTROLLER FOR MITIGATION OF UNBALANCED DIPS AND SWELLS handle the nbalances in order to obtain a high performance controller. The proposed modifications of the DVC are: 1) detection of positive and negative seqence components of the nbalanced qantities; 2) se of two controllers: one for the positive seqence and one for the negative seqence component. The detected positive seqence components are transformed and controlled in the dqpframe, i.e. a coordinate system that rotates positively with the grid anglar freqency ω, where they appear as dc qantities. While the detected negative seqence components are transformed and controlled in the dqn-frame, i.e. a coordinate system rotating in the negative (clockwise) direction. In the latter frame, negative seqence components appear as dc components Separation of Positive and Negative Seqence Components In Fig.2.17, the algorithm sed to extract the seqence components is shown. This detection algorithm is called the delayed signal cancellation (DSC) algorithm and has been proposed in [33]. The positive seqence of the vector g, gp in the positively rotating dqp-frame is calclated as dqp dqp ( ( k) + ( k N ))/ 2 dqp gp ( k) = (2.7) g g d where N d is eqal to f s /(4f 1 ) and f 1 is the grid freqency of the fndamental component. The negative seqence of the vector g, gn in the negatively rotating dqn-frame is calclated as: dqn gn dqn dqn ( ( k) + ( k N ))/ 2 ( k) = (2.8) g g d Ths, the positive seqence of the vector g is obtained by adding the vector g at the sample k to the vector g at the sample k-n d, which is delayed by one forth of the fndamental period. (t ) g1 S & H (t ) g2 g3(t ) S & H S & H g1 g2 g3 (k) (k) (k) abc αβ + e θ j + αβ dqp g g e jθ dqn g.5 dqp gp dqn gn Fig Delayed signal cancellation method to separate positive and negative seqence components. 32

33 2 SYSTEM DESCRIPTION AND DEVELOPMENTS Control of Positive and Negative Seqences The eqations of the positive seqence controller of the DVC are given in (2.9), where the sbscript p denotes the positive seqence. Becase the negative seqence rotates in opposite direction to the positive seqence, the cross-copling terms between the d- and the q- components have opposite signs in the negative seqence controller. Hence, the eqation of the negative seqence controller are given in (2.1), where the sbscript n denotes the negative seqence. Positive Seqence Controller Negative Seqence Controller * idp = igdp ω CF / 2) * iqp = igqp + ω CF / 2) * * dp = cdp + RFidp ω ) * * qp = cqp + RFiqp + ω F ) dp * * ( cqp + cqp ) + K ( cdp cdp ) * * ( cdp + cdp ) + K ( cqp cqp ) * * LF / 2 ( iqp + iqp ) + K p ( idp dp ) * * L / 2 ( i + i ) + K ( i ) ( ( * idn = igdn + ω CF / 2) * iqn = igqn ω CF / 2) * * dn = cdn + RFidn + ω ) * * qn = cqn + RFiqn ω F ) dn ( i ( i dp * * ( cqn + cqn ) + K ( cdn cdn ) * * ( cdn + cdn ) + K ( cqn cqn ) * * LF / 2 ( iqn + iqn ) + K p ( idn dn ) * * L / 2 ( i + i ) + K ( i ) ( ( p qp ( i ( i dn p qn qp qn (2.9) (2.1) After calclating the reference voltage of the VSC, the dq-negative and the dq-positive seqences are transformed to the αβ-frame. Then they are added, transformed into the three-phase frame and compared with the trianglar wave to obtain the PWM pattern. A schematic diagram for the modified doble vector controller is presented in Fig Higher Switching Freqencies It has been shown in the previos section that adding a negative seqence controller may improve the performance of the SSC in the case of nbalanced dips. However, this has the disadvantage of a more complex controller. *dqp L abc g abc αβ θ αβ g dqp g dqn g *dqn L abc c abc αβ i abc g i abc *dqp c abc αβ abc αβ * dqn c αβ c αβ i g θ αβ i dqn c c dqp i dqp g i dqp i dqn g i dqn * dqp * dqn θ dqp αβ dqn αβ *αβ αβ abc sw Fig Schematic diagram of modified doble vector controller. 33

34 2.6 MODIFIED DOUBLE VECTOR CONTROLLER FOR MITIGATION OF UNBALANCED DIPS AND SWELLS If the switching and the sampling freqencies increase, only a positive seqence controller is needed. By increasing these freqencies, a faster controller is obtained and the crrent ripples are redced. Apparently, the negative seqence components are seen (by the controller) as variations in the positive seqence and with higher switching/sampling freqency, the controller is able to track these variations. Bt the switching losses increase with the increase of the switching freqency. Therefore, sch strategy may be sitable for low-power loads PHASE LOCKED LOOP FOR STATIC SERIES COMPENSATOR The accrate phase information is crcial for most of the modern power electronics apparats sch as the SSC. Normally obtaining the phase information has been realized by the Phase-Locked Loop (PLL) Hardware PLL The hardware PLL was first described in 1923 and 1932 [34]. In 197 it become widespread becase of the development of integrated circits. The classical configration of the PLL is shown in Fig Three main blocks constitte the basic PLL hardware: phase detector, low-pass filter and voltage-controlled oscillator. Normally, the phase detector is of the mltiplier type whose otpt consists of a dc term that has the phase information of the inpt signal and an ac term that shold be filtered by the low-pass filter. The low-pass filter can be realized either by a passive filter or an operational amplifier. The otpt of low pass filter is a dc signal that corresponds to the phase error between the inpt and otpt voltages. This dc signal is the inpt to the voltage-controlled oscillator Software PLL With the advanced technology of microcontrollers and digital signal processors, all the fnctions of the classical PLL have been implemented by software. Hence the software PLL (SPLL) has become a competitive alternative to the hardware PLL. The SPLL design offers the most degrees of freedom available in any PLL design [35], becase the SPLL can be tailored to perform any fnction, withot modifying the hardware as the case of the classical PLL. Moreover, the classical PLL adds some cost to the total cost of the system. The flexibility added by the SPLL arises from the fact that the design parameters can be easily changed by modifying a few lines in the software code [36]. In single-phase systems, the zero-crossing detection has been sed to estimate the phase angle of the grid voltage [37]. Despite the ease to write a zero-crossing detection algorithm, the dynamic performance of the loop is slow and a fast tracking performance is impossible. This is de to that the response can never be faster than ½ cycle of the fndamental voltage. In addition, the accracy of zero-crossing detection is inflenced by distrbances in the inpt signal sch as harmonics. Fast tracking has been obtained by sing the delayed grid voltage by one forth of a period of the fndamental freqency together with the grid voltage itself to constrct a stationery reference frame and then a synchronos reference frame [38]. 34

35 2 SYSTEM DESCRIPTION AND DEVELOPMENTS (t ) in ε (t ) F (t ) (t ) K d F (s) K v o Fig Scheme of classical hardware phase locked loop. In three-phase systems, the SPLL has been proposed for the SSC by transforming the threephase voltage of the grid into the synchronos reference frame [39, 4] and the performance of the SPLL is controlled by either a lead/lag filter or a PI controller. In [39] and [4], it is stated that the bandwidth of the SPLL shold be low for SSC applications bt it is not clear how slow the performance shold be and how to tne the SPLL. Tning the SPLL to get a desired transient performance is strongly related to the applications where the SPLL is sed. In this thesis, a criterion to tne the SPLL for the SSC is discssed and the gains of the PI controller are determined to obtain the desired performance SPLL Operational Principle A block diagram of the proposed SPLL is depicted in Fig.2.2. The operational principle of the SPLL is explained throgh the following steps: measre and sample the grid voltage g1( t ), ( t), ( ) g2 t g3 to get ( k g1 ), ( k), ( k) ; g2 g3 transform the sampled grid voltage to the αβ-frame, obtaining ( k ) and ( k) ; gα gβ normalize to the magnitde of the αβ-vector of the grid voltage, αβ g = + ; 2 gα 2 gβ separate the positive and the negative seqence by sing the delayed signal cancellation techniqe (DSC) to obtain the positive seqence of the grid voltage in the positive αβframe, αβp-frame. The DSC was briefly explained in Section 2.6; transform from αβp-frame to positive dq-frame, dqp-frame to get the positive seqence components of the grid voltage, gdp and gqp ; the d-component gdp is the inpt to the PI controller of the SPLL to calclate the change in the anglar freqency of the grid voltage, ω ; ( K P -PLL + K I-PLL /( z 1) ) gdp ω = (2.11) where K P-PLL and K I-PLL are the proportional and the integral gains of the PI controller. Here it is worth to state that an integration part is necessary especially in the case of low-inertia grids where the grid freqency can deviate arond the nominal freqency. * * * add the reference anglar freqency, ω = 2πf, where f is the reference freqency of the grid, 5 or 6 Hz. ω + mltiply ω by the sampling time T s to obtain the increment of the phase angle θ (k) * = ω ω (2.12) ; θ = Tsω (2.13) 35

36 2.7 PHASE LOCKED LOOP FOR STATIC SERIES COMPENSATOR ω * g α 1 αβ g g β 123 αβ g α g β g βn g αn g αp g β p αβp dqp T s g dp K P-PLL + K z 1 qp g θ 1 z I-PLL. ω 2π ω (t ) (t ) (t ) g3 T s θ (k) g1 (k) (k) g2 g3 ω * g1 g2 Fig.2.2. Block diagram of proposed software phase locked loop. by integrating the increment θ, the estimated phase angle of the grid voltage θ is obtained; 36 θ = z θ /( z 1) (2.14) the estimated angle θ is sed to calclate the new d-component gdp ntil gdp becomes zero and gqp becomes constant and the difference between the actal phase angle of the grid voltage and the estimated angle becomes zero SPLL Modeling A model of the SPLL is obtained to be able to tne it. The grid voltage, after sampling is assmed as: = = = 2U cos( θ ) 2U cos( θ 2π ) 3 2U cos( θ + 2π ) 3 (2.15) where U is the RMS of the grid voltage (phase to grond). The αβ-components of the grid voltage are calclated as gα gβ 2 1 = g1 g2 g 3 (2.16) αβ After normalization to g and algebraic maniplation of (2.16), the αβ- components of the grid voltage become:

37 gα gβ cos = sin ( θ ) ( ) θ 2 SYSTEM DESCRIPTION AND DEVELOPMENTS (2.17) Then the positive seqence is extracted to obtain gαp and gβp. The dqp- components of the grid voltage are calclated as: gdp gqp = cos( θ ) sin( θ ) sin( θ ) cos( θ ) gαp g βp (2.18) where θ is the estimated angle by the SPLL. It is worth to mention that as the synchronization is made with respect to a virtal flx vector, -π/2 is added to the estimated angle. After algebraic maniplation, the dqp- components of the grid voltage are obtained: When the difference gdp gqp sin( θ θ ) = cos( θ θ ) θ θ approaches zero the dqp-components become (2.19), 1 (2.2) gdp gqp Eqation (2.19) represents a nonlinear relation where the d-component of the grid voltage gdp is a fnction of the sine of the difference between the actal and the estimated angles. To simplify the analysis, a linearized model is obtained SPLL Linearized Model A linearized model of the SPLL can be obtained if the difference between the actal and the estimated phase angles is considered small. This assmption implies that sin( θ θ ) θ θ Conseqently, gdp can be approximated: (2.21) (2.22) gdp θ θ = e where e is the phase error between the actal phase and the estimated one. Ths, the block diagram of the SPLL (Fig.2.2) is redrawn as shown in Fig.2.21 and the forward transfer fnction becomes: ( K T ( z + ( K / K ) 1) )/( ) 2 G F( z) = P-PLL s I-PLL P-PLL z 1 (2.23) The closed-loop transfer fnction of the SPLL is G SPLL θ ( z) ( z) = = θ ( z) z 2 K + ( K P-PLL P-PLL ( z + K / K 1) Ts I-PLL T 2) z + T ( K By (2.24), the stability margin of the SPLL is checked. s s P-PLL I-PLL K P-PLL ) + 1 (2.24) 37

38 2.7 PHASE LOCKED LOOP FOR STATIC SERIES COMPENSATOR θ e K P-PLL + K z 1 I-PLL ω T s θ 1 z 1 θ Fig Simplified model of software phase locked loop assming that it works within reference freqency range Stability of SPLL The stability conditions of the SPLL can be obtained by investigating the SPLL transfer fnction in (2.24). The closed system given by (2.24) has a zero at z = 1 ( KI -PLL / KP-PLL ) 1 and two poles at 2 2 z = 2 K ± P-PLLTs K 2Ts 4KI-PLLTs. Doing the Jry s stability test 2 P-PLL [32] yields the following conditions to keep the system stable: KI-PLL 2 (2.25) K P -PLL >., K P-PLL < + and K I-PLL < KP- PLL 2 T s If the integral gain is taken in the form K I -PLL = KP-PLLTs / Ti, where T i is the integration time, then T i shold be higher than the sampling time T s to keep the system stable. If the integral gain is assmed very small, K I-PLL., the closed loop system of the SPLL is frther simplified to a first order system having the transfer fnction given by (2.26), which clearly shows that K < 2 T to keep system stability. P -PLL / G SPLL 2.8. TUNING SPLL s θ ( z) ( z) = = θ ( z) K z + K P-PLL P-PLL Ts T 1 s (2.26) Tning First-order SPLL Tning the SPLL to get a desired transient performance is strongly related to the applications where the SPLL is sed. In this Section, a criterion to tne the SPLL for SSC applications is specified. The gains of the PI controller are determined to obtain the desired performance. As the SSC is sed to protect sensitive loads against voltage dips and normally voltage dips are associated with phase angle jmps, an extremely fast SPLL will reslt in a phase angle jmp of the load voltage. Some loads are distrbed by the phase-angle jmp and ths an extremely fast SPLL is not preferred. Moreover, an extremely fast SPLL implies that the 38

39 2 SYSTEM DESCRIPTION AND DEVELOPMENTS proportional gain can be high and the stability limit cold be reached. Extremely slow SPLL wold cope with the phase angle jmp of the load voltage bt it does not sit the control of the SSC. This is tre becase the SPLL will calclate a wrong phase angle dring the voltage dip if the response time of the SPLL is set mch longer than the dip dration. In this case, the phase angle of the load voltage can be kept constant bt the SPLL is not locked to the grid dring the voltage dip. Ths, the SPLL shold be tned sch that most of the loads will not be distrbed dring a voltage dip. Interpreting the Eropean Standard EN516, most of the loads perform satisfactorily if the deviation of the grid freqency is kept within ±1 Hz [17]. At the same context, a gradal change in the phase angle of the grid voltage with respect to time is sensed as a change in the grid freqency ( ω = d θ / dt ). Hence a phase-angle jmp of the grid voltage shold be softened at the load terminals and the load shold not sense a freqency deviation ot of the range ±1 Hz. This concldes that most of the loads will not be distrbed by the phase angle jmp of the grid voltage if d θ / dt (or alternatively θ / t ) is kept within ±1 Hz. One Hz is eqivalent to a change of the phase angle by 2 π radian (36 o ) every second. Conseqently, θ / t = 2π (2.27) From (2.27), the reqired time by the SPLL to reach its steady state can be obtained as a fnction of the phase angle jmp θ : t = θ / 2π (2.28) From the basic control theory, the settling time of a first order system is approximately five times the time constant of the system [32]. Ths, the time constant of the simplified SPLL is calclated as: τ = (1/ 5) t = θ / 1π (2.29) SPLL To be able to se this criterion, the discrete transfer fnction of the simplified model of the SPLL, G ( z) in (2.26) is transformed to the continos time sing the bilinear SPLL transformation: z ( 1+ st )/( st ) =. The continos system is obtained as s 1 s θ ( s) 1 sts / 2 GSPLL( s) = = θ ( s) s( ( 1 KP-PLLTs / 2) / KP-PLL ) + 1 (2.3) The time constant of the system in (2.3) is τ SPLL = ( 1 KP-PLLTs / 2) / KP-PLL (2.31) Comparing (2.29) and (2.31) gives the proportional gain that satisfies the identity (2.28). 2 (2.32) KP-PLL = θ / 5π + T ( ) s It can be noticed from (2.32) that the proportional gain of the PI controller depends on the sampling time as well as the maximm expected phase angle jmp. 39

40 2.7 PHASE LOCKED LOOP FOR STATIC SERIES COMPENSATOR It has been shown that voltage dips in the transmission systems reslt in a phase-angle jmp of ± 5 o, while p to 6 o phase jmp can occr de to falts in the distribtion systems [18]. Considering the maximm phase angle jmp that can occr, -6 o (-π / 3), the proportional gain in this case is obtained by sbstitting θ by π / 3 in (2.32), which yields ( 1 ) K = 3 + T (2.33) P-PLL / Tning Second Order SPLL To tne the second order system of the SPLL represented in (2.26), the pole placement techniqe can be sed. The poles of the SPLL transfer fnction in (2.26) are the zeros of the polynomial: ( K T 2) z + T ( K ) P ( z) = z + P-PLL s s I-PLL K (2.34) P-PLL Assming that the poles of G ( z) have the general form: SPLL s z = ρ e ± jϑ (2.35) jϑ jϑ then the general form of the denominator polynomial of G ( z) is ( z ρ e )( z ρ e ) ; 2 ( 2ρ cos( ϑ ) + 2 g z) z ) SPLL P ( = z ρ (2.36) Comparing (2.34) and (2.36) yields K P-PLL = ( 1 ρ cos( ϑ) ), K I-PLL = KP-PLL + T ( ρ 1) (2.37) s Ts Selecting the vales of ρ and ϑ determines the poles of the system and hence its performance. The performance of the SPLL shold be slow and not exhibit an overshoot to avoid power oscillations between the SCC and the grid. Ths, the poles are preferably located close to the real axis. Conseqently the angle ϑ can be assmed zero, which yields ( / T )( ) 2 K = 1 ρ, K = K T / 4 (2.38) P-PLL 2 s I-PLL If ρ =., the SPLL performs as a deadbeat controller and the calclated phase angle is obtained after two sampling periods. As ρ approaches nity, the performance gets slower. To satisfy that the settling time of the SPLL shold be 1/6 second (for a phase jmp of 6 o ) to obtain the desired performance for most of the loads, the poles shold be placed close to nity in the real axis of the z plane bt the stability limit shold not be reached CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID P-PLL s Control of active and reactive powers It has been shown that by sing the vector control, the active and reactive powers can be controlled independently [41]. The athors of [41] gave the formla of active and reactive power (for the shnt-connected VSC) in the stationary reference (ab ) frame as: 4

41 2 SYSTEM DESCRIPTION AND DEVELOPMENTS pinj α β iα = qinj β α iβ (2.39) For series-connected VSC, the expression in (2.39) changes to: pinj iα iβ α = qinj iβ iα β (2.4) In the synchronos reference frame, the active and reactive power are estimated as: pinj iq id q = qinj id iq d (2.41) For a nity power factor operation i.e. i d =, ths active and reactive power expressions are redced to: p = i (2.42) inj inj q q q = i (2.43) d q The voltage components q and d represent the components of the injected voltage cq and cd when applying (2.42) and (2.43) to the case of the SSC. Also, the crrent components i q and i d represent the components of load/grid crrent i gq and i gd. For a fast tracking control, the actal voltage component cq / cd can be approximated to its reference * cq / (2.42) and (2.43) become: inj * cq gq * cd. Hence p = i (2.44) q = i (2.45) inj * cd gq From (2.44) and (2.45), it is clear that the active and the reactive powers can be controlled separately by controlling * cq and * cd, respectively. Conseqently, the amont and the direction of the active power flow between the SSC and the grid are controlled by the vale and the sign of * cq. Also, the amont and the direction of the reactive active power flow * between the SSC and the grid are controlled by the vale and the sign of cd Charging Control of Energy Storage Operation Modes of SSC Before discssing the charging control algorithm of the Energy Storage Capacitor (ESC), the operation of the SSC is described and divided into for modes, according to the state of the valves of the VSC, the thyristors thy (shown in Fig.2.22) and the switching pattern. These modes are: Nll, Self-charging, Blocking, and Compensating modes. Nll mode: In the nll mode, all the valves (as S in Fig.2.22) are off and the VSC behaves as a diode rectifier. The ESC is charged if i ntil another mode is activated. g 41

42 2.9 CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID Self-charging mode: If the diode rectifier is not sed to charge the ESC, the self-charging mode can be sed. Blocking mode: In the blocking mode, the dc voltage is blocked by trning on the pper three valves and trning off the lower three valves of the converter legs, or vice versa. The thyristors thy are trned on to bypass the SSC. Compensating mode: When the SSC detects a voltage dip/swell, the compensating mode is activated. The reference of the injected voltages is calclated by the DVC. The bypass thyristors thy are trned off and the SSC starts to mitigate the dip/swell. Self-charging Techniqe By the self-charging techniqe, it is meant that the VSC of the SSC itself is sed to charge the ESC. Doing so implies that some active power is drawn from the grid into the VSC. When the grid voltage is 1 % of its nominal vale, the control algorithm of the SSC is adapted to control the load voltage sch that the reqired active power can be extracted from the grid and fed into the ESC. An illstrative diagram is given in Fig.2.22, where the direction of the VSC crrent is into the VSC instead of ot the VSC, as in the case of voltage dip compensation. The idea with the self-charging mode is to inject a small voltage component and ths draw a small active power from the grid to charge the ESC. The injected voltage shold be independent of the voltage level of the ESC. This is achieved by generating the proper reference to the plse width modlator. To draw an active power from the grid, the injected voltage mst have a sign sch that dring the charging of the ESC, the active component of the load voltage ( Lq ) will decrease. g + i g inj + L 1 % i D (1-x)*1 % x : Charging Factor x = -.5 S C dc + dc dc t Fig Illstrative diagram to explain self-charging techniqe. 42

43 2 SYSTEM DESCRIPTION AND DEVELOPMENTS Nevertheless, this decrease shold be limited and made so that it does not case problems to the load. In order to charge the ESC and not distrb the load dring the charging process and at the same time to employ the VSC of the SSC, the self-charging is realized with two alternatives: 1) the phase angle of the load voltage is kept constant; 2) the phase angle of the load voltage is allowed to jmp dring the charging of the ESC. Constant phase-angle techniqe To ensre a constant phase of the load voltage, the d- and the q-components of the injected voltage are set sch that: where * cd, * cq, * Ld, and * cd * cq * * ( j ) + j = x + (2.46) Ld Lq * Lq are the d- and the q- references of the injected voltage and the load voltage, respectively. In (2.46), x is the charging factor and it can take a vale in the range.1 to.5 to meet the reqirements that the load voltage drop dring the charging shold be accepted. This means that the load will sense a voltage dip of 95-99% dring the self-charging mode, withot phase angle jmp. The physical meaning of the charging factor x is explained via the example: If the stored energy in the ESC is sed to compensate for a 5 % voltage dip with dration of 1 s, the charging of the capacitor will last 5 s if the allowed voltage drop of the load is 1 %. If the allowed voltage drop of the load is 5 %, the charging will last 1 s. Phase-angle jmp techniqe To keep the load voltage magnitde constant, a phase-angle jmp is allowed in the phase of the load voltage. In this case, active power is drawn from the grid while the VSC injects reactive power. Ths, the magnitde of the load voltage is constant at any time. This is achieved by setting the reference for the VSC to be as in (2.47). * = x cq * * dq 2 * dq 2 cd ( L ) ( L x) = (2.47) * 2 * 2 where L = ( Ld) + ( Lq) is the magnitde of the load voltage in the dq-reference frame. Bt before the self-charging mode can be sed, the dc voltage mst reach a desired vale in order to compensate for the injected voltage calclated by (2.46) or (2.47) and the voltage drop across the LC-filter withot having overmodlation. For instance, the dc voltage has to reach.2 p before the self-charging mode can be applied. This.2 p voltage is realized by applying the nll mode. To conclde, the self-charging techniqe can be smmarized as follows, where a state flag BLOCK is sed to distingish the for operational modes: * dq 1. The VSC is set to the nll mode ntil the dc-voltage reaches 2 % of the stand-by vale (BLOCK = ). 2. The self-charging mode is activated ntil the dc-voltage reaches its stand-by vale (BLOCK = 3). 43

44 2.9 CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID 3. When the desired dc voltage is reached, the blocking state is initiated (BLOCK = 1). 4. In the case of voltage dips in the grid, the injected voltage is determined according to the DVC algorithm (BLOCK = 2) and the thyristors thy are switched off Compensation Strategies To restore the load voltage to its pre-dip conditions, the SSC shold inject some amont of active power. Normally, this active power is obtained from the ESC. The size of the ESC is a limiting factor for the SSC to be able to compensate for deep and long-dration voltage dips. If the amont of the injected active power can be minimized, the cost and volme of the ESC is redced. On the other hand, the minimization of active power shold not affect the waveform of the restored load voltage. The needed amont of active power depends on many factors sch as: 1) voltage dip characteristics (magnitde, dration and phase jmp); 2) the load characteristics sch as the rated power and the power factor. Becase the voltage dips are stochastic, the SSC calclates the missing voltage (amplitde and angle) and injects this voltage in order to maintain the load voltage constant. Of corse, this is achieved within the ratings of the SSC. If the missing voltage amplitde is beyond the rated voltage of the SSC, the SSC injects the maximm voltage bt in this case the load voltage will not be restored to 1 p. Ths, the injected voltage magnitde shold not exceed the SSC rated voltage. Conseqently, three main factors shold be taken into accont: 1) minimization of active power; 2) keeping the injected voltage within the rating of the SSC; 3) smoothing the waveform of the load voltage when applying a phase angle jmp. In order to optimize the performance of the SSC, for different compensation strategies are stdied: 1) Voltage Difference Compensation; 2) In-Phase Compensation; 3) Phase Advance Compensation; 4) Progressive Phase Advance Compensation. Voltage Difference Compensation By the Voltage Difference Compensation (VDC), it is meant that the injected voltage vector c is estimated by sbtracting the grid voltage vector g from the reference of the load voltage vector * L as depicted in Fig Conseqently, the load voltage is restored to its pre-dip magnitde and its phase is nchanged. From the power qality point of view, this is the best compensation strategy. In Fig.2.23, the load crrent vector is taken as the reference vector, which coincides with the q-axis. φ is the angle of the load voltage vector and also the power factor angle. δ is the angle of the grid voltage vector, or alternatively the phase angle jmp dring the dip. With these arrangements, the q-component of the injected voltage represents the injected amont of active power in p. The d- and q-components of the injected voltage are calclated as: * = sin( φ) + sin( δ ) cd L g c 2 cd cq 2 cq = * L cos( φ) * 2 L 2 g g cos( δ ) * 2 L g = + = + cos( φ δ ) (2.48) 44

45 2 SYSTEM DESCRIPTION AND DEVELOPMENTS c φ c g g d φ i L P inj Active Power q d N i N L i Active Power q N Fig Phasor diagram of voltage difference compensation. Fig Phasor diagram of in-phase compensation. From (2.48), it can be noticed that injection of only reactive power ( = cq ) is possible if * L and only if cos( φ) < / cos( δ ). This implies that to inject only reactive power, the g power factor of the load shold be less than the drop of the grid voltage in p when no phase jmp occrs. In-Phase Compensation When applying the In-Phase Compensation (IPC), the load voltage is forced to be in phase with the grid voltage dring the dip. Conseqently, if the phase of the grid voltage jmps a certain angle de to the dip, the phase of the load voltage will jmp by the same angle. Becase the crrent is taken as a reference where the phase angle jmp (δ ) is measred, the load voltage will rotate by an angleφ-δ (as shown in Fig.2.24). If load is assmed to have a constant power factor, the load crrent vector is also rotated by an angle φ-δ. Conseqently, the calclations of the injected voltage and active power is made with the reference to the new crrent axis d N and q N and the amont of active power may be redced as indicated in Fig Becase both of the load voltage and the grid voltage are in phase dring the dip, the amplitde of the injected voltage by the SSC is minimm. The d- and q-components of the injected voltage are: Phase Advance Compensation cd cq = = ( g L ) sin( φ) ( ) cos( φ) L g (2.49) Phase Advance Compensation (PAC) has been proposed in [42, 43] to redce the energy storage size. By the phase advance, it is meant that the injected voltage is synthesized in sch a way that it leads the grid voltage dring the voltage dip. Accordingly, the phase of the load voltage will jmp by a certain angle, which may case problems to some of the loads. Moreover, the effect of the power factor of the load on the PAC has not been stdied, particlarly in the case of constant power factor loads. 45

46 2.9 CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID For constant power factor loads, if the phase of load voltage jmps by a certain angle, the phase of the load crrent will jmp the same angle to keep the power factor angle constant. This implies that to keep the injected active power minimm, the load voltage vector will move in a circle whose radis is eqal to the load voltage magnitde. Conseqently, the operating point when the dip commences (to minimize active power) will not be the same dring the dip and the minimization of active power may not be realized. Moreover, when experiencing a voltage dip associated with a phase angle jmp, there exist a natral phase advance with respect to the grid voltage and this phase advance shold be exploited in the compensation process. Another factor, which limits the applicability of the PAC, is that the magnitde of the injected voltage that shold be limited within the ratings of the VSC. Fig.2.25 displays the phasor diagram of the PAC, where the injected voltage c leads the grid voltage by an angle β. It is shown also in Fig.2.25 that if the VDC is sed, the injected voltage will lead the grid voltage by the natral phase advance angle, β N de to the phase jmp of the grid voltage dring the dip. The angle β N can be obtained as 46 sin( φ) d sin β = δ + tan 1 N cos( φ) d cos ( δ ) ( δ ) (2.5) where d = g / L. Then advancing the injected voltage shold start with the angle β N. Adding an angle β to β N is made to minimize the injected active power: β = β N + β, where β is the advanced phase of the injected voltage dring the dip. De to the phase advance of the injected voltage by an angle β, the load voltage vector rotates by an angle θ. This rotation angle is calclated as: { sin( β )} + δ φ θ = β sin 1 d (2.51) In this case, the injected voltage d- and q-components are: cd cq = sin( φ) + sin L = cos( φ) cos L g g ( δ θ ) ( δ θ ) (2.52) To illstrate the significant effect of the power factor angle ϕ on the injected active power and the voltage magnitde, the variables obtained by (2.48), (2.49) and (2.52) have been calclated for different vales of ϕ and the reslts of are displayed in Fig.2.26 and Fig The maximm injected voltage and active powers are assmed.5 p of the load voltage and rated power. Fig.2.26 illstrates the relation between the reqired active power verss ϕ. In Fig.2.27, the amplitde of the injected voltage is drawn as a fnction of ϕ for the three compensation strategies. The considered voltage dip has a magnitde of.7 p and its phase jmps 3 o. The phase advance angle sed here is π/4. It is noticed from Fig.2.26 and Fig.2.27 that for very high power factors loads (greater than.98), the IPC minimizes both the active power and the injected voltage magnitde. As the power factor decreases (ϕ increases), the reqired active power decreases for all of the three strategies and the PAC ensres that the SSC will inject the minimm amont of active power. On the other hand, the injected voltage magnitde increases as ϕ increases in the case of the PAC and it is independent on ϕ in the case of the IPC.

47 2 SYSTEM DESCRIPTION AND DEVELOPMENTS.5 θ * N L g * L c β β N N q Active Power [p] d d N δ i L Active Power q Φ [Deg] Fig Phasor diagram of phase advance compensation. Fig Injected active power in case of VDC (solid), IPC (dashed) and PAC (dotted). Injected Voltage Mag [p] Φ [Deg] Active Power Φ increases β [Deg] Fig Injected voltage magnitde in case of VDC (solid), IPC (dashed) and PAC (dotted). Fig Injected active power by applying PAC verss the advance angle. It is worth to mention that the amont of active power is also a fnction of the advance angle β as shown in Fig.2.28 in the case of PAC. From Fig.2.28, it can be conclded that there is an angle β that reslts in minimm active power and if the phase advance is frther increased the injected active power will not be minimm. It is also shown that for low power factor loads, the minimm active power cold be negative. This implies that the storage of the SSC will be charged dring the dip. Progressive Phase Advance Compensation Applying the PAC cases the phase of the load voltage to jmp dring the dip. Some of the loads may be distrbed becase of the phase jmp sch as the dc drives and indction motors. To overcome the problems associated with the phase angle jmp, the Progressive Phase Advance Compensation (PPAC) has been proposed [43]. The strategy is based on making the phase advance of the injected voltage progressively in sch a way that the load will not sense a large phase-angle jmp. This can be achieved either by the proper selection of the gains of the Phase Locked Loop as presented in [44] or by dividing the phase advance angle β into small steps. After the dip, the phase advance cased by this strategy shold be removed by applying small backward steps. 47

48 2.9 CONTROL AND OPTIMIZATION OF ENERGY FLOW BETWEEN STATIC SERIES COMPENSATOR AND GRID Proposed Control Algorithm to Optimize SSC Performance From the power qality point of view, the VDC is the best strategy. Bt this is in contrast to the energy saving principle. From the energy saving perspective, the PAC is excellent bt it reqires the injection of higher voltage magnitde. Ths, the proposed control algorithm ses the VDC at the dip start and then applies the PPAC in order to minimize the injected active power. Application of the PPAC is done after checking the injected voltage magnitde and comparing it to the rated voltage of the SSC. The proposed algorithm is based on the doble vector control algorithm presented in Section 2.5 to obtain a fast and improved transient performance. A flow chart of the proposed algorithm is shown in Fig It is noted that the different compensation strategies are employed by the algorithm to satisfy the reqirements sch as: 1) minimm injection of active power; 2) keeping the injected voltage magnitde jst below the maximm allowable voltage by the SSC; 3) improving the continity of load voltage waveform. δ β, N θ, U id, U, iq U i U i U i_max β β, N θ, U id, U, iq U i Fig Flow chart of proposed controller to optimize performance of Static Series Compensator. 48

49 2 SYSTEM DESCRIPTION AND DEVELOPMENTS 2.1. STATIC SERIES COMPENSATOR AS AN ACTIVE FILTER Voltage Harmonics The harmonic contamination has become a problem to sensitive loads. The effect of harmonic distortion on eqipment and power system operation is docmented in many textbooks and literatre sch as [6,7,8,9]. Ths to garantee the operation of sch loads, these harmonics shold be filtered ot from the spplied voltage. The traditional response to mitigate harmonics is the se of passive filters. Passive filters provide either a lowimpedance path or a high-impedance block to harmonics [9]. However, passive filters have some shortcomings sch as: dependence on the sorce impedance; resonance between the passive filter and the sorce impedance; not being able to adapt to the changes of the load conditions. De to the shortcomings of the passive filters, the active filters have been proposed [41]. Instead of providing impedance paths to crrent/voltage harmonics, active filters inject the same magnitde of the harmonic crrent/voltage with an opposite direction to cancel ot the harmonics at the selected node (either load terminals or the point of common copling). It has been proposed to extend the capability of the SSC to compensate for grid harmonics by selective harmonic control in steady state operation [45]. To be able to reglate the load voltage at the desired voltage and filter ot harmonics, the fndamental voltage component as well as the harmonic contamination of the grid voltage shold be accrately detected. Hence, any employed control algorithm shold perform the following tasks satisfactorily: 1) detect the start and the end of the voltage dip; 2) separate the fndamental component of the measred voltages and crrents; 3) estimate the harmonic voltage that shold be injected. To satisfy those reqirements, this thesis proposes a moving average filter to detect the fndamental component of the grid voltage while sing the DVC algorithm to improve the transient performance of the SSC. A selective harmonic compensation strategy is applied to filter ot the grid harmonics Moving Average Filter The idea behind applying a moving average filter (MAF) to detect the fndamental component of the measred signals is based on the fact that the harmonics are transformed into oscillations in the synchronos reference (dq) frame. In the dq-frame, if the voltage is sinsoidal with only the nominal freqency, this voltage appears as a dc voltage. In the presence of harmonics, the voltage appears as a dc component bt sperimposed with oscillations whose freqency depends on the order of the present harmonic and the nominal freqency. An illstrative diagram for the principle of the MAF is shown in Fig.2.3. The analoge form of a MAF for an inpt signal x is given as in (2.53). This filter calclates the mean vale of the inpt signal in the time period from t-t to t, where T is the window width. 1 x ( t) = x( t) dt T t t T (2.53) 49

50 2.1 STATIC SERIES COMPENSATOR AS AN ACTIVE FILTER x dq Moving Average x dq MA Fig.2.3. Principle of sing moving average filter. To realize a MAF as a part of a discrete control algorithm, the inpt signal is sampled N times in the period T and the form given in (2.53) is modified as in (2.54): x( k) = k ( ) = 1/ N j= k N + j x( j) 1 (2.54) Althogh the formla given in (2.54) is easy to implement in a digital controller, it is comptationally expensive. An alternative formla, which is not comptationally expensive and also easy to implement is given in (2.55): x ( k) = x( k 1) + { x( k) x( k N) }/ N (2.55) where x(k-n) is the inpt signal bt it is delayed by N samples. The formla in (2.55) leads to obtain the transfer fnction of the MAF as: x( z) = x( z) N 1 z 1 N N z z N 1 (2.56) The freqency response of the transfer fnction of the MAF is shown in Fig.2.31, where a half-cycle window is applied with a sampling freqency of 5 khz and fndamental freqency of 5 Hz. It can be seen from Fig.2.31 that the gain is db for freqencies p to 3 Hz. For freqencies, which are mltiples of 1 Hz, the gain is very low (-14 db). These freqencies are the freqencies de to the dominant harmonics (5 th, 7 th ) in the dqframe. It can also be seen that the phase of those freqencies is zero Resonant Filter The se of resonant filters has been implemented to selectively compensate harmonic crrents by active filters [46,47]. They can be applied to mitigate harmonic voltage distortion by the SSC. The idea is to implement a filter, which has particlar characteristics. Gain [db] Phase [Deg] Freqemcy [Hz] Freqemcy [Hz] a) b) Fig Freqency response of half-cycle window moving average filter: a) gain, b) phase. 5

51 2 SYSTEM DESCRIPTION AND DEVELOPMENTS These characteristics are: low gain for all freqencies apart from the selected freqency; no phase shift at the selected freqency. In the continos time domain the transfer fnction of sch filter is: G( s) K ω ( s + ω ) f c c = s + 2ω cs + ωc + ω (2.57) n where: K f is the filter gain; ω n is the freqency of the selected harmonic in rad/s; ω c is the band freqency in rad/s to improve the transient performance of the filter. K f is designed to obtain a nity gain at the selected freqency (ω n ). In order to obtain that, the gain K f shold be eqal to 2ω c nder the assmption that ω n >>ω c. The filter in (2.57) shold be discretized to be a part of a discrete control algorithm, reslting: G( z) C z + C z + C = 2 (2.58) C4z + C5z + C6 The coefficients C 1 to C 6 are constants for one selected harmonic freqency. Eqation (2.58) can be easily implemented in the control algorithm. Fig.2.32 illstrates the freqency response of the 5 th order resonant filter, where it is shown that the filter gain is db at 25 Hz (5 th harmonic) and very low otherwise. In Fig.2.32, ω n = 157.8; ω c = 2π and K f = 4π Block Diagram of Proposed Controller for Mitigation of Voltage Dips and Harmonics Referring to the DVC algorithm presented in Section 2.5, the inpts to the controller are: the grid voltage dq g ; the injected voltage at the low voltage side of the injecting dq transformer c ; the grid crrent i dq g and the converter crrent i dq. These signals are individally inpt to a MAF. The otpt of the MAFs are the inpts to the basic DVC *abc algorithm to calclate the fndamental converter voltage ( 1 ). At the same time, the *abc reference of the injected harmonics ( H ) is obtained by sing a resonant filter for each individal harmonic that shold be filtered gain [db] phase [deg] Freqency [Hz] Freqency [Hz] a) b) Fig Freqency response of 5 th order resonant filter: a) gain, b) phase. 51

52 2.1 STATIC SERIES COMPENSATOR AS AN ACTIVE FILTER dq g dq c i dq i dq g Moving Average Filter Moving Average Filter Moving Average Filter Moving Average Filter dq g_ma dq c_ma i dq MA i dq g_ma *dq L *dq c DVC *dq 1 dq αβ αβ abc *abc 1 *abc *abc H abc L5 abc L7 abc L11 Resonant Filter 5th Resonant Filter 7th Resonant Filter11th L abc Fig Resonant and moving average filters with doble vector controller to mitigate harmonics. is obtained by passing the load voltage ( *abc H abc L ) to the resonant filters. Here, it is worth to mention that the measrement of the load voltage is not necessary becase the load voltage can be calclated by smming the grid and the injected voltages. After estimating the reference of the fndamental injected voltage and the reference of the injected harmonic voltage, both voltages are added to each other MITIGATION OF VOLTAGE SWELLS AND OVERVOLTAGE PROTECTION Voltage Swells A voltage swell is an increase in the RMS voltage above 1.1 p at the power freqency for dration from.5 cycle to 1 minte [2]. An example of a measred 2% voltage swell for 5 fndamental cycles is depicted at Fig Swells and overvoltages can case overheating, tripping or even destrction of indstrial eqipment sch as motor drives and control relays. Many power qality srveys have been made in order check the load immnity against power system distrbances [48,49]. From those srveys, condcted at North America, it can be stated that the voltage swells are experienced in the power systems locally or remotely. The nmber of voltage swells per year is natrally random bt from the statistics presented in [48], it can be conclded that not less than 165 events/year have been recorded. The dration of the recorded swells varies from one fndamental cycle to 8 hors. A simplified circit diagram for the SSC is depicted at Fig.2.35, where R LF +jx LF is the impedance of the LC-filter indctor and R LT +jx LT is the impedance of the series transformer. The voltage swell is an increase in the RMS voltage of the grid, which implies that the reference of the injected voltage by the SSC is negative becase g is greater than * L. Hence, the direction of active power flow may be reversed and the ESC may be charged. In steady-state basis, the reference of the injected voltage by the SSC is compted as: U inj * L = U = U U (2.59) g 52

53 2. SYSTEM DESCRIPTION AND DEVELOPMENTS From Fig.2.35, the otpt voltage of the SSC can be calclated as: U = U { I ( RLF + jx LF) + I g ( RLT + jx LT) } (2.6) where: R T : resistance of the injection transformer, X LT : leakage reactance of the injection transformer, R F : resistance of the LC-filter, X LF : leakage reactance of the LC-filter I: crrent throgh the LC-filter indctor, I c : crrent throgh the LC-filter capacitor, I g : Load crrent. If the capacitor crrent I c can be ignored, the reference voltage of the VSC is simplified to: U = { U I ( R + R )}- j{ I( X + X )} (2.61) LF LT Eqation (2.61) shows that even in case of a voltage swell, the reference voltage of the VSC may be positive or negative depending on: 1) the characteristics of the voltage swell; 2) the impedance of the series injection transformer and the LC-filter. Being positive means that the SSC is delivering active power to the load and the ESC discharges. If the reference voltage of the VSC is negative, it indicates that the grid is feeding active power to the SSC and the ESC is charged nless the overvoltage protection is triggered. LF LT 1.2 RMS Grid Voltage [p] Time [ms] Fig Example of voltage swell. R F + j X LF R T + j X L T + U I Ic -j X CF I g + U inj Fig Simplified single line diagram of static series compensator in steady state dring swell. 53

54 2.11. MITIGATION OF VOLTAGE SWELLS AND OVERVOLTAGE PROTECTION The phase of the grid voltage may jmp dring the voltage swell and ths becomes either lagging or leading the phase of the load voltage. The amont of active power that can be exchanged dring the voltage a swell with a lagging phase jmp is calclated in p as: P inj = cos( φ) (1 + U ) cos( φ δ ) (2.62) In the case of a voltage swell with a leading phase jmp, the active power is obtained as: P inj = cos( φ ) (1 + U ) cos( φ + δ ) (2.63) where φ: load power factor angle, δ: phase angle jmp of the grid voltage, 1+ U: the voltage swell magnitde. From (2.62) and (2.63), it is noted that the injected active power depends on the load power factor, the voltage swell magnitde and the phase angle jmp of the grid voltage dring the swell. If the phase of the grid voltage does not jmp de to the swell; δ =, the expressions in (2.62) and (2.63) are redced to Pinj = U cos( φ). The energy stored/delivered by the ESC is obtained as: E ESC = Pinjtswell, where t swell is the swell dration. Hence by the aid of (2.62) and (2.63) and the expected dration of the voltage swell, the size of the energy storage can be designed Overvoltage Protection Scheme If the dc voltage of the SSC exceeds a predetermined voltage level, the SSC shold be protected against the overvoltage. This overvoltage protection can be made when the SSC is online or offline depending on the vale of the measred dc voltage. For instance, if the dc voltage reaches a vale in the middle of the nominal voltage and the maximm allowable voltage, the online overvoltage protection shold be triggered. The offline protection is triggered if the dc voltage exceeds its maximm allowable voltage. An illstrative diagram of the zones of the overvoltage protection is depicted at Fig In Fig.2.37, the zone of the online protection is placed between the nominal dc voltage U dc_nom and the predetermined online protection voltage level U on_p. The zone of the offline protection is located between the maximm of the dc voltage U max and the setting of the online protection U on_p. Online protection If the SSC is reqired to be in service dring a voltage swell, the overvoltage protection is realized online by sing a shnt resistor across the dc link together with a dc chopper. A single-phase diagram of the overvoltage protection scheme is shown in Fig The dc chopper is enabled when the dc voltage exceeds a certain voltage level (sch as U on_p in Fig.2.37). This voltage level is determined by the voltage that the SSC valves can withstand de to the voltage swell. If the dc chopper is closed (on-state), the dc resistor dissipates the energy excess in the dc capacitor. In other words, the dc capacitor will discharge thogh the dc chopper and the resistor. 54

55 2. SYSTEM DESCRIPTION AND DEVELOPMENTS Offline protection Offline protection is realized by trning on the thyristor pair thy on the line side of the SSC (Fig.2.36) as well as the pper or the lower IGBTs in each phase leg of the VSC. Trning on the pper IGBTs and trning off the lower IGBT or vice versa interrpts the dc crrent and blocks the dc voltage. It is worth to note that trning on the thyristors only is not sfficient to protect the VSC becase the thyristors will short-circit the injection transformer and the VSC. In this case the energy stored in the capacitor of the VSC will circlate a high crrent throgh the valves of the VSC, which may be dangeros as well Design of dc resistor The resistance sed with the chopper shold satisfy two main reqirements: 1) the discharging process of the dc capacitor to the rated dc voltage shold be made in a reasonable time; 2) the initial discharging crrent shold not exceed the maximm allowable crrent of the chopper. The minimm vale of the resistance is obtained as: R chop _ min = U on_p / I (2.64) disch While the maximm vale of the resistance is obtained as: R chop_max = tdisch /( Cdc ln( U dc_max / U dc_nom)) (2.65) where U on_p : vale of the dc voltage, which triggers the online protection; U dc_ NOM : nominal dc voltage; C dc : energy-storage capacitor; I disch : initial discharging crrent; t disch : discharging time. To clarify the significance of (2.64) and (2.65), a design example is given here. A prototype SSC is nder development (in another project by another PhD stdent) at the Department of Electric Power Engineering, Chalmers University of Technology, Sweden. The relevant data of this prototype is given in TABLE.I. chop + dc i dc g + C dc i g R F L F + i C F + c L dc Voltage [V] U max U on_p Udc_NOM Offline Protection Online Protection Time [ms] Fig Overvoltage protection scheme of static series compensator. Fig Zones of online and offline protection of static series compensator. 55

56 2.11. MITIGATION OF VOLTAGE SWELLS AND OVERVOLTAGE PROTECTION TABLE.I. Prototype SSC nder constrction Converter Model Danfoss VLT 552 [5] U on_p 7 V U dc_nom 6 V I disch 9 A C dc 4.7 mf The discharging time t disch is selected as ½ period of the fndamental freqency (1 ms). This is de to the fact that the switching freqency of the chopper is designed as 5 Hz and the dty cycle is 5%. Ths, the discharging of the dc capacitor is assmed to be complete within one switching cycle of the chopper. Applying (2.64) and (2.65) with the data given in TABLE.I and taking the discharging time t disch as ½ period of the fndamental freqency (1 ms) yields: R min = 7.7 Ω and R max = 13.8 Ω. Here it is worth to mention that the proposed vale of the resistance by the manfactrer [5] is 12 Ω, which belongs to the range R min <R chop < R max.. A resistor of 9 Ω resistance was designed and sed in the SSC prototype given in TABLE.I, which shows the significance of (2.64) and (2.65) SUMMARY OF CHAPTER 2 The operational principle and the design of the Static Series Compensator (SSC) have been described in this Chapter. A Doble Vector Control (DVC) algorithm was developed to mitigate the balanced voltage dips. Then the DVC was modified to cope with nbalanced dips. The capability of the SSC to mitigate voltage swells has been investigated and an overvoltage protection scheme was proposed. Also, the fnctionality of the SSC as a series active filter was stdied and a control algorithm has been developed. 56

57 CHAPTER 3. RESULTS AND ANALYSIS 3.1. INTRODUCTION In Chapter 2, different controllers have been developed in order to mitigate three power qality problems: voltage dips, voltage swells, and voltage harmonics. In order to investigate the performance of the developed controllers, simlations and experiments are made. A simlation model is designed and implemented in the PSCAD/EMTDC package. Experiments are carried ot on a 1 kv SSC prototype in order to show the validity of the controllers. Some of the reslts are presented and analyzed in this Chapter. For the interested readers, all the reslts are given in the inclded papers SIMULATION MODEL The simlation model is composed of three main blocks: 1) power system; 2) load model; 3) model of the SSC. The main parts of the simlation model are displayed in Fig.3.1. All the models are obtained by the defined models in the PSCAD/EMTDC package. The power system is modeled as a voltage sorce behind a finite sorce impedance to simlate the grid performance de to power system events sch as short-circit falts and load switching. Three-different types of loads are involved in the simlation model: static linear; dynamic linear and nonlinear loads. The static linear load is a resistive-indctive and an indction machine represents a model for the dynamic linear load. The nonlinear load is a three-phase diode rectifier. The control of the SSC is realized by a nmber of ser-defined models, which are written sing the FORTRAN langage and linked with PSCAD/EMTDC. Also the pstream loads are modeled and investigated. Capacitor banks and transformers are candidates for the pstream loads.

58 3.3. EXPERIMENTAL SETUP s + Zs + dc S D R F LF c C F Fig.3.1. Simlation model in PSCAD/EMTDC EXPERIMENTAL SETUP The experimental setp of the SSC has been bilt at the Institte of Energy Technology, Aalborg University, Denmark as a part of the PhD work reported in [31]. A single line diagram of the experimental setp is shown in Fig.3.2. The SSC displayed in Fig.3.2 is operated at 1 kv. To obtain a 1kV line in the laboratory, a step-p transformer.4/1 kv and a step-down transformer 1/.4 kv are installed. Data of the system is given in Paper *dq * * C. The reference load voltage is L = Ld + jlq = +j1. p. The SSC was fed with a programmable California Instrments Spply at 38 V, which was then fed into the step-p transformer to create the 1 kv system. A photo of the step-p and the step-down transformer is displayed in Fig.3.4. Three specially made 67 kva.29 kv/2.9 kv singlephase transformers are sed to series connect the voltage sorce converter of the SSC the 1 kv system. The load voltage was stepped down sing step-down transformer to allow tilization of low-voltage linear and non-linear loads. s + Lg R g.4 / 1 kv Y/ g ig i dc i R F L F i + i L L 1/.4 kv / Y dc + + c + C F Fig.3.2. Single-phase diagram of 1 kv static series compensator sed in experiments. 58

59 3. RESULTS AND ANALYSIS IGBTS Filter Fig.3.3. Photo of experimental setp: VSC and LC-filter indctor. Fig.3.4. Photo of high voltage transformers sed to generate 1-kV system. The dc-bs of the converter is charged maximally to 6V sing a nidirectional dc spply, which provides 468 J of energy in the 26 mf of the dc capacitors. An Analog Devices AD2162 floating-point Sharc DSP was sed to implement the developed controllers, with the PWM signal generation for the six IGBT phase-legs (shown in Fig.3.3). The PWM signals were created sing a Siemens SAB 8C167 Micro Controller. The medim voltage spply and load voltages were measred with ABB resistive voltage transdcers. At the low voltage side, the injected voltage is measred by LV 25-P/SP2 voltage transdcer. Also the grid crrent at the low voltage side is measred by LT 2-S/SP44 LEM crrent transdcer GENERATION AND MITIGATION OF VOLTAGE DIPS Generation of Voltage Dips In the simlation model, the voltage dips are generated by switching on impedance to the grond at the Point of Common Copling (PCC), pstream the SSC. This sitation is eqivalent to a remote short-circit falt, which reslts in voltage dips with a phase angle jmp. Experimentally the programmed power spply (California Instrments), was employed to generate balanced and nbalanced voltage dips Mitigation of Balanced Voltage Dips A resistive load of 2 Ω is sed as a linear load and an indction machine: ASEA MK IM (see Paper C) is installed as a dynamic linear load while carrying ot the experiments. Also a three-phase diode rectifier is connected directly downstream the SSC as a nonlinear load. Only, the reslts with the IM are presented in this Chapter. The performance of the SSC with the linear and nonlinear loads is analyzed in Paper C. A 7 % voltage dip is initiated for 5 cycles at the PCC as displayed in Fig.3.5a. The injected voltage is shown in Fig.3.5b and the load voltage is displayed in Fig.3.5c. A zoom on the load voltage at the dip start is shown in Fig.3.5d while a zoom at the dip end is displayed in Fig.3.5e. The reslts confirm the improved transient performance of the SSC compared to like sing phasors [22,23] and vector control withot an inner crrent loop [31]. The speed 59