FIR Filter Design Using The Signed-Digit Number System and Carry Save Adders A Comparison

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1 (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 FIR Filter Design Using The igned-digit Nmber ystem and arry ave Adders A omparison Hesham Altwaijry ompter Engineering Department, King ad University PO Box 578, Riyadh 543, adi Arabia Yasser Mohammad eddiq ompter Engineering Department, King ad University PO Box 578, Riyadh 543, adi Arabia Abstract This work looks at optimizing finite implse response (FIR) filters from an arithmetic perspective. ince the main two arithmetic operations in the convoltion eqations are addition and mltiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniqes shold enhance the addition operation of the filter. The signed-digit nmber system is tilized to speedp addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also sed here to compare its performance to the signed-digit adder. For mltiplication, Booth encoding is sed to redce the nmber of partial prodcts. The two filters are modeled in VHDL, synthesized and place-androted. The filters are deployed on a development board to filter digital images. The resltant hardware is analyzed for speed and logic tilization Keywords FIR Filters igned Digit arry-ave FPGA I. INTRODUTION Digital signal processing (DP) systems employ compter systems to digitally process inpt signals. An example where compter arithmetic is a key factor in optimizing the design is digital filters especially convoltion-based ones. The hardware complexity and processing delay of these digital filters are proportional to a parameter called the filter order, which is highly desired to be large []. These filters have been bilt sing FPGA s [] [3] [4] A fndamental principle in compter arithmetic pon which all the scceeding aspects are based is how vales are to be represented. As all the compting platforms that are sed today for digital signal processing are based on digital electronics, the arithmetic operations they perform shold be handled in a way that is sitable to the natre of the electronics that bild these platforms. The way a vale is represented is called a nmber system. ompters were initially developed to se the binary nmber system (radix-). Althogh, compters se radix-, there have been few nmber systems discssed in the compter arithmetic literatre that are nconventional in terms of representation and operations. ch nmber systems are sed in compters for some special applications. A. The Binary Nmber ystem Binary nmber systems are called positional nmber systems [5]. A general expression for the vale of an n-digit nmber A consisting of digits a n, a n,, a 0, in radix-r nmber system is as follows: A n i0 i a i r In compters, the choice of r is de to electronic circit limitations. When r eqals a constant vale as in the decimal and the binary systems, this is called a fixed-radix nmber system. An observation on the conventional fixed-radix positional representation is that special representations are reqired for signed nmber and that carry propagation in addition, which increases the delay of operations, limits system scalability and adds more complexity to algorithm implementation. B. Unconventional Nmber ystems A common featre of the nconventional nmber systems is redndancy; a positional nmber system is redndant when the nmber of elements in its digit set is greater than r, where r is the radix. In a redndant nmber system, an algebraic vale can have more than one representation. Redndant nmber systems can improve system reliability, increase speed of operations, and provide strctral flexibility. [6] igned digit nmber systems are a positional nmber representation with a constant radix r 3. Each digit of a signed-digit nmber can have one vale of the set { a, a +,, 0,, a, a} [7] [8]. The maximm possible magnitde, a, is set as follows ro a r o for odd radices r 3 re a re for odd radices re 4 o () 48 P a g e

2 (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 8-tap delay line tage tage tage tage tage h[0] h[] h[] h[3] h[4] h[5] h[6] h[7] c 5 c 4 c 3 c c tage tage tage tage Fig.. Basic FIR Filter When a vale is represented with n binary bits, then it will be represented with k n / log r signed digits [9] igned-digit systems have the advantage that the addition time of a mlti-operand adder that is bilt by cascading identical digit adders is constant. A special case in signed-digit representation is for the radix r = and the digit set is {, 0, } where represents. In this case, the representation is called canonic signed-digit (D). Three main properties of the D are that it is irredndant, the nmber of nonzero digits is minimal and mltiplying any two adjacent digits will prodce zero. In the applications that involve mltiple constant mltiplications (MM) as in the FIR filters, sing D garantees the minimal nmber of adders. II. DIGITAL FILTER Filters are signal processing components that are sed to process interfered and corrpted signals. They can be classified to two main categories: analog and digital filters. Filters in these two categories are different in terms of cost, speed, accracy, power consmption and implementation, bt they are similar in the sense that they are both sed to filter signals. A commonly sed method of implementing digital filters is by considering a sbset of the filter s implse response. Filter designed this way are called finite implse response (FIR) filters. The mathematical process sed to get the otpt of a linear system according to its implse response is the convoltion. When a digital signal x[n] is to be processed by a system of implse response h[n], the otpt is the reslt of the following eqation []: y[ n] N k 0 Mlti-Operand Adder h[ k] x[ n k] The above eqation describes how each sample of the otpt signal is calclated. This is an application of the widely sed mathematical operation of the dot prodct, which consists prely of mltiplication and addition. Optimizing the dot prodct does not only serve the FIR filter application, bt also some other applications that are similarly described sch as radar processing, signal correlation and matrix mltiplication. s 5 s 4 s 3 s Fig.. igned Digit Addition A general block diagram of the convoltion process as it is implemented in hardware is shown in Fig. The delay line represents the inversion and shift in the inpt x[n]. The taps of the delay line are mltiplied by the constant vales of h[n]. The wider the delay line, the more accrate the reslts of the FIR filter are. Of corse, this is on expense of more hardware resorces, higher power consmption and higher cost. In order to make the FIR filter performs addition faster, breaking the carry propagation chain in its adders is essential. The two most common techniqes to achieve this are signeddigit addition and carry-save addition. A. igned-digit Addition igned-digit nmber system can perform addition and sbtraction with a limited propagation of carry. This featre makes the adder's delay independent of the operand length which implies less delay. The carry propagation can go as far as one position to the left. The sign of the nmber is implicitly expressed in the digits and no special representation is needed for this prpose. A block diagram of a signed digit adder is depicted in Fig.. The vales shown in the figre are determined in [0] B. arry-ave Addition arry-save addition is one of the carry-propagate free methods of addition []. arry-save adders (A) are mainly sed when adding three operands or more. As are bilt sing (3, ) conters in a manner that prevents carry propagation. The term (3, ) conter is an alternative name for a fll adder becase it receives three bits of the same weight and otpts two bits representing the nmber of ones in the three-bit inpt. In the ordinary carry-propagate adders, the least significant bit of the otpt of the (3, ) conter is the sm while the most significant bit is the carry that propagates to the left. Therefore, adding mlti-operands sing a A will reslt in a vector of the sm bits and another vector of carry bits. This two-vector reslt invites the need for a carrypropagate adder to add these two vectors to get a single reslt in the normal binary representation. III. IMPLEMENTING IGNED DIGIT FILTER For the prpose of implementing a high-speed FIR filter, the arithmetic advantages of the signed-digit nmber system have been exploited to enhance the filter performance. This section is an elaboration to or work in []. It discsses the adder and the mltiplier design and implementation. 49 P a g e

3 (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 mltiplicand (M) Partial Prodct Generation Fig. 3. igned Digit Mltiplier A. Digit et and Encoding Partial Prodcts Mlti-Operand igned-digit Adder (Tree strctre) election lines (M, M and M) The signed-digit nmber system sed in this work is in radix-. Therefore, the allowed set of digits is {, 0, } where represents. As there are three possible digits in this set, two bits are needed to encode each digit. There are two commonly sed encoding methods sed to encode the digits of a nmber in the signed-digit representation [0] [3]. In the first method, each digit is assigned a s complement nmber representing the algebraic vale of that digit. In the second encoding method, each digit of the nmber in signed-digit representation is assigned a -bit code x sch that the sm of the two bits is eqal to the vale of that digit. If the high bit holds a negative sign, the low bit holds a positive sign and vice versa. That is, the vale can be determined either as x + + x or as x + x +. The second encoding method makes converting signed-digit nmbers to s complement nmber easier [0]. Additionally, sign inversion of a digit is simply swapping the high and the low bits. Therefore, in this work the second encoding method with the vale determined as x h x l is sed. A igned digit adder can be implemented as a straight forward implementation into an FPGA by means of sing lookp tables (LUT). However, the synthesis of this implementation reslts in a very poor tilization for the FPGA logic elements. Alternatively, the adder can be implemented sing logic gates based pon eqations presented by [4]. B. igned Digit Partial Prodct Generation mltiplier (R) Partial Prodct election Prodct FIR filters involve mltiplying the inpt samples with the filter kernel coefficients. Ths, improving the filter mltipliers will significantly improve the filter performance. Mltiplication is done two steps:. Generating the partial prodcts.. Accmlating the partial prodcts. The nmber of partial prodcts needed for the mltiplication can be redced by sing Booth s algorithm [5], however this encoding is performed serially, it can be done in parallel sing the modified Booth encoding [6]. Booth- encoding is the most commonly sed method. However, provides more redction for the non-zero digits bt the existence of the hard mltiple 3M forms an obstacle when applying encoding. An efficient soltion for the hard mltiple 3M was proposed in [3] by exploiting the advantages of the signed-digit nmber system. The mltiplier proposed accepts two operands in s complement representation and gives their prodct in signed-digit representation. The digit coding method sed in that work is the sm-of-bits in the form x + + x. The signed-digit encoding method is tilized to determine the hard mltiple 3M as 4M M. Finally, the partial prodcts are added p to get the final prodct. This step reqires a signed-digit mlti-operand adder. Binary tree architectre is sed to bild the mlti-operand adder sing two-operand signed-digit adders. The block diagram of the mltiplier that is designed in this work is shown in Fig. 3. igned Digit Filter After the mltiplier and the mlti-operand adder are already implemented, the FIR filter jst needs to be assembled. The delay line has been implemented as an array of registers. ince the otpt of the final adder is still in signed-digit representation, a converter had to be added to convert the reslt to s complement format. In this work, the converter is simply a carry lookahead adder that adds the positive and the negative parts of the signed-digit nmber. onverting an n- digit signed-digit nmber X is performed as follows: X = (x +, x ) n (x +, x ) n (x +, x ) (x +, x ) (x +, x ) 0. The positive part is XP = x + n x + n x + x + x + 0. The negative part is XN = x n x n x x x 0 The s complement representation is Y = XP + XN. A scalable and parameterized design has been highly considered. Ths, when the FIR filter is assembled, the filter order and the sample width are defined as design generics in the VHDL code sch that the generated filter architectre meets the intended filter parameter. The block diagram of the signed-digit FIR filter implemented in this work is depicted in Fig. 4. If the sample width is W and the filter order is N, the log N. filter otpt sample will be of width W Inpt sample Register 0 Fig. 4. igned Digit FIR Filter [] IV. Register Register IMPLEMENTING ARRY AVE FILTER In this section, another method of breaking the carry propagation chain is reported. That is by sing carry-save addition (A) []. As are bilt sing (3, ) conters in a manner that prevents carry propagation. The term (3, ) conter is an alternative name for the fll adder becase it Register N- h0 h h hn- N-ample Delay Line Mlti-Operand igned-digit Adder (Tree strctre) Register N- hn- LA Otpt ample 50 P a g e

4 (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 receives three bits of the same weight and otpts two bits representing the nmber of ones in the three-bit inpt. In A instead of propagating the carry bits to a higher position, these carry bits are kept and added sing later stages of the A. arry-save adders are sed in FIR filters to add the partial prodcts of the mltipliers and to calclate the final reslt of the filter. A. arry-ave Addition An efficient way of designing a carry-save adder to achieve fast performance is by designing it based on a 3- operand carry-save adder. A k-operand A adder (where k > 3), is constrcted ot of several blocks of 3-operand As [7] [8]. This k-operand A cold be implemented in two common ways: cascade or tree. The cascade strctre accepts one new operand at each level except at the first level where three new operands are accepted. The nmber of levels in this strctre is more than the nmber of levels in the tree strctre, which implies more delay. However, the cascade strctre remains a preferred option sometimes de to its reglar layot, which implies more simplicity in the VLI design. On the other hand, the tree strctre, which is known as the Wallace tree [], accepts as many operands as possible at the first level. The following levels are sed to add the sm and the carry vectors in addition to the operands remaining from the first level, which mst be at most two remaining operas. When sing the tree strctre to bild a A, the nmber of levels will be less than the cascade strctre. [9] B. arry-ave Filter The A and Booth- mltiplier are the fndamental blocks of the carry save FIR filter. As in the signed-digit case, the FIR filter is bilt by assembling these blocks with some extra logic for the delay line, which is an array of registers, and the converter, which is a carry lookahead adder. The conversion from the carry-save to the s complement format is performed by adding the sm and carry vectors. The filter is illstrated in Fig. 5 Inpt sample Register 0 Register Register Fig. 5. arry-ave FIR Filter V. TETING AND VERIFIATION The implementation of the different configrations of the FIR filters have been tested fnctionally sing test benches written in VHDL. Those test benches covered the top-level Register N- h0 h h hn- Booth- Booth- N-ample Delay Line Booth- Booth- Mlti-Operand arry-ave Adder (Tree strctre) Register N- hn- Booth- m arry LA Otpt ample architectres along with the sb-components throghot the design hierarchy. Moreover, the filters have been synthesized and mapped into an FPGA in order to verify their fnctionality on real hardware for image processing. This experiment is reported briefly in [] while described in more details in the following. ch applications are challenging in the sense that two dimensional (D) FIR filters are needed instead of the one dimensional (D) filters available in hand. A D FIR filter applies the D convoltion eqation: y[ m, n] M N i0 j 0 x[ i, j] h[ m i, n j] A sample of an image signal is in indexed by two vales: m and n indicating the row and colmn position of that sample respectively. ince the filters implemented so far in this work are D, they are instantiated in parallel to bild a D FIR filter of order M-by-N sch that each one of the M D filters performs convoltion operation of order N as illstrated in Fig.6. The kernel h of each filter is assigned as one row of the D kernel. The D filter of order -by- that is designed in this work is intended to smooth ot the sharp edges of an inpt image by averaging ot each pixel with its neighbors sch that the otpt image is a blrred version of the original one. o, this is a moving average filter, which is a low-pass filter. After blrring the image, the reslt is sbtracted from the original image in order to extract the image edges and cancel ot the constant regions. In this work the filter size is -by- and the filter kernel is h The above described process is implemented on Altera yclone II tarter Development Board. The image sorce is a normal personal compter. The interface between the FPGA and the compter is the serial port. The reslts are depicted in Fig. 7 x[, n] x[, n] x[, n] x[m-, n] FIR filter FIR filter FIR filter FIR filter M- Fig. 6. -D FIR filter [] Kernel = h[m-, ] to h[m-, N- ] Kernel = h[m-, ] to h[m-, N- ] Kernel = h[m-, ] to h[m-, N- ] : : Kernel = h[, ] to h[, N- ] + x[m, n] 5 P a g e

5 (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 (a) Original image (b) Blrred image (c) btracted image Fig. 7. Edge Extraction sing FIR filter [] VI. YNTHEI REULT The two FIR filter designs have been implemented in a scalable and parameterized manner by exploiting the generality featres of VHDL. The sample width W and the filter order N are the two generics of the two filters. Recalling that the major problem that is handled in this work is the carry propagation delay, different vales for W, which is directly affecting the carry chain, shold be examined. ince we are talking abot FIR filters, the order N is also worth examining. Three precision levels of W are selected: low precision, medim precision and high precision where W is eqal to, 4 and 48 bits respectively. These vales of W are selected becase when is applied on them, the nmber of generated partial prodcts is a power of, which redces the complexity of the mlti-operand adder when bilt as a binary tree. In fact, there is also some attractive and practical advantage for choosing sample widths of and 4 bits. That is, most of the commercial analog-to-digital converters (ADs) that are sed today electronic systems are -bit wide and most of the adio codec components sed in media systems are 4-bit wide. For the vales of N, arbitrarily chosen vales of 6, 3 and 64 samples have been considered. With two filter types, three precision levels and three filter orders, there are 8 different FIR filters to be synthesized. The 8 filters have been synthesized and place-and-roted sing Qarts II software. The target FPGA is Altera tratix III EP3L340 [0]. The timing and hardware reslts of the place-and-rote process are targeted for analysis. To get accrate timing reslts, the delay from the primary inpt to the primary otpt of the filter shold be measred. In fact, some software design tools measre the delay starting from the FPGA pin to which the primary inpt is assigned and ending at the pin to which the primary otpt pin is assigned. This method of measring delay is not accrate when comparing two or more designs becase there will be some extra roting delay between the pins of the primary ports. This roting delay is dependent on where the tool places and rotes the design and hence is not reglar. To avoid this problem in this work, the primary inpt and the primary otpt of the filter are latched. Once the tool figres ot that there is some logic between two registers, it will calclate the maximm clock freqency fmax allowed for this design. The reciprocal of the freqency (/ fmax) is the propagation delay of the logic between the two registers, pls some seqencing overhead which is common for all designs. Ths, the presence of this extra delay in the comparison is fair. The place-and-rote reslts for delay and hardware are collected and analyzed. These reslts are discssed in the following figres. The delay data collected for the 8 filters are smmarized in Fig.8. An observation on the chart is that the latency in both filters is proportional to W and N. The jstification of this observation is that the sample width W directly affects the nmber of partial prodcts that is generated in the Booth mltipliers, which in trn increases the nmber of levels in the mlti-operand adder inside the mltiplier. Likewise, the vale of N affects the nmber of levels in the mlti-operand adder that generates the final filter reslt. This increase in the adder levels, which is proportional to W and N, reslts in a larger latency. It is interesting to notice that the delay of the two filters is not eqally proportional to W and N; it is highly proportional to W while slightly proportional to N. This is, in fact, de to the delay introdced by the carry lookahead adder that acts as a converter at the last stage in both filters. A LA is a carry propagate adder and it is expected to be highly tied to W. When this LA has been separately analyzed, it has been fond that it is responsible for abot 8 % of the overall filter delay. This explains why W has more inflence on the filter delay than N. Another observation is that the signed-digit filter is always faster than the carry-save filter. This improvement in filter performance needs more analysis in order to see how the improvement behaves with respect to the design parameters and how significant it is. Fig. 9 depicts the ratio of the signeddigit filter delay over the carry-save filter delay. learly, the delay improvement is very slight since the chart indicates that signed-digit filter performs between. and. times faster than the carry-save filter. The speedp is almost constant regardless of the vales of W and N ns W= Fig. 8. FIR filter Delays P a g e

6 Improvment percentage FPGA percentage (IJAA) International Jornal of Advanced ompter cience and Applications, Vol. 4, No., 03 Fig. 9. Ratio of - to A FIR filter delays W= Fig. 0. Logic Utilization X W= W= Fig.. Logic Utilization Percentage The data of the logic tilized by the 8 filters is also collected and analyzed. The place-and-roting logic tilization reslts are smmarized in Fig. 0. While Fig. shows the percentage of hardware redction in the signed-digit filter with respect to the carry-save filter. It is logical and expected to see that the hardware of the two filters grows as the vales of W and N increase. It is noticeable that the hardware tilization when W = bits, regardless of the vale of N, is almost the same for the two types of filters. With higher vales of W, the signed-digit filter has an advantage. The case of having the signed-digit filter being smaller than the carry-save filter despite that the added complexity of the signed-digit adder is may by the significance of Booth mltipliers in the filters since most of the filter size is occpied by them. Booth mltiplier efficiency in saving hardware and time becomes more significant and appreciated when the mltiplier gets bigger. This is what makes the logic difference more notable when W is eqal to 4 and 48 bits. From Fig., the signeddigit filter is between 30 % and 40 % smaller than the carrysave filter for W = 48. This might seem conterintitive. However, this cold be jstified by amont of mltipliers sed, and the fact that the redction from Booth to Booth 3 is the case for this redction in size. VII. ONLUION In this work, FIR filter design and implementation have been approached from arithmetic perspective. The signed-digit and the carry-save arithmetic techniqes have been exploited to redce addition time. Booth encoding was sed to speedp mltiplication. The athors designed, simlated and tested a high-speed FIR filter sing the signed digit nmber system. The first part of work is the design and implementation of the FIR filter sing the signed-digit nmber system and encoding to improve the filter adders and mltipliers respectively. The implementation of the signed-digit twooperand and mlti-operand adders has been discssed. In implementation, it has been shown how the signeddigit nmber system helps in generating the hard mltiple 3M. The other part of this work is the design and implementation of an FIR filter sing carry-save addition and Booth- encoding to improve the filter adders and mltipliers respectively. The hierarchical design of As of several sizes has been reported. For the two types of filters in this work, nine different configrations have been considered for the sample width W (, 4, 48 bits) and for filter order N (6, 3, 64) samples. A total of 8 filters of both types have been modeled and generated in VHDL. Then, these filters have been synthesized and place-and-roted. The data reslted from the place-androt process, which is related to system delay and logic size, has been collected and analyzed. The reslts analysis have shown that the signed-digit FIR filters designed in this work are slightly faster than the carrysave FIR filters. The filter delay is slightly proportional to N, bt highly proportional to W. The signed-digit filters are constantly abot. times faster than the carry-save filters. Both types of filters have consmed almost the same amont of logic for low precision samples while they differ in logic tilization as the precision increases. The signed-digit filter reported better logic tilization especially for W = 48 bits where it becomes 30 % to 40 % smaller than the carry-save filter. In conclsion, both the signed-digit and the carry-save filters are fast and efficient becase of the carry-propagate-free addition they involve. The speedp that is gained in the FIR filter when signed-digit arithmetic is sed is not so significant. Likewise, the filter size redction for a sample width arond bits is almost negligible. However, the improvement in logic tilization for wider samples is strongly significant. Therefore, designing FIR filters sing signed-digit nmber system becomes efficient and sefl more than carry-save filters when the filter works for high precision samples. However, the signed-digit filter is sperior over the carry-save filter in logic tilization more than speed. REFERENE []. mith, The cientist and Engineer's Gide to Digital ignal Processing, an Diego: alifornia Technical Pblishing, P a g e

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