Design and Implementation of Multilevel QAM Band pass Modems (8QAM, 16QAM, 32QAM and 64QAM) for WIMAX System Based on SDR Using FPGA

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1 International Jornal of Soft Compting and Engineering (IJSCE) ISSN: , Volme-4, Isse-, March 24 esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA Hadi T. Ziboon, Mhannad Y. Mhsin Abstract The objective of this paper is to simlate, design and implementation of a proposed system of mltilevel bandpass AM modems (modlation/demodlation) schemes with selectable techniqe between them based on Software efined Radio (SR) sing FPGA for WIMAX system. These modems are 8AM, 6AM, 32AM and 64AM. MATLAB-Simlink tool and M-files are sed to design these modems. Simlink HL Coder is sed to convert all files to VHL Codes for hardware implementation sing FPGA Altera-Cyclone II Family E2 board. Simlink HL Coder proves the capabilities to generate Hardware escription Langage (HL) code to MATLAB model (Simlink and M-file) for comple nits of proposed system. The comple nits are converted to simple nits compatible with Simlink HL Coder. The eperimental reslts show that there is coincidence between transmitted and received data with average time delay of (.35-.4µsec) for different data rate (.5-3Mbps). Keywords: FPGA, SR, Simlink HL Coder, VHL and WIMAX. I. INTROUCTION The wireless commnications revoltion started with the mobile phone at the beginning of the 8 s and all the improvements which have led to the mltiplication of mobile and wireless commnications networks and standards []. Wireless commnication systems are rapidly evolving throgh the incessant etension of the old standards with the new generations. A side effect of this rapid growth is an ecess of mobile system standards; every major contry has its own standards. Therefore, the software defined radio (SR) concept is emerging as a potential pragmatic soltion [2]. SR is a new commnication system architectre in the field of wireless commnications. It has played a hge role in giding the development of commnication systems [3,4]. The software radio architectre consists of three major sections RF section, IF section and Baseband section. RF section which incldes antenna and RF front-end which are fied hardware. IF section and Baseband section perform signal processing fnctions. However, Analog to igital Converter (AC) and igital to Analog Converter (AC) will be reqired for trans-receiver. Silicon technology provides common platforms for SR implement, sch as Field Programmable Gate Arrays (FPGAs), igital Signal Processors (SPs), General Prpose Processors (GPPs) and Application-Specific Integrated Circits (ASICs) [5,6]. Manscript received on March, 24 r. Hadi T. Ziboon, M.Sc. degree in electronic and commnication engineering from college of engineering University of Baghdad, Iraq Mhannad Y. Mhsin, received the B.Sc. degree in electronic engineering from University of Technology, Baghdad, Iraq MathWorks introdced Simlink HL Coder, in 26, which atomatically generates synthesizable Hardware escription Langish HL Codes. Simlink HL Coder with MATLAB facility can be considered as a compact package which incldes the analysis, design, implementation and verification of hardware, ths providing a path directly from system models to programming FPGA. The design and implementation of the SR proposed system based on HL Simlink Coder give more fleibility and more confidence becase of the ability to eamine the system performance at any point in the design process. II. AM SYSTEM adratre Amplitde Modlation (AM) is a type of high spectral efficiency modlation techniqe that is widely sed by mobile celllar commnications [7]. AM signals are normally generated by smming two amplitde modlated signals with carriers that are ninety degrees ot of phase. The AM signal is given by: s(t) A(t) [cos(φ(t)) cos(2πfct) sin(φ(t)) sin(2πfct)] () Then, Eqation () can be simplified as shown below s(t) AI(t) cos(2πfct) A(t) sin(2πfct) (2) where the modlating signals AI(t) A(t) cos(φ(t)) and A(t) A(t) sin(φ(t)). However, modlation schemes with high spectral efficiencies are often qite sensitive to noise and can reslt in high bit error rates, as is the case with high-level AM constellations. For this reason, many new systems adapt the AM constellation to the channel conditions. Mltilevel adratre Amplitde Modlation (M-AM) etends AM by making the size of the transmitted constellation variable. The variable constellation size means that the nmber of bits per symbol is also variable. Therefore, as the nmber of bits per symbol increases, the rate at which the information can be sent also increases as long as the symbol rate remains constant. This leads to the possibility of variable bit rate operation in a constant bandwidth. Figre () shows the constellation of 4AM, 6AM, 64AM. Figre (2) and Figre (3) show the AM transmitter and receiver block diagram respectively [8, 9]. 7 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

2 esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA Figre (): Constellation diagram of 4AM, 6AM, 64AM Figre (2) : Block diagram of AM transmitter Figre (5): esign procedre of the proposed SR System Figre (3): Block diagram of AM receiver III. ESIGN AN IMPLEMENTATION PROCEURE OF THE PROPOSE SYSTEM Figre (4) shows the block diagram of the proposed system. The main parts and fnctions of the implemented proposed system are:. Transmitter: The transmitter is responsible for generating the symbols of the transmitted data which is transmitted over a wireless channel. 2. Receiver: which is responsible for data reception and demodlation of the received data. Figre (4) General layot of the proposed system Figre (5) describes the design and implementation procedre sed for the proposed SR system. The SR parameters are set p according to IEEE82.6e WIMAX standard. Then, the design is implemented as a model sing MATLAB (combination MATLAB-Simlink and M-file) and fnctional simlation is performed to performance evalation. When the design behavior becomes persaded, the net step wold be generating VHL codes for the model as well as generating test benches for simlation prposes. The design behavior is tested once again bt this time in digital environment sing ModelSim tool provided by Altera. Finally, the generated VHL netlists are synthesized and downloaded to FPGA board. The proposed system was designed based on MATLAB (Simlink and M-file) to satisfy the fnctionality of the SR proposed system. However the Simlink HL Coder is sed to convert to VHL codes. Codes are sed to implement SR proposed system in FPGA hardware platform. Some MATLAB-Simlink blocks and MATLAB codes for M-file, especially those that contain comple fnctions, modlator, demodlator, filter coefficient parameters and carrier signals specifications can not be converted to VHL codes directly. To solve these problems, these blocks are redesigned sing their basic components sch that they can be converted to VHL codes, change the coefficient parameters and sed MATLAB instrctions codes sitable for converted to VHL codes. The system parameters setting incldes specifying the different types of modlation/demodlation and other related system operations that the SR cold handle []. Table () shows the proposed design system parameters. The SR system is very fleible and can change its parameters easily. Table (): esign system parameters Item Font Size Modlation type 8AM, 6AM,32AM, 64AM MAM is sed in this system to increase data rate of transmission. IF freqency MHz Moderate freqency can be sed to implement SR system. Sampling freqency ecision circit Arm filter MHz Soft ecision circit 5 lengths of FIR filter type This vale is selected for better simlation reslts. Mltilevel decision circit sed to demodlate the MAM modlated signal to retrn the transmitted data. Becase it has linear phase response. 8 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

3 In A[3..] B[3..] 4' h -- A[3..] B[3..] A[3..] B[3..] 4' h -- A[3..] B[3..] Add Eqal Add Eqal In P_block:_S_P Ot Ot2 Ot3 4' h -- 4' h -- 5' h4 -- 5' hc -- 5' hc -- 5' h4 -- address_cnt~[3..] _enable 3[4..] 4[4..] 5[4..] 6[4..] 2 2 address_cnt_~[3..] Embedded_4:_Embedded_4 y[4..] y[4..] address_cnt[3..] address_cnt_[3..] 6' he -- 6' hfe4c -- 6' hfe4c -- 6' he -- 6' hff2 -- 6' h8c -- 6' hf8 -- 6' hf9 -- 6' hfe8a -- 6' hff6 -- 6' h8 -- 6' hffe -- M [2..] ATA[7..] M [2..] ATA[7..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] M4 [3..] ATA[5..] M5 [3..] ATA[5..] M6 [3..] ATA[5..] M7 [3..] ATA[5..] M8 [3..] ATA[5..] M9 [3..] ATA[5..] M [3..] ATA[5..] M [3..] ATA[5..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] 2' h -- A[7..] B[4..] A[4..] B[7..] Mlt Mlt A[3..] B[3..] Add2 2' h -- A[3..] B[7..] A[3..] B[7..] Mlt2 Mlt3 Inpt[2..] Inpt[2..] LPF_block:_LPF LPF_block:_LPF Otpt[2..] Otpt[2..] In[2..] In[2..] REI_block:_REI REq_block:_REq Ot[4..] Ot[4..] Embedded_5:_Embedded_5 _enable y2 y3 y[4..] y[4..] Rate_Transition4_ot In In2 In3 S_block:_P_S Ot data demod International Jornal of Soft Compting and Engineering (IJSCE) ISSN: , Volme-4, Isse-, March 24 IV. GENERATION OF VHL COES FOR THE PROPOSE SYSTEM USING HL SIMULINK COER Simlink HL Coder generates bit-tre and cycleaccrate, synthesizable Verilog and VHL code from Simlink models, M-files of MATLAB codes, and Stateflow charts. The generated HL code can be simlated and synthesized sing indstry-standard tools and then implemented on FPGAs or ASICs. Simlink HL Coder can be sed to generate the Hardware escription Langage (HL) code based on Simlink models and Stateflow finite-state machines. The coder brings the Model-Based esign approach into the domain of (ASIC) and (FPGA) development. The time spent by designer to fine tning algorithms and models can be redced by sing HL Simlink Coder[]. The coder generates synthesis scripts for the Synplify family of synthesis tools. In this work, The arts II 9. web edition sed as synthesis software have been sed. The defalt settings of Simlink HL coder are not compatible with arts II (compatible with Synplify synthesis software as mentioned above), therefore a control file (MATLAB file) is sed to change the coder settings to be compatible with arts II 9. web edition synthesis software. V. VERIFYING ESIGN FUNCTIONALITY USING MOELSIM SIMULATION TOOL Simlation may be defined as the process of verifying the fnctional characteristics of models at any level of abstraction. VHL simlation verifies the fnctionality of the system i.e., given the epected inpt and test whether the otpts are as epected or not. A VHL testbench and data vectors, which have been created by MATLAB Simlink Coder tool and se ModelSim-Altera 6.4a (arts II 9.) Starter Edition simlation tool to simlate the VHL Codes. ModelSim provides a complete HL simlation environment that enables verifing the fnctional and timing models of the design, and the VHL sorce code. VI. ESIGN SYNTHESIS OF THE PROPOSE SYSTEM USING UARTUS II esign Synthesis is a process that starts from a high level of logic abstraction (typically Verilog or VHL) and atomatically creates a lower level of logic abstraction of the proposed system. The first step in the synthesis process is compilation. Compilation is the conversion of the highlevel VHL langage, which describes the circit at the Register Transfer Level (RTL), into a netlist at the gate level. The second step is optimization, which is performed on the gate-level netlist of VHL Codes to get optimal speed of eection and minimize the area of FPGA (NO. of nits of FPGA which is sed). Finally, place-and-rote (fitter) software will generate the physical layot for a PL/FPGA chip or will generate the masks for an ASIC. In this work, arts II 9. software has been sed, providing a complete design environment for System On a Programmable Chip (SOPC) design, which ensres easy design entry, fast processing, and straightforward device programming. Altera-Cyclone II FPGA family- E2 Kit is sed as a target device for implementation prposes. VII. IMPLEMENTATION OF 8AM, 6AM, 32AM, 64AM SYSTEMS TECHNIUE BASE ON FPGA Figre (6) The implementation of the 8AM techniqe Figre (6) shows the implementation of the 8AM System techniqe based on Altera- Cyclone II FPGA-E2 board. The inpt serial data have been passed in the serial to parallel converter circit for the 8AM specification and bassband modlated by embedded4 circit then mltiplied in the IF stage by the carrier signals (digital sin for I- Channel and digital cos for -Channel) and they are mied to transmit 8AM bandpass modlated signal. in the receiver, the 8AM bandpass modlated signal has been demodlated by mltiplying it by the carrier signals in the receiver IF stage and filtered to etract two channels bassband signals (I&) then decision circits are sed for I& channels and embedded5 circit is sed to bassband demodlate signals finally, the parallel to serial converter circit is sed to retrn the serial data. Figre (7) shows the implemented embedded4 circit (sed to bassband modlated signal). Figre (8) shows the implemented embedded5 circit (sed to bassband demodlated signal). Figre (9) and Figre () show the implemented decision circits for I& channels respectively. _enable 4[4..] 3[4..] 5[4..] 6[4..] Embedded_4~7 Embedded_4~4 Embedded_4~ Embedded_4~ Embedded_4~8 Embedded_4~6 Embedded_4~5 Embedded_4~3 Embedded_4~2 Embedded_4~ y~[4..] 2 y~[4..] 2 y~[9..5] 2 y~[9..5] 2 y~[4..] 2 Figre (7) The implemented embedded4 circit of 8AM (sing for bassband modlated signal ) y~[4..] 2 y~[9..5] 2 y~[9..5] 2 y~[24..2] 2 y~[24..2] 2 y~[29..25] 2 y~[29..25] 2 y~[34..3] 2 y[4..] y[4..] 9 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

4 2' h -- ' h -- A[2..] B[2..] A[3..] B[3..] 3' h3fe66666 ' h -- 9' h -- A[2..] B[2..] 2' h ' -- ' h -- A[3..] 9' h -- B[3..] 3' h A[3..] B[3..] 3' h99999 ' -- 9' h In 4' h -- 4' h -- A[3..] B[3..] A[3..] B[3..] A[3..] B[3..] A[3..] B[3..] Add Eqal Add Eqal In P_block:_S_P Ot Ot2 Ot3 Ot4 4' h -- 4' h -- 5' h4 -- 5' hc -- 5' hc -- 5' h4 -- address_cnt~[3..] _enable 3 4[4..] 5[4..] 6[4..] 7[4..] 2 2 address_cnt_~[3..] Embedded_6:_Embedded_6 y[4..] y[4..] address_cnt[3..] address_cnt_[3..] 6' he -- 6' hfe4c -- 6' hfe4c -- 6' he -- 6' hff2 -- 6' h8c -- 6' hf8 -- 6' hf9 -- 6' hfe8a -- 6' hff6 -- 6' h8 -- 6' hffe -- M [2..] ATA[7..] M [2..] ATA[7..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] M4 [3..] ATA[5..] M5 [3..] ATA[5..] M6 [3..] ATA[5..] M7 [3..] ATA[5..] M8 [3..] ATA[5..] M9 [3..] ATA[5..] M [3..] ATA[5..] M [3..] ATA[5..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] 2' h -- A[7..] B[4..] A[4..] B[7..] Mlt Mlt A[3..] B[3..] Add2 2' h -- A[3..] B[7..] A[3..] B[7..] Mlt2 Mlt3 Inpt[2..] Inpt[2..] LPF_block2:_LPF LPF_block:_LPF Otpt[2..] Otpt[2..] In[2..] In[2..] REI_block2:_REI REq_block:_REq Ot[4..] Ot[4..] Embedded_7:_Embedded_7 _enable y2 y3 y[4..] y[4..] 3 Rate_Transition5_ot In In2 In3 In4 S_block:_P_S Ot data demod esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA y[4..] A[4..] B[4..] 5' hc -- Eqal2 Embedded_5~3 y[4..] _enable Eqal3 A[4..] B[4..] 5' hc -- Eqal A[4..] B[4..] 5' h4 -- Eqal A[4..] B[4..] 5' h4 -- Embedded_5~ Embedded_5~2 Embedded_5~ ~ ~ ~ ~ ~ ~ ~2 ~2 ~2 ~3 ~3 ~4 ~4 ~5 ~3 ~6 ~5 B[4..] 5' hc -- Eqal5 A[4..] Embedded_5~6 A[4..] B[4..] 5' h4 -- Eqal4 Embedded_5~5 Embedded_5~4 y2 (GN) y3 (VCC) Figre (8) The implemented embedded5 circit of 8AM (sing for bassband demodlated signal) Figre () The implementation of the 6AM techniqe y[2..] _enable LessThan Embedded_i_block~ i~[9..5] Embedded_6~4 Embedded_6~8 Embedded_6~5 Embedded_6~ Embedded_6~9 Embedded_6~5 Embedded_6~6 Embedded_6~3 Embedded_6~2 Embedded_6~ Embedded_6~2 Embedded_6~7 Embedded_6~6 Embedded_6~4 y~[44..4] 2 y~[4..] 2 y~[9..5] 2 y~[49..45] 2 y~[9..5] 2 y~[4..] 2 y~[54..5] 2 y~[4..] 2 y~[9..5] 2 y~[9..5] 2 y~[24..2] 2 y~[29..25] 2 y~[34..3] 2 y~[39..35] 2 y~[44..4] 2 y~[49..45] 2 y~[54..5] 2 y~[59..55] 2 y~[64..6] 2 y~[69..65] 2 y~[59..55] 2 y~[24..2] 2 y~[74..7] 2 y[4..] y~_ y[4..] LessThan Embedded_i_block~ i~[4..] i~[4..] i[4..] 3 Embedded_6~ Embedded_6~24 Embedded_6~2 Embedded_6~26 Embedded_6~22 Embedded_6~3 y~[4..] 2 Embedded_6~23 Embedded_6~2 y2[4..] y3[4..] y4[4..] y5[4..] Embedded_6~ Figre (9) The implemented decision circit for the I-Channel of 8AM Embedded_6~8 Embedded_6~9 Embedded_6~7 Embedded_6~_ Embedded_6~9_ Embedded_6~7_ y[2..] _enable A[2..] 2' h -- B[2..] ' h -- LessThan 4[4..] 5[4..] 6[4..] y~_ 7[4..] Figre (2) The implemented embedded6 circit of 6AM (sing for bassband modlated signal) Embedded_7~5_ ~[2..] y2[4..] y3[4..] 3' h ' h -- A[3..] ' h -- B[3..] LessThan Embedded_q_block~ q~[4..] Figre ()The implemented decision circit for the -Channel of 8AM The same procedre, which is mentioned above can be sed for implementation 6AM, 32AM and 64AM. Figre () shows the implementation of the 6AM System techniqe. Figre (2) shows the implemented embedded6 circit (sed to bassband modlated signal). Figre (3) shows the implemented embedded7 circit (sed to bassband demodlated signal). Figre (4) and Figre (5) show the implemented decision circits for I& channels respectively. 2 q[4..] Embedded_7~6_ y3 (VCC) y2 (GN) Eqal3_ y[4..] Embedded_7~3_ Embedded_7~2_ Embedded_7~_ Embedded_7~8_ Embedded_7~_ Embedded_7~3_ Embedded_7~_ Embedded_7~_ Embedded_7~7_ Embedded_7~9_ Embedded_7~4_ A[4..] B[4..] 5' h4 -- ~ Eqal 3~ ~ ~ 2 Embedded_7~2 3~ ~ ~ ~3 3~2 ~2 ~2 ~4 3~3 ~3 ~3 ~5 3~4 ~4 ~4 ~6 3~5 ~5 ~[6..5] 2 ~6 ~7 3~7 ~[8..7] 2 3~[9..8] ~9 2 3~ ~ Figre (3) The implemented embedded7 circit of 6AM(sing for bassband demodlated signal) 3~6 ~8 ~9 ~ 3~ ~ 3~2 ~2 3~3 A[4..] B[4..] 5' hc -- A[4..] B[4..] 5' h4 -- A[4..] B[4..] 5' hc -- ~7 3~4 ~3 ~ Eqal7 Eqal6 Eqal4 3 Eqal7_ Eqal6_ Eqal4_ Eqal_ Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

5 In A[3..] B[3..] 4' h -- A[3..] B[3..] A[3..] B[3..] 4' h -- A[3..] B[3..] Add Eqal Add Eqal In P_block2:_S_P 2' h -- ' h -- A[2..] B[2..] A[3..] B[3..] 3' h3fe66666 ' h -- 9' h -- A[2..] B[2..] 2' h ' -- ' h -- A[3..] 9' h -- B[3..] 3' h A[3..] B[3..] 3' h99999 ' -- 9' h -- 2' h -- ' h -- A[2..] B[2..] A[3..] B[3..] 3' h3fe66666 ' h -- 9' h -- A[2..] B[2..] 2' h ' -- ' h -- A[3..] 9' h -- B[3..] 3' h A[3..] B[3..] 3' h99999 ' -- Ot Ot2 Ot3 Ot4 Ot5 9' h -- 4' h -- 4' h -- 7' h4 -- 7' h7c -- 7' hc -- 7' h ' h4 -- 7' h6c -- address_cnt~[3..] _enable 3 4 5[6..] 6[6..] 7[6..] 8[6..] 9[6..] [6..] 2 2 address_cnt_~[3..] Embedded_8:_Embedded_8 y[6..] y[6..] address_cnt[3..] address_cnt_[3..] 6' he -- 6' hfe4c -- 6' hfe4c -- 6' he -- 6' hff2 -- 6' h8c -- 6' hf8 -- 6' hf9 -- 6' hfe8a -- 6' hff6 -- 6' h8 -- 6' hffe -- M [2..] ATA[7..] M [2..] ATA[7..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] M4 [3..] ATA[5..] M5 [3..] ATA[5..] M6 [3..] ATA[5..] M7 [3..] ATA[5..] M8 [3..] ATA[5..] M9 [3..] ATA[5..] M [3..] ATA[5..] M [3..] ATA[5..] M2 [3..] ATA[5..] M3 [3..] ATA[5..] 2 2 2' h -- A[7..] B[6..] A[6..] B[7..] Mlt Mlt A[5..] B[5..] Add2 2 2' h -- A[5..] B[7..] A[5..] B[7..] Mlt2 Mlt3 2 Inpt[23..] Inpt[23..] LPF_block3:_LPF LPF_block2:_LPF Otpt[23..] Otpt[23..] 2 In[23..] In[23..] REI_block3:_REI REq_block2:_REq Ot[6..] Ot[6..] 2 _enable y2 y3 y[6..] y[6..] Embedded_9:_Embedded_9 3 4 Rate_Transition6_ot In In2 In3 In4 In5 S_block2:_P_S Ot data demod International Jornal of Soft Compting and Engineering (IJSCE) ISSN: , Volme-4, Isse-, March 24 y[2..] _enable Embedded_8~58_ 3 Embedded_8~55 Embedded_8~6 Embedded_8~56 Embedded_8~6_ Embedded_8~56_ Embedded_8~54 Embedded_8~54_ Embedded_i_block~ i~[9..5] Embedded_8~57 Embedded_8~53 Embedded_8~53_ Embedded_8~48 Embedded_8~5 Embedded_8~5_ LessThan Embedded_8~46 Embedded_8~47 Embedded_8~45 Embedded_8~47_ Embedded_8~45_ Embedded_8~4 Embedded_8~4_ LessThan Embedded_i_block~ i~[4..] i~[4..] i[4..] Embedded_8~42_ Embedded_8~43 Embedded_8~38 Embedded_8~4 Embedded_8~39 Embedded_8~37 Embedded_8~4_ Embedded_8~39_ Embedded_8~37_ Embedded_8~34_ Embedded_8~35 Embedded_8~36 Embedded_8~33 Embedded_8~36_ Embedded_8~33_ Embedded_8~3 Embedded_8~32 Embedded_8~32_ y2[4..] y3[4..] y4[4..] y5[4..] Figre (4) The implemented decision circit for the I-Channel of 6AM Embedded_8~26 Embedded_8~27 Embedded_8~28 Embedded_8~3 Embedded_8~29 Embedded_8~25 Embedded_8~3_ Embedded_8~29_ Embedded_8~25_ y[2..] _enable Embedded_8~9_ Embedded_8~2 Embedded_8~23 Embedded_8~22 Embedded_8~2 Embedded_8~8 Embedded_8~22_ Embedded_8~23_ Embedded_8~2_ Embedded_8~8_ Embedded_8~6 Embedded_8~7 Embedded_8~7_ Embedded_q_block~ q~[9..5] Embedded_8~ Embedded_8~2 Embedded_8~3 Embedded_8~5 Embedded_8~4 Embedded_8~5_ Embedded_8~4_ 4 Embedded_8~ Embedded_8~_ LessThan Embedded_8~8 Embedded_8~9 Embedded_8~7 Embedded_8~9_ Embedded_8~7_ LessThan Embedded_q_block~ q~[4..] Embedded_8~4_ Embedded_8~5 Embedded_8~6 Embedded_8~3 Embedded_8~6_ Embedded_8~3_ q~[4..] q[4..] Embedded_8~ Embedded_8~2 Embedded_8~2_ Embedded_8~ Embedded_8~_ y2[4..] y3[4..] y4[4..] y5[4..] Figre (5) The implemented decision circit for the -Channel of 6AM Figre (6) shows the implementation of the 32AM System techniqe Figre (7) shows the implemented embedded8 circit (sed to bassband modlated signal). Figre (8) shows the implemented embedded9 circit (sed to bassband demodlated signal). Figre (9) and Figre (2) show the implemented decision circits for I& channels respectively. Embedded_8~26_ Embedded_8~_ Embedded_8~43_ Embedded_8~57_ Figre (7) The implemented embedded8 circit of 32AM (sing for bassband modlated signal) Embedded_9~8_ ~5_ y2 (GN) Embedded_9~23_ Embedded_9~2_ Embedded_9~9_ 4~9_ 4~26_ Embedded_9~5_ Embedded_9~2_ 4~6_ ~6 4~2 ~7 4~2 ~8 4~22 ~9 4~23 ~ 4~24 ~ 4~27 4~25 ~_ 4~27_ 4~25_ 4~7_ Embedded_9~22_ 4~7 Embedded_9~29_ y3 (VCC) Embedded_9~6_ 3~_ Embedded_9~3_ Embedded_9~27_ Embedded_9~28_ 4~ 3~2 4~ 3~3 4~2 3~4 4~3 3~5 4~4 3~6 3~7 3~8 4~7 4~5 3~9 4~7_ 4~5_ 3~9_ Embedded_9~4_ ~2_ Embedded_9~24_ ~_ Embedded_9~4_ ~7_ 4~6_ Embedded_9~9_ Embedded_9~2_ Embedded_9~2_ Embedded_9~_ Embedded_9~_ Embedded_9~_ Embedded_9~_ Embedded_9~26_ Embedded_9~25_ Embedded_9~7_ Embedded_9~5_ Embedded_9~3_ Embedded_9~6_ ~22 ~2 ~8 ~23 ~3 ~9 ~24 ~4 ~ ~25 ~5 ~ ~26 ~6 ~2 ~3 ~4 3~ ~27 ~7 ~5 3~_ ~7_ ~5_ Figre (6) The implementation of the 32AM techniqe Figre (8) The implemented embedded9 circit of 32AM (sing for bassband demodlated signal) Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

6 y[23..] _enable y2[6..] y3[6..] y4[6..] y5[6..] y6[6..] y7[6..] y8[6..] y9[6..] y[23..] _enable y2[6..] y3[6..] y4[6..] y5[6..] y6[6..] y7[6..] y8[6..] y9[6..] 23' h7fe -- 32' hffa66666 ' h -- 23' h2 ' -- ' h -- A[23..] B[23..] 9' h -- ' h -- A[32..] B[32..] A[23..] B[23..] A[32..] 9' h -- B[32..] 32' h A[33..] 33' h4ccccc -- B[33..] ' h -- ' h -- 23' h2 -- ' h -- A[23..] B[23..] ' h -- A[33..] ' h -- B[33..] 33' hffb ' h7fe ' h -- 23' h -- A[23..] B[23..] ' h -- A[23..] B[23..] A[33..] 33' hffb B[33..] ' h -- ' h -- 23' h ' -- ' h -- A[23..] B[23..] A[33..] ' h -- B[33..] 33' h4ccccc -- 32' h ' -- 9' h -- 23' h7fe -- 32' hffa66666 ' h -- A[32..] B[32..] ' h -- A[23..] B[23..] 9' h -- 23' h2 ' -- ' h -- A[23..] B[23..] A[32..] 9' h -- B[32..] 32' h A[33..] 33' h4ccccc -- B[33..] ' h -- ' h -- 23' h2 -- A[32..] B[32..] ' h -- A[23..] B[23..] ' h -- A[33..] ' h -- B[33..] 33' hffb ' h7fe ' h -- 23' h -- A[23..] B[23..] ' h -- A[23..] B[23..] A[33..] 33' hffb B[33..] ' h -- ' h -- 23' h ' -- ' h -- A[23..] B[23..] A[33..] ' h -- B[33..] 33' h4ccccc -- 32' h ' -- 9' h -- A[32..] B[32..] LessThan LessThan LessThan8 LessThan9 LessThan6 LessThan7 LessThan5 LessThan LessThan LessThan LessThan LessThan8 LessThan9 LessThan6 LessThan7 LessThan5 LessThan LessThan Embedded_i_block2~5 Embedded_i_block2~4 Embedded_i_block2~3 Embedded_i_block2~2 Embedded_i_block2~ Embedded_i_block2~ i~[6..] 2 2 Embedded_q_block2~5 Embedded_q_block2~4 Embedded_q_block2~3 Embedded_q_block2~2 Embedded_q_block2~ Embedded_q_block2~ q~[6..] i~[3..7] 2 q~[3..7] 2 i~[2..4] 2 q~[2..4] 2 i~[27..2] 2 q~[27..2] 2 i~[34..28] 2 q~[34..28] 2 i~[4..35] 2 q~[4..35] 2 i~[48..42] 2 q~[48..42] 2 i[6..] q[6..] esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA 6 Embedded_9_block~4 Embedded_9_block~9 Embedded_9_block~2 Embedded_9_block~3 Embedded_9_block~22 Embedded_9_block~22_ Embedded_9_block~ Embedded_9_block~_ 3 Embedded_9_block~5 Embedded_9_block~6 Embedded_9_block~7 Embedded_9_block~3 Embedded_9_block~3_ Embedded_9_block~ Embedded_9_block~_ Embedded_9_block~97 Embedded_9_block~97_ Embedded_9_block~88 Embedded_9_block~89 Embedded_9_block~9 Embedded_9_block~9 Embedded_9_block~9_ 5 Embedded_9_block~85 Embedded_9_block~84 Embedded_9_block~84_ Embedded_9_block~73 Embedded_9_block~8 Embedded_9_block~74 Embedded_9_block~82 Embedded_9_block~82_ Embedded_9_block~7 Embedded_9_block~7_ 4 Embedded_9_block~66 Embedded_9_block~67 Embedded_9_block~67_ Embedded_9_block~64 Embedded_9_block~63_ Embedded_9_block~57 Embedded_9_block~58 Embedded_9_block~64_ Embedded_9_block~59 Embedded_9_block~59_ Embedded_9_block~5 Embedded_9_block~5 Embedded_9_block~5_ Embedded_9_block~47 Figre (9) The implemented decision circit for the I-Channel of 32AM Embedded_9_block~44_ Embedded_9_block~47_ Embedded_9_block~45 Embedded_9_block~45_ Embedded_9_block~42 Embedded_9_block~43 Embedded_9_block~43_ Embedded_9_block~35 Embedded_9_block~32 Embedded_9_block~32_ Embedded_9_block~26 Embedded_9_block~27 Embedded_9_block~28 Embedded_9_block~29 Embedded_9_block~25 Embedded_9_block~25_ Embedded_9_block~7_ Embedded_9_block~23 Embedded_9_block~23_ Embedded_9_block~9 Embedded_9_block~9_ Embedded_9_block~ Embedded_9_block~2 Embedded_9_block~3 Embedded_9_block~3_ Embedded_9_block~8 Embedded_9_block~8_ Embedded_9_block~6 Embedded_9_block~5_ Embedded_9_block~6_ Embedded_9_block~4 Embedded_9_block~4_ Embedded_9_block~85_ Embedded_9_block~29_ Embedded_9_block~35_ Embedded_9_block~66_ Embedded_9_block~74_ Embedded_9_block~8_ Embedded_9_block~3_ Embedded_9_block~2_ Figre (22) The implemented embedded circit of 64AM (sing for bassband modlated signal) Figre (2) The implemented decision circit for the -Channel of 32AM Figre (2) shows the implementation of the 64AM System techniqe Figre (22) shows the implemented embedded circit (sed to bassband modlated signal). Figre (23) shows the implemented embedded circit (sed to bassband demodlated signal). Figre (24) and Figre (25) show the implemented decision circits for I& channels respectively. Figre (26) shows the implemented digital low pass filter sed for all modems. Embedded_~_ 6~5_ Embedded_~9_ Embedded_~8_ Embedded_~3_ 6~48_ Embedded_~4_ Embedded_~6_ 6~45_ y2 (GN) Embedded_~47_ 6~32_ Embedded_~2_ Embedded_~4_ Embedded_~26_ 6~3_ Embedded_~53_ Embedded_~33_ 6~28_ Embedded_~35_ 6~26_ y3 (VCC) Embedded_~49_ 6~2_ Embedded_~5_ 6~_ Embedded_~54_ 6~7_ Embedded_~7_ 6~46 6~8 6~5 6~49 6~47 6~33 6~3 6~29 6~27 6~3 6~ 6~9 6~5_ 6~49_ 6~47_ 6~33_ 6~3_ 6~29_ 6~27_ 6~3_ 6~_ 6~9_ 5~53_ Embedded_~6_ Embedded_~_ 5~54 5~55 5~55_ 5~5_ 5~5_ Embedded_~23_ 5~5 5~37_ 5~38_ Embedded_~27_ 5~38 5~33_ Embedded_~29_ 5~34 5~35 5~35_ 5~3_ 5~32_ Embedded_~43_ 5~32 5~7_ 5~8_ Embedded_~48_ 5~8 5~2_ Embedded_~46_ Embedded_~5_ 5~3 5~4 5~5 5~5_ 4~53_ Embedded_~24_ 4~34_ Embedded_~39_ 4~54 4~35 4~36 4~37 4~38 4~55 4~39 4~55_ 4~39_ 4~9_ Embedded_~38_ Embedded_~44_ 4~2 4~2 4~2_ 4~4_ 4~5_ Embedded_~59_ 4~5 4~_ Embedded_~2_ 4~ 3~52_ 3~53_ Embedded_~5_ 3~53 3~39_ 3~4_ Embedded_~2_ 3~4 3~33_ 3~34_ Embedded_~4_ 3~34 3~3_ Embedded_~55_ 3~4 3~5 3~5_ 3~_ Embedded_~3_ 3~ Embedded_~22_ ~44_ ~24_ Embedded_~7_ ~43_ Embedded_~42_ ~25 ~26 ~27 ~28 ~29 ~44 ~3 ~3_ ~4_ ~5_ Embedded_~2_ ~5 ~8_ ~9_ Embedded_~3_ ~9 ~_ Figre (2) The implementation of the 64AM techniqe Figre (23) The implemented embedded circit of 64AM (sing for bassband demodlated signal) ~ 2 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

7 y[23..] _enable y2[6..] y3[6..] y4[6..] y5[6..] y6[6..] y7[6..] y8[6..] y9[6..] y[23..] _enable y2[6..] y3[6..] y4[6..] y5[6..] y6[6..] y7[6..] y8[6..] y9[6..] 23' h7fe -- ' h -- A[23..] B[23..] A[32..] B[32..] 32' hff ' h -- 9' h -- A[23..] B[23..] 23' h2 ' -- ' h -- A[32..] 9' h -- B[32..] 32' h A[34..] 34' h B[34..] ' h -- ' h -- 23' h2 -- ' h -- A[23..] ' h -- B[23..] A[34..] ' h -- B[34..] 34' h3ff A[23..] B[23..] 23' h7fe ' h -- 23' h -- ' h -- A[23..] B[23..] A[34..] 34' h3ff B[34..] ' h -- ' h -- A[23..] B[23..] 23' h ' -- ' h -- A[34..] ' h -- B[34..] 34' h A[32..] 32' h B[32..] ' h -- 9' h -- 23' h7fe -- ' h -- A[23..] B[23..] A[32..] B[32..] 32' hffa66666 ' h -- 9' h -- A[23..] B[23..] 23' h2 ' -- ' h -- A[32..] 9' h -- B[32..] 32' h A[34..] 34' h B[34..] ' h -- ' h -- 23' h2 -- ' h -- A[23..] ' h -- A[34..] ' h -- B[34..] 34' h3ff A[23..] B[23..] 23' h7fe ' h -- 23' h -- ' h -- A[23..] B[23..] A[34..] 34' h3ff B[34..] ' h -- ' h -- A[23..] B[23..] 23' h ' -- ' h -- A[34..] ' h -- B[34..] 34' h B[23..] A[32..] 32' h B[32..] ' h -- 9' h -- LessThan LessThan LessThan8 LessThan9 LessThan6 LessThan7 LessThan5 LessThan LessThan LessThan LessThan LessThan8 LessThan9 LessThan6 LessThan7 LessThan5 LessThan LessThan Embedded_i_block3~5 Embedded_i_block3~4 Embedded_i_block3~3 Embedded_i_block3~2 Embedded_i_block3~ Embedded_i_block3~ i~[6..] 2 Embedded_q_block3~5 Embedded_q_block3~4 Embedded_q_block3~3 Embedded_q_block3~2 Embedded_q_block3~ Embedded_q_block3~ q~[6..] 2 i~[3..7] 2 q~[3..7] 2 i~[2..4] 2 q~[2..4] 2 i~[27..2] 2 q~[27..2] 2 i~[34..28] q~[34..28] 2 2 i~[4..35] q~[4..35] 2 2 i~[48..42] q~[48..42] 2 2 q[6..] i[6..] International Jornal of Soft Compting and Engineering (IJSCE) ISSN: , Volme-4, Isse-, March 24 Figre (32) shows the baseband signal of the 8AM modem modlated signal of cosine carrier. Figre (33) shows the 8AM bandpass transmitted signal. Figre (34) shows the received signal (after mltiplied by a carrier) before filter for I-Channel. Figre (35) shows the received signal after low pass filter for I-Channel. Figre (36) shows the signal after decision circit for I-Channel. Figre (37) shows the received signal (after mltiplied by a carrier) before filter for -Channel. Figre (38) shows the received signal after low pass filter for -Channel. Figre (39) shows the signal after decision circit for -Channel. Figre (4) shows the transmitted data and the final otpt of the PSK modem. The same procedre was sed to generate signals for 6AM, 32AM and 64AM modems. However, their figres are not shown here de to limit the nmber of pages. Figre (24) implemented decision circit for the I-Channel of 64AM Figre (27) Inpt data for I-Channel of the 8AM modem Figre (28) Sin carrier signal of the 8AM modem Figre (29) The modlated signal of I-Channel for 8AM modem Figre (3) Inpt data for -Channel of the 8AM modem Figre (25) implemented decision circit for the -Channel of 64AM Figre (3) Cos carrier signal of the 8AM modem Figre (32) The modlated signal of -Channel for 8AM modem Figre (33) 8AM bandpass modlated signal Figre (26) Implemented igital Low Pass Filter (sed for all modems) VIII. GENERATION OF SIGNALS FOR 8AM MOEM Figre (27) shows the inpt data for I-Channel of the 8AM modem. Figre (28) shows the sine carrier sed for IF stage. Figre (29) shows the baseband signal of the 8AM modem modlated signal of sine carrier. Figre (3) shows the inpt data for -Channel of the 8AM modem. Figre (3) shows the cosine carrier sed for IF stage. Figre (34) Received 8AM signal before filter for I-Channel Figre (35) Received 8AM signal after filter for I-Channel 3 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

8 esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA Figre (36) Received 8AM signal after the decision circit for I-Channel Figre (37) Received 8AM signal before filter for -Channel Figre (4) Inpt data signal, 8AM bandpass modlated signal, demodlated data signal and related control signals for 8AM modem Figre (38) Received 8AM signal after filter for -Channel Figre (42) etails on the 8AM bandpass modlated signal Figre (39) Received 8AM signal after the decision circit for -Channel Figre (4): (a) Inpt data (b) otpt received data IX. SIMULATION RESULTS BASE ON MOELSIM The simlation reslts obtained by sing ModelSim- Altera 6.4a (arts II 9.) represent the second step in the simlation process. Figre (4) shows the inpt data signal, bandpass modlated signal of the 8AM modem, demodlated data signal and related control signals for the 8AM modem. Figre (42) shows more details on the 8AM bandpass modlated signal that are transmitted over the channel. Figre (43) shows the inpt data signal, bandpass modlated signal of the 6AM modem, demodlated data signal and related control signals for the 6AM modem. Figre (44) shows more details on the 6AM bandpass modlated signal that are transmitted over the channel. Figre (45) shows the inpt data signal, bandpass modlated signal of the 32AM modem, demodlated data signal and related control signals for the 32AM modem. Figre (46) shows more details on the 32AM bandpass modlated signal that are transmitted over the channel. Figre (47) shows the inpt data signal, bandpass modlated signal of the 64AM modem, demodlated data signal and related control signals for the 64AM modem. Figre (48) shows more details on the 64AM bandpass modlated signal that are transmitted over the channel. Figre (43) Inpt data signal, 6AM bandpass modlated signal, demodlated data signal and related control signals for 6AM modem Figre (44) etails on the 6AM bandpass modlated signal Figre (45) Inpt data signal, 32AM bandpass modlated signal, demodlated data signal and related control signals for 32AM modem 4 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

9 International Jornal of Soft Compting and Engineering (IJSCE) ISSN: , Volme-4, Isse-, March 24 Figre (49) 8AM modem when control signals are () Figre (46) etails on the 32AM bandpass modlated signal Figre (5) 6AM modem when control signals are () Figre (47) Inpt data signal, 64AM bandpass modlated signal, demodlated data signal and related control signals for 64AM modem Figre (5) 32AM modem when control signals are () Figre (48) etails on the 64AM bandpass modlated signal X. EXPERIMENTAL RESULTS After compiling the VHL code by sing arts II and downloading the bit streams sccessflly to Cyclone II FPGA family, altera E2 kit. TTL data from fnction generator of variable data rate of (.5Mbps-3Mbps) have been applied as the inpt to the kit, while the otpt has been measred by an oscilloscope. Figre (49) shows the inpt and otpt data of the 8AM modem when the control signals are () applied to the kit switches (SW and SW) at the inpt data rate of (.5Mbps). Figre (5) shows the inpt and otpt data of the 6AM modem when the control signals are () applied to the kit switches (SW and SW) at the inpt data rate of (2Mbps). Figre (5) shows the inpt and otpt data of the 32AM modem when the control signals are () applied to the kit switches (SW and SW) at the inpt data rate of (2.5Mbps). Figre (52) shows the inpt and otpt data of the 64AM modem when the control signals are () applied to the kit switches (SW and SW) at the inpt data rate of (3Mbps). Figre (52) 64AM modem when control signals are () XI. CONCLUSIONS The main important reslts obtained from this work can be smmarized as follows:. Software efined Radio (SR) has the fleibility to modify the characteristics of a transmitting and receiving radio device, withot physically modifying the hardware, de to development in system. 2. FPGA offers fleible soltion in IF stage and wideband (WB) modem processing becase it provides high speed, high level of integration, low development costs and low power. 3. Simlink HL Coder proves the capabilities to generate Hardware escription Langage (HL) code to MATLAB model (Simlink and M-file) for comple nits of proposed system. The following comple nits are designed, implemented and verified:- a. The optimal FIR filter design with (5) lengths sed for all modems. 5 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.

10 esign and Implementation of Mltilevel AM Band pass Modems (8AM, 6AM, 32AM and 64AM) for WIMAX System Based on SR Using FPGA b. Mltimode soft decision circit to determine the regions of the received signal in order to define the final otpt data. The decision circit incldes 8, 6, 32 and 64 regions. c. ivision of inpt data by the variable factor according to nmber of bit per symbol. The variable factor is 3,4,5 and 6 and is determined by selectable circits. d. Symbol mapping (baseband modlators) to convert the inpt data levels to the level compatible with bandpass modlators of the proposed system. e. Generation bandpass signal for si modems in order to set the IF signal reqired by SR systems, As well as the generation of the bandpass signal which has optimal tilized area by FPGA with satisfied the reqired sampling rate. 4. The combination of MATLAB (Simlink and M-file) and Simlink HL Coder provides fleible capabilities to analyze, design, simlate, implement and verify. However all these capabilities eist in one system to redce the time spent on fine tning to redce the algorithms and models throgh rapid prototyping and eperimentation and less time on HL coding. Hadi Tarish Ziboon received the B.Sc. degree in electrical engineering from University of Technology, Iraq in 973 and the M.Sc. degree in electronic and commnication engineering from college of engineering University of Baghdad, Iraq in 978 and the Ph.. degree in electronic commnication engineering from University of Aston in Birmingham UK in984. From 984 to 24 he was with research and development center, where he worked on spread spectrm system, freqency synthesizes and synchronization techniqes. He is crrently an Assistant Professor of electronics engineering at University of Technology. His research incldes development of wireless commnication systems based on SR sing FPGA. Mhannad Yosif Mhsin received the B.Sc. degree in electronic engineering from University of Technology, Baghdad, Iraq in 28 and the M.Sc. degree in electronic engineering from University of Technology, Baghdad, Iraq in 22. He is crrently worked in development of wireless commnication systems based on SR sing FPGA. REFERENCES [] F. Kasperski, O. Pierrelee, F. otto and M. Sarlotte, High ata Rate Flly Fleible SR Modem Advanced Configrable Architectre & evelopment Methodology, IEEE esign, Atomation & Test in Erope Conference & Ehibition, pp. 4 44, September 29. [2] R. Mzammil, M.S. Beg and M.M. Jamali esign and Implementation of BPSK Transmitter and Receiver for Software efined Radio on a Model Based evelopment Platform, IEEE Symposim on Indstrial Electronics and applications, pp.89_94, September 2. [3] Z. Zhao, Y. Shen and Y. Bai, esign and Implementation of the BPSK Modem Based on Software efined Radio, IEEE First International Conference on Instrmentation, Measrement, Compter, Commnication and Control, pp. 78_784, 2. [4] A. Karmakar and A. Sinha, A Novel Architectre of a Reconfigrable Radio Processor for Implementing ifferent Modlation Schemes, IEEE Compter Research and evelopment (ICCR) 3rd International Conference, pp. 5_9, 2. [5] Y. H. Chye, M. F. Ain and N. M. Zawawi, esign of BPSK Transmitter Using FPGA with AC, IEEE 9th Malaysia International Conference on Commnications, pp. 45_456, ecember 29. [6] S. W. Shaker, S. H. Elramy and K. A. Shehata, FPGA Implementation of a Reconfigrable Viterbi ecoder for WIMAX Reciver, IEEE International Conference on Microelectronics, pp. 264_267, 29. [7] Y. Yang, J. Li,. Zhang and C. Xi Performance Analysis for Rectanglar AM Modlation with Arbitrary Bits-to-Symbols Mapping over Rician Channel, IEEE International Conference, pp. 7_, 2. [8 A. Goldsmith, Wireless Commnications, Cambridge University Press, 25. [9] S. O. Leary, Understanding igital Terrestrial Broadcasting, Artech Hose Boston London, INC., 2. [] J. G. Andrews, A. Ghosh and R. Mhamed, Fndamentals of WiMAX Understanding Broadband Wireless Networking, Pearson Edcation, Inc., 27. [] Simlink HL Coder, the Mathwork Inc., 2. 6 Pblished By: Ble Eyes Intelligence Engineering & Sciences Pblication Pvt. Ltd.