Minimization of the DC Current Ripple of a Three-Phase Buck+Boost PWM Unity Power Factor Rectifier

Transcription

1 Minimization of the DC Crrent Ripple of a Three-Phase Bck+Boost PWM Unity Power Factor Rectifier Martina Bamann Vienna University of Technology Department of Electrical Drives and Machines Gsshasstrasse 27/E372 A 1040 Vienna/Astria phone: , fax: martina.bamann@twien.ac.at Johann W. Kolar Swiss Federal Institte of Technology (ETH) Zrich Power Electronic Systems Laboratory ETH-Zentrm / ETL H22 CH 8092 Zrich/Switzerland phone: , fax: kolar@lem.ee.ethz.ch Abstract The modlation of a novel three-phase three-switch bck-type nity power factor rectifier with integrated DC/DC boost converter otpt stage is optimized concerning the ripple amplitde of the bck+boost indctor crrent. This is achieved by coordination of the switching operation of the bck inpt stage and of the boost otpt stage. A comparative evalation of different modlation schemes does identify a modlation scheme which simltaneosly does provide minimm DC crrent ripple and minimm inpt filter capacitor voltage ripple at minimm switching losses and/or maximm plse freqency. All theoretical considerations are for operation in a wide inpt voltage range and are verified by simlations and by measrements on a DSP-controlled 5kW prototype of the system. Key words: three-phase PWM rectifier, bck type converter, bck+boost indctor, indctor crrent ripple minimization. 1 Introdction In [1] a novel three-phase three-switch bck-type nity power factor PWM rectifier with integrated DC/DC boost converter otpt stage (three-phase bck+boost PWM rectifier) has been presented (cf. Fig. 1), which does allow to control the otpt voltage to a constant vale of U 0 = 400 V within an niversal inpt voltage range of U N,l l =( ) Vrms line-to-line [2]. D R,N D R,N+ i U,i i N,i ~ D R+ D R L F S R S S S T D F C F ~ N,l-l ~ C F,i Fig. 1: Strctre of the power circit of the three-phase bck+boost PWM rectifier. The three-phase bck+boost PWM rectifier shows the following main advantages: sinsoidal shape of the inpt crrents resistive fndamental mains behavior possibility of limiting the inpt crrent and/or the crrent in the bck+boost indctor for mains overvoltages high efficiency (p to η =97%) high power density (ρ =965W/dm 3 or 15.8W/in 3 ). Frthermore, in contrast to rectifier systems with boosttype inpt stage L L S I ' D C 0 + I 0 U 0 no axiliary start-p circit is reqired. An experimental setp of the three-phase bck+boost PWM rectifier has been realized sing standard power semicondctors (in TO 247 packages) and a digital signal processor ADSP SHARC (Analog Devices) for the implementation of the system control. The specifications of the system prototype are: P 0 =5kW f N =50Hz U N,l l =208V V f P =23.4kHz U 0 =400V (f N denotes the mains freqency, f P denotes the plse freqency). There are different modlation methods available, which differ concerning switching losses, inpt filter capacitor voltage ripple, time behavior of the bck+boost indctor crrent ripple, and concerning the minimm load at which the transition between continos bck+boost indctor crrent (CCM) and discontinos bck+boost indctor crrent (DCM) does occr. In [4] an optimization of the modlation scheme concerning the AC side system behavior has been proposed which does provide a minimm rms vale of the inpt filter capacitor voltage ripple and minimm switching losses. However, as a comparison of the size and/or of the weight of the inpt filter capacitors and of the bck+boost indctor shows, an optimization concerning the DC side cold be more sefl as compared to an AC side optimization in order to redce the size and the weight of the heavy bck+boost indctor and to increase the specific power (W/kg). Crrently, the size of the bck+boost indctor is 327 cm 31, the inpt filter capacitors are approximately 40 % smaller in size. The differenceinweightisevenmoresignificant: the weight of the bck+boost indctors is 1500 g, the weight of the inpt filter capacitors is only 300 g. The implemented components are depicted in Fig. 2, Fig. 2 shows the relations between size and weight. In this paper the modlation of the three-phase bck+ boost PWM rectifier for operation in a wide inpt voltage range is optimized concerning the bck+boost indctor crrent ripple, and all theoretical considerations are verified by simlations and by measrements on the DSP-controlled 5 kw prototype of the system. It is interesting to note, that to the knowledge of the athors the ripple of the DC otpt crrent of a high freqency three-phase bck type PWM converter has not been considered in the optimization of modlation schemes in the literatre so far. (Also for boost-type systems only a very limited nmber of papersisavailableontheanalysisoftherippleofthedcside qantity, cf. e.g. [3].) In section 2 of the paper the basic principle of operation of the three-phase bck+boost PWM rectifier is described briefly. Section 3 treats the different 1 Dimensions: diameter 6cm(2.4in), height 6cm(2.4in)

2 G / g V / cm g 1500 g 190 cm³ Weight Volme 330 cm³ Fig. 2: Comparison of weight and volme of the inpt filter capacitors C F and of the bck+boost indctors L employed in the prototype of the 5kW three-phase wide inpt voltage range bck+boost PWM rectifier: Physical appearance and volme and weight. modlation methods which are available for the control of the bck and of the boost stage. Based on this, the ripple of the bck+boost indctor crrent is analyzed in section 4. There, the time behavior of the ripple crrent and its envelope are calclated analytically for the different modlation methods. Frthermore, the rms vale of the crrent rippleiscalclatedinanalyticallyclosedforminorderto provide a basis for the estimation of the copper losses of the bck+boost indctor. Finally, the theoretical considerations are verified by simlations (cf. section 5) and by experimental investigations in section 6. 2 Principle of Operation In the following, the basic principle of operation of the system shown in Fig. 1 is discssed briefly. Basedontheinvestigation of the condction states several possibilities for arranging the switching states within one plse period, reslting in different modlation methods are analyzed. De to the phase symmetry of the converter strctre and based on the assmed symmetry of the mains voltage system, the investigation can be limited to a π 6 -wide interval of the mains period. In the case at hand we will consider a combination of the mains phase voltages N,R > 0 > N,S > N,T (1) being valid within the mains angle interval (0; π 6 ), in case the mains voltage N,i is defined as N,R = ÛN cos(ωn t), N,S = ÛN cos(ωn t 2π/3), N,T = ÛN cos(ω N t +2π/3). For the characterization of a switching state of the system we se the combination j =(s Rs Ss T ) of the phase switching fnctions s i. There, the switching fnction does define the switching state of the corresponding power transistor, where s i = 0 denotes the off-state, and s i = 1 denotes the on-state. In Fig. 3 the condction states of the bck stage are given for the considered mains interval (cf. (1)). For achieving a resistive fndamental mains behavior, i N,i N,i, and for neglecting the fndamental of the inpt filter capacitor crrents (i N,i i U,(1),i ) fndamentals j=(111) = j= j= Fig. 3: Condction states of the bck stage (valid for filter capacitor phase voltage relation according to (1)). The crrent flow is indicated by a bold line, and the power transistors are not explicitly shown for the sake of clearness. and : active switching states, (c): free-wheeling state. C F L (c) i U,(1),i of the discontinos rectifier inpt phase crrents i U,i lying in phase with the corresponding mains phase voltage N,i ( CF,i) havetobeformed. Accordingly,therelative on-times of the power transistors S i of the bck inpt stage have to be set proportional to the instantaneos vale of the mains phase voltages. There, the bck stage otpt crrent I is assmed to be approximately constant and impressed by the bck+boost indctor. With the modlation index M of the bck inpt stage 2 U M [0; 1], 3 UN,l l M = ÎN I = (where Î N denotes the amplitde of the mains phase crrent (fndamental); U denotes the average vale of the otpt voltage of the bck inpt stage, and U N,l l denotes the rms vale of the line-to-line voltage), one receives for the maximm otpt voltage of the bck inpt stage 3 U max = U N,l l M max, (4) 2 where at the case at hand the maximm modlation index is set to M max = 0.9 inordertohaveamargintothe theoretical limit Mmax 0 = 1 (cf. ) for system control. If U max is lower than the reference vale U0 of the system otpt voltage U 0, the boost stage has to be activated, i.e., the on-time and/or dty cycle δ of the boost power transistorhastobesetaccordingto δ =1 Umax U0 δ [0; 1]. (5) Considering an inpt voltage range U N,l l =( ) V and an otpt voltage U 0 = 400 V the operating modes given in Tab. 1 can be distingished. Operating Mode U N,l l M δ Bck+Boost ( ) V Bck ( ) V Table 1: Operating modes of the three-phase bck+boost PWM rectifier for wide inpt voltage range and a controlled otpt voltage of U 0 =400V. In the following section, the different modlation methods (of the bck and of the boost stage) are given which do show different switching losses and different AC side behavior. 3 Modlation Methods There are several possibilities for arranging the system switching states within one plse half period. The reslting different switching state seqences (modlation methods) are depicted in Fig. 4. The active switching states can either be arranged symmetrically (cf. (1), in Tab. 2) or asymmetrically (cf. in Tab. 2) with reference to the middle of the plse period, and the free-wheeling state can be placed in the middle or at the beginning and/or at the end of a plse half period, respectively (1). The different modlation methods are given in the following for amainsinterval (0; π 6 ), for the sake of clearness, the free-wheeling state is shown in bold face. If the switching power losses are assmed to be proportional to the switched crrent I and to the switched voltage, the modlation methods given in Tab. 2 show a ratio of the average vales of switching power losses within one mains period of P (1) : P : P =1: 3:2 (6) for given plse freqency f P. Accordingly, for eqal switching losses plse freqencies showing a ratio f P,(1) : f P, : f P, =1:1/ 3:1/2 (7)

3 Modlation method (1): =0 = /2 Modlation method : =0 = /2 Modlation method : =0 = /2 = = = Table 2: Different switching state seqences (modlation methods) for the bck inpt stage within one plse period. denotes the local time being conted within the plse period, i.e., (0, ). have to be selected [5]. For each switching state j with on-time δ j,aline-toline voltage is switched to the otpt of the bck stage. In Tab. 3 the analytical expressions for the on-times δ j and for the corresponding instantaneos vales of the otpt voltage of the bck stage j are given for a mains phase voltage condition according to (1). j δ j j M ( 1 2 cos sin ) Û N,l l cos( π 6 ) M ( 1 2 cos 3 2 sin ) Û N,l l cos( + π 6 ) 1 M cos 0 Table 3: On-times δ j and otpt voltages j for the switching states j within the mains interval (0; π 6 ). The time behavior of the voltage at the otpt of the bck stage within one plse period is dependent on the selected modlation method (cf. Fig. 4), whereby the bck+boost indctor crrent ripple is inflenced, bt the modlation method does not take any inflence on the average vale of the voltage U appearing at the bck stage otpt, 3 UN,l l U =( δ + δ )=. (8) 2 M In Fig. 6 the behavior of the bck otpt voltage for an otpt power of P 0 =2.5kW@U N,l l = 440 V and for an otpt voltage of U 0 = 400 V is given for modlation method (1).,, δ δ δ δ δ δ δ δ (1) δ Fig. 4: Time behavior of the bck stage otpt voltage within one plse period for different modlation methods and deactivated boost stage (δ = 0, i.e., 0 =const.=u 0 )., If the boost stage has to be activated, i.e. if δ > 0 is valid (cf. (5)), there are different possibilities of placing the switching fnction of the boost power transistor within the plse (half) period, what does take inflence on the voltage applied to the bck+boost indctor. The boost power transistor can either be activated dring the freewheeling state of the bck inpt stage (modlation method (1).1, cf. Fig. 5) or dring the active state of the bck stage (modlation method (1).2, cf. Fig. 5). This effect is clearly shown in Figs. 6 and (c): Trning the boost power transistor on dring the active switching states of the bck stage reslts in a significantly higher crrent ripple of the bck+boost indctor crrent as compared to Fig. 6(c), where the boost transistor is trned on while the bck inpt stage is operating in the free-wheeling state., (1).1, (1).2 Fig. 5: Modlation of the boost stage. Voltage at the otpt of the bck stage and voltage 0 across the boost power transistor for placing the on-time of the boost converter power transistor in the bck stage free-wheeling interval (cf., modlation method (1).1); : operation of the boost converter power transistor shifted by /2 in time as compared to (modlation method (1).2). Therefore, the time behavior of the ripple of the bck+boost indctor crrent is strongly dependent on the coordination of the modlation of the bck and of the boost stage. The ripple time behavior as well as the ripple rms vale are calclated analytically in the following section. 4 Analytically Closed Calclation of the Bck+Boost Indctor Crrent Ripple The crrent in the bck+boost indctor is determined by the voltage at the otpt of the bck stage and by the voltage across the boost power transistor 0 (which eqals the system otpt voltage U 0 for disabled boost stage). One receives for the crrent ripple in the bck+boost indctor (,2 )= 1 L Z tµ,2,1 (tµ ) 0 ( ) d + (,1 ). (9) The local rms vale of the crrent ripple in dependency on the position of the plse interval considered within the mains period can be calclated via = 2 rms(ϕ 1 Z tµ = 1 2 U)= () 2 d = (10) /2 =0 2 [,1 2 3 T tµ,1 + 2,1 + P (,2,1 ) 2,1 + tµ,1 tµ,2 + 2,2 + ( /2,2 ) 2,2 + tµ,2 TP /2 + 2 /2. The global rms vale of the DC crrent ripple within the mains period can be calclated by smmation of the local rms vales within one plse half period, Irms 2 = 1 X 2 rms(). (11) T N If the plse freqency is sbstantially larger than the mains freqency (which is flfilled in the case at hand) the smmation can be replaced by an integration with good approximation, I 2 rms = k Z ϕu,2 1,2,1,1 2 rms( )d. (12) This allows an analytically closed calclation of the global rms vale of the DC crrent ripple.

4 : Operation for disabled boost stage, δ =0. : Boost operating dring active state of bck stage. (c): Boost operating dring free-wheeling state of bck stage. Fig. 6: Bck stage otpt voltage, voltage 0 across the boost power transistor and bck+boost indctor crrent ripple for P 0 U N,l l = 440 V. Voltage scale: 250 V/div; crrent scale: 2 A/div. If we e.g. consider modlation method (1) for deactivated boost stage (cf. Fig. 4 (1)), one receives for the bck+boost indctor crrent ripple at the time instants,i within one plse half period for a mains interval (1) 0 = 0, tµ,1 = 1/L U 0 δ101 /2, (13) tµ,2 = 1/L U 0 δ110 /2+(,1 ), TP /2 = 0. The global rms vale of the DC crrent ripple within one mains period can now be calclated incorporating the relative on-times δ j and the otpt voltages j given in Tab. 3, (10) and (12) as well as the condition concerning the plse freqencies (7); there the integration (12) can be limited to a π 6 -wide mains interval and yields I rms,(1) / n = (14) = M q 8 240π M( ) + M 2 ( π), 5π with n = ÛN,l l Lf P 1 δ, (15) where δ = 0 at the case at hand. For modlation methods and one receives for the global rms vale of the DC crrent ripple I rms, / n = (16) q 3M = 8 180π M + M 2 (180π 135 3), 5π I rms, / n = M p 4 120π 704M + 105M 2 π. (17) 10π In Fig. 7 the reslts of the analytical calclations are compiled and compared with the simlation reslts, where an excellent conformity is given. Therefore, the very complex reslts of an analytical calclation of the global ripple crrent rms vale for active boost otpt stage (δ > 0) are omittedhereforthesakeofbrevity.forthedetermination of the rms vale of the bck+boost indctor crrent ripple for this case one cold refer to the simlation reslts given in Fig. 10. Incorporating (9) one can derive the local time behavior of the crrent ripple in the bck+boost indctor and its envelope for the different modlation methods. In Fig. 8 the time behavior of the bck+boost indctor crrent ripple (i) within a mains period is given for modlation methods (1) and for disabled boost stage and a modlation index M =0.9, Fig. 9 shows the according envelopes max,(i) in dependency on the modlation index M of the bck inpt stage and on the mains angle for inpt voltage condition NORMALIZED RMS-VALUE I rms / n 0,30 0 0,10 (1) SIMULATION RESULTS LINE-LINE VOLTAGE U N,l-l / V Fig. 7: Comparison of the reslts of a simlation (cf. Fig. 10) and of an analytical calclation of the rms vale of the DC crrent ripple I rms,(i) for the different modlation methods (i) in case of deactivated boost otpt stage (δ =0). according to (1). One can see immediately, that modlation method having the free-wheeling state in the middle of one plse half period does partly provide a lower DC crrent ripple. The comparison of Fig. 11 and Fig. 8 again shows the consistence between analytical calclation and simlation reslts. TheenvelopeoftheDCcrrentrippleofmodlation method does approximately eqal modlation method (1) at f P, = 2f P,(1), a figre showing its dependency on the modlation index M andonthemainsangle is i (1) n i n f P,(1) 0 π 2π f P, 0 π 2π Fig. 8: Time behavior of the bck+boost indctor crrent ripple for modlation methods (1) and within one mains period (modlation index M =0.9). The plse freqencies f P,(1) and f P, are set according to (7). The boost stage is not active (δ =0). (1)

5 (1), max n, max n Fig. 9: Envelopes i,max of the normalized local bck+boost indctor crrent ripple i in dependency on the modlation index M for modlation methods (1) and and for a mains phase voltage conditionaccordingto(1)). : modlation method (1), : modlation method ; plse freqencies f P,(1) and f P, are set according to (7). The boost stage is not active (δ =0). π 6 1,0 0,8 f P,(1) M π 6 1,0 0,8 f P, M therefore omitted here for the sake of brevity. The minimm load at which a transition between continos condction mode (CCM) and discontinos condction mode (DCM) occrs can be easily derived employing Fig. 9: in order to ensre CCM, the average vale of the bck+boost indctor crrent I has to remain above the maximm amplitde of the crrent ripple (i) occrring within one mains period. In case of boost converter operation (δ > 0) the crrent ripple does decrease for modlation methods (1).1, and (cf. Fig. 11), hence DCM will not occr at the lower inpt voltage range for the same load condition. 5 Simlation Reslts The time behavior of the bck+boost indctor crrent ripple for the different modlation methods has been analyzed by simlation sing CASPOC r [6] with respect to (7) and the global rms vale of the DC crrent ripple I rms,(i) was determined for the wide inpt voltage range U N,l l = ( ) V for an otpt voltage of U 0 =400Vbycalclating the rms vale online dring the simlation. The reslts are normalized sing (15) and are compiled in Fig. 10. Figre 11 shows the simlation reslts of the time behavior of the bck+boost indctor crrent ripple for the different modlation methods for disabled boost stage: U N,l l =380V,U 0 =400V, i.e., M =0.9, and for boost converter operating: U N,l l = 230 V, U 0 = 400 V, i.e., M =0.9 andδ =. NORMALIZED RMS-VALUE I rms / n 0,3 0,1 (1).2 (1).1 f P, f P,(1) f P, LINE-LINE VOLTAGE U N,l-l / V Fig. 10: Normalized rms vale of the global bck+boost indctor crrent ripple I rms,(i) for the different modlation methods within a wide inpt voltage range. The comparison of the global rms vale of the different modlation methods shows that modlation method (1).1 is advantageos over all other modlation methods within the whole inpt voltage range in case of activated and/or deactivated boost otpt stage. Modlation methods (1) and show the approximately the same rms vale of the DC crrent ripple, bt the plse freqency of modlation method (1) is twice the plse freqency of modlation method for eqal switching losses. As the comparison of modlation method (1).1 and (1).2 shows, the crrent ripple is clearly dependent on placing the switching fnction of the boost power transistor within the plse (half) period: placing the active state of the boost power transistor dring the active switching states of the bck inpt stage (cf. Fig. 5) reslts in a rms vale of the bck+boost indctor crrent ripple being 4.5 times higher in the worst case as compared to modlation method (1).1, where the boost stage power transistor trn-on interval is centered in the free-wheeling interval of the bck inpt stage (cf. Fig. 5). 6 Experimental Reslts In Fig. 12 a comparison of the local and global time behavior of the bck+boost indctor crrent ripple between simlation reslts and experimental reslts is given for P 0 = 2.5kW,U N,l l = 440V,U 0 = 400 V. There is averygoodconformityofthesimlatedandexperimental waveforms. Accordingly, the simlation reslts and/or the theoretical considerations can be considered to provide a sfficiently accrate description of the actal circit behavior (c) (d) Fig. 12: Experimental reslts,(c) and related simlation reslts,(c) for disabled boost stage: Bck stage otpt voltage, voltage across the boost power transistor 0 = U 0 and DC crrent ripple. Local time behavior,; global time behavior within one half mains period (c),(d). Scales: ; 0 in, : 250V/Div; : 2A/Div.

6 NORMALIZED DC CURRENT RIPPLE i/ i n (1) (1) (1) TIME t / s Fig. 11: Time behavior within one mains period of the normalized crrent ripple of the different modlation methods for disabled boost otpt stage (δ = 0) and maximm modlation index M =0.9 whereu N,l l = 380 V,U 0 = 400 V (top), and for boost stage operating at δ = andm =0.9 whereu N,l l =230V,U 0 = 400 V (below). For modlation method the trn-on interval of the boost stage power transistor is centered arond the middle of each plse period. For modlation method the trn-on interval of the boost stage power transistor is placed jst before the end of each plse half period; the switching freqency is twice the bck stage plse freqency and therefore is eqal to modlation method (1) (cf. (7)). 7 Conclsions In this paper, different modlation methods of a threephase three-switch bck+boost nity power factor PWM rectifier are investigated concerning the time behavior and rms vale of the bck+boost indctor crrent ripple. The modlation methods do differ concerning the arrangement of active and passive switching states of the bck inpt stage and the coordination of the switching of the bck inpt stage and the boost otpt stage within a plse interval. The comparison shows that there exists one modlation method which does provide simltaneosly a minimm DC crrent ripple and a minimm inpt filter capacitor voltage ripple at minimm switching losses and/or maximm plse freqency. This optimm modlation method is characterized by the free-wheeling state of the bck inpt stage being placed at the beginning/at the end of one plse half period, and by a trn-on interval of the boost stage power transistor being centered in the free-wheeling interval of the bck stage. De to the simltaneos minimization of inpt capacitor voltage ripple and otpt indctor crrent ripple and/or of AC and DC side behavior there is no way of frther improving the DC side behavior by accepting lower AC side performance. Sch trade-off wold be possible in case the AC and DC side ripple minima wold occr for different modlation schemes and wold help to balance the largely different overall size of the AC side filter capacitors and the DC side filter indctor (cf. Fig.2). So, the only remaining possibility of minimizing the DC side indctor volme is a redction of the indctance as far as possible. However this does reslt in a higher crrent ripple and in a higher sensitivity of the DC side crrent waveform concerning e.g., mains phase voltage nbalances and inaccracies of the applied switching pattern de to, e.g. gate drive delay times or power semicondctor condction voltage drops. (A control concept providing a proper pre-correction of the plse pattern and/or trn-on times of the switches of bck and boost stage will be presented in a ftre paper.) Frthermore, the minimm load at which a transition from CCM to DCM occrs is shifted to higher vales if the indctance is redced. This cold be compensated by activating the boost otpt stage. However, there one has to accept higher switching and/or higher condction losses of the bck and of the boost stage. A redction of the size of the bck+boost indctor of given indctance cold be achieved by magnetically biasing the indctor core by insertion of a permanent magnet. There eddy crrent losses in the permanent magnets are an isse to be considered. Frthermore, a local redction of the bck+boost indctor crrent ripple and/or of the indctance for given ripple amplitde cold be achieved by modlation of the bck stage carrier freqency with six times the mains freqency. Both approaches will be investigated in detail in the corse of the contination of the research. References [1] Bamann, M., Drofenik, U., and Kolar, J. W.: New Wide Inpt Voltage Range Three-Phase Unity Power Factor Rectifier Formed by Integration of a Three-Switch Bck- Derived Front-End and a DC/DC Boost Converter Otpt Stage. Proceedings of the 22 nd IEEE International Telecommnications Energy Conference, Phoenix, Arizona, U.S.A., Sept , pp (2000). [2] Kolar, J. W.: Netzrückwirkngsarmes Dreiphasen-Stromzwischenkreis-Plsgleichrichtersystem mit weitem Stellbereich der Asgangsspannng. Astrian Patent Application A9/2000, filed: Jan. 5, [3] Dahono, P.A., Sato, Y., and Kataoka, T.: An Analysis of the Ripple Components of the Inpt Crrent and Voltage of PWM Inverters. Proceedings of the International Conference on Power Electronics and Drive Systems, Singapore, Feb , Vol. 1, pp (1995). [4] Bamann, M., and Kolar, J. W.: Comparative Evalation of Modlation Methods for a Three-Phase/Switch Bck Power Factor Corrector Concerning the Inpt Capacitor Voltage Ripple. Proceedings of the 32 nd IEEE Power Electronics Specialists Conference, Vancover, Canada, Jne 17 21, pp (2001). [5] Nishida, Y., and Maeda, A.: ASimplified Discontinos-Switching-Modlation for Three-Phase Crrent-Fed PFC-Converters and Experimental Stdy for the Effects. Proceedings of the 11 th IEEE Applied Power Electronics Conference, San Jose, California, U.S.A., March 3 7, pp (1996). [6] CASPOC - Power Electronics and Electrical Drives Modeling and Simlation.