Aalborg Universitet. Published in: IET Power Electronics. DOI (link to publication from Publisher): /iet-pel Publication date: 2015

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1 Aalborg Uniersitet Analysis and Modeling of Circlating Crrent in Two Parallel-Connected Inerters Maheshwari, Ram Krishan; Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Mnk-Nielsen, Stig Pblished in: IET Power Electronics DOI (link to pblication from Pblisher): /iet-pel Pblication date: 2015 Docment Version Early ersion, also known as pre-print Link to pblication from Aalborg Uniersity Citation for pblished ersion (APA): Maheshwari, R. K., Gohil, G. V., Bede, L., & Mnk-Nielsen, S. (2015). Analysis and Modeling of Circlating Crrent in Two Parallel-Connected Inerters. IET Power Electronics, 8(7), General rights Copyright and moral rights for the pblications made accessible in the pblic portal are retained by the athors and/or other copyright owners and it is a condition of accessing pblications that sers recognise and abide by the legal reqirements associated with these rights.? Users may download and print one copy of any pblication from the pblic portal for the prpose of priate stdy or research.? Yo may not frther distribte the material or se it for any profit-making actiity or commercial gain? Yo may freely distribte the URL identifying the pblication in the pblic portal? Take down policy If yo beliee that this docment breaches copyright please contact s at bn@ab.aa.dk proiding details, and we will remoe access to the work immediately and inestigate yor claim. Downloaded from bn.aa.dk on: december 12, 2018

2 Effect of Dead-Time in Interleaed PWM for Two Parallel-Connected Inerters Ramkrishan Maheshwari *, Ghanshyam Gohil, Lorand Bede, Stig Mnk-Nielsen * Dept. of Electrical Engineering Dept. of Energy Technology Indian Institte of Technology, Delhi Aalborg Uniersity New Delhi, India Aalborg, Denmark Tel.: rkmahesh@ee.iitd.ac.in URL: Keywords Parallel-connected inerter, Dead-time, Circlating crrent, Plsewidth modlation. Abstract Parallel-connected inerters are sed for high power application. De to the parallel-connection, there exists a circlating crrent which does not contribte to the ac side crrent. The analysis presented in the paper shows that the circlating crrent is affected by the dead-time. The effect of the dead time on the circlating crrent for the space ector plse width modlation (PWM) and a discontinos PWM is analyzed. The dead-time cases a dc ale of the circlating crrent for the discontinos PWM. A dead-time compensation techniqe is sed for eliminating the dc component of the circlating crrent. Experimental reslts are presented to erify that. Introdction Parallel-connected oltage sorce inerters (VSI) hae seeral adantages, sch as redced crrent ripple, modlarity, improed thermal management, increased power capability, redndancy, easy maintenance, increased efficiency etc. [1]-[8]. The parallel-connected inerters hae a common dclink, and the ac sides of the inerters are connected throgh single-phase chokes as shown in Fig. 1. The parallel-connected inerters are widely sed as a front-end ac-dc conerter for high-power applications [1], [4]. Seeral literatres are aailable on the operation, control, and design of the parallel-connected inerters sed for rectifiers [6], renewable energy systems, actie filters [2], and power systems. The parallel-connected VSI are operated with interleaed plsewidth modlation (PWM). This cases a circlating crrent between the inerters. The circlating crrenoes not contribte to the grid crrent and cases additional losses in the system. An interleaed discontinos PWM (DPWM) is sed in [7] for the parallel-connected inerters. The implementation is done by calclating the dwell time of the oltage ectors which are needed to be applied. The dty cycles are calclated sing the dwell time and then phase shifted by the switching period. This reslts in differenty cycles for a phase of different inerters and cases a low freqency component in the circlating crrent. Similar implementation was sed in [8] for DPWM, and a low freqency circlating crrent is obsered de to difference between the dty cycles of the two inerters in a phase dring a switching period. In this paper, it is shown that the low freqency oscillation in the interleaed DPWM can be eliminated. Howeer, in this process, a dc component is introdced in the circlating crrent. It is shown in the paper that the dc component is de to the dead-time. A deadtime compensation can be sed to eliminate the dc component. In this way, the circlating crrent contains only switching freqency component. Therefore, the circlating crrent filter size can be optimized. Section II describes the case of the circlating crrent. The effect of the dead-time on the circlating crrent is

3 analyzed in Section III. The experimental reslts erifying the analysis are shown in Section IV. Conclsions are presented in Section V. Fig. 1. Parallel-connected inerters. Circlating Crrent The block schematics of the system nder consideration is shown in Fig. 1. The dynamics of the circlating crrent (i o ), which is the aerage of inerter 1 indctor crrents, can be gien by d 1 Rio + L io = ( cm 1 cm2 ) (1) dt 2 where R and L represent the resistance and indctance of the inerter otpt choke. cm1 and cm2 are the common-mode (CM) oltages of the inerter 1 and inerter 2, respectiely. The CM oltage is gien by 1 cmx = ( AxO + BxO + BxO ) x = 1, 2 (2) 3 The circlating crrenepends on the difference of the CM oltages. The CM oltage depends on the PWM strategy sed for the conerter. In addition, the difference of the CM oltage depends on the interleaing angle between the carrier signals for the inerters. The interleaing angle affects the total harmonic distortion (THD) of the inerter otpt crrent also. It is shown in [4] that the minimm THD for the otpt crrent is obtained when the interleaing angle is 180 for the two parallelconnected inerters. Therefore, this paper considers the case of 180 interleaing angle. Different PWM strategies generate different CM oltage. Howeer, in a switching period, if the reference signal for the PWM is the same for both inerters, the CM oltage aeraged oer a switching period will be the same for both inerters and the difference of the aeraged CM oltages will be zero. This reslts in zero circlating crrent aeraged in a switching period according to (1). Howeer, in a practical case when dead time is not neglected there are some cases which reslt in nonzero circlating crrent. The analysis for the CM oltage when the dead time is not neglected is presented in the following section. Effect of Dead-Time on Circlating Crrent In a leg of a two-leel inerter shown in Fig. 2, there is a time delay between the trn-off of the one deice in a leg and the trn-on of the other deice in the same leg. This delay is referred to as the dead-time, and both deices are off dring this time. In the preios section, it is assmed that the dead-time is zero. The effect of the dead-time is analyzed in this section for space ector PWM (SVPWM) and DPWM3. The assmptions made for the analysis are that the crrent is in-phase with the reference oltage and the phase crrents do not change sign in a switching period. Since the

4 crrent is in-phase with the reference oltage, the crrenirection is positie for positie reference oltage, and the crrenirection is negatie for negatie reference oltage. If the crrenirection is positie, the bottom diode of the inerter leg will condcring the dead-time, and the ac terminal oltage will be /2. Similarly, if the crrenirection is negatie, the top diode of the inerter leg will condcring the dead-time, and the ac terminal oltage will be + /2. Fig. 2. A leg of a two-leel inerter. The ac terminal oltages and the difference between the terminal oltages of the phases for SVPWM are plotted in Fig. 3. The dotted cres show the ideal condition withot the dead-time, while the solid lines show the different plots with the dead-time. The point to be noted here is that the reference signals for both inerters are the same and pdated at the same time. If there is no dead-time, it can be shown that the aerage ale of the CM oltage for both inerters is the same and the difference between the CM oltages is zero. Therefore, there is no low freqency component in the circlating crrent. Dring the dead-time, the ac terminal oltage is /2 for phase A and B becase of positie crrent, and the rising edge of the ac terminal oltages are delayed by the dead-time ( ). The opposite is tre for phase C, and the falling edge of the ac terminal oltage is delayed by the dead-time. De to this, the difference between the ac terminal oltages of a phase has different waeform compared to the ideal condition. It can be shown that the time for which the difference between phase A terminal oltages is is eqal to the time for which it is +, and it is eqal to 2t a + which is shown in Fig. 3. This means that the aerage ale of the difference of phase A terminal oltages is zero. Similarly, it can be shown that the aerage ales of phase B and phase C ac terminal oltages difference are zero. This implies that 0 (3) cm 1 cm 2 = Similar analysis can be done for a DPWM. The DPMW3 gien in [5] is chosen for the analysis. The ac terminal oltages, the difference between the ac terminal oltages of the phases, and the circlating crrent for the DPWM3 are plotted in Fig. 4. The figre is plotted for a condition when phase A discontines switching and is clamped to the positie dc-link terminal, and phase C (which was clamped to the negatie dc-link terminal) contines switching. The reference oltage ale of phase B changes its sign from negatie to positie as shown in Fig. 4. Dotted cres in Fig. 4 show the waeform nder ideal conditions withot the dead-time, while the solid cres show the waeform with the dead-time. As described in the preios analysis of the SVPWM with the dead-time, it can be shown that the time, for which the difference between phase B terminal oltages is dc, is eqal to the time for which it is + dc. This means that the aerage ale of the difference between phase B terminal oltages is zero, and the aerage circlating crrent componene to phase B is zero. The same is tre for phase C. Howeer, phase A which has positie reference oltage and positie crrent and when it clamps to positie dc-link terminal, phase A top switch of inerter 1 is switched off at the end of switching period. De to positie crrent in the phase, the rising edge of the ac terminal oltage is delayed becase of the dead-time which is marked

5 t 1 T s t 1 A,ref t 2 t 2 B,ref C,ref t 3 t 3 A 1 O B 1 O CO 1 A 2 O B 2 O C 2 O ta t a A1O A2O t b t 1 t 2 t 1 t b BO 1 B2O t 2 tc t c - CO 1 C2O t 3 t 3 Fig. 3. Difference between the ac terminal oltages of the inerters for SPWM or SVPWM. in Fig. 4 by a red circle. Therefore, the aerage ale of the difference between phase A terminal oltages is not zero and is gien by dc A 1O A2O = t T d s o o ωt= 30,300 Ts where Ts is the switching period. (4) Similar condition will occr for phase B at ωt = 180 and 270 and for phase C at ωt = 60 and 150. De to this, there exists a dc component of the circlating crrent. Similarly, when a phase clamps to a negatie dc-link oltage, that phase bottom IGBT of inerter 2 is switched off at the end of the switching period, and de to the dead-time there is a delay in the falling edge of the ac terminal oltage for the inerter 2. This in trn cases a nonzero aerage difference between the ac terminal oltages. The conditions when it occrs for inerter 2 are for phase A at ωt = 120 and 210, phase B at ωt = 240 and 330, and phase C at ωt = 90 and 360. There are 12 switching periods in a fndamental period (Tf) where the aerage ale of the difference between a phase oltages has the ale of dctd/ts. So the

6 aerage ale of the difference between the common-mode oltages of the two inerters oer a fndamental cycle is gien by 4dc cm 1 cm2 = t T d s o o ωt= 30,300 T s ωt<30 T s ωt>30 T s A,ref Carrier 1 B,ref Carrier 2 C,ref AO 1 B 1 O CO 1 A 2 O td B 2 O C 2 O AO 1 AO 2 B1O B2O C1O C2O Fig. 4. Difference between the ac terminal oltages of the inerters for DPWM3. Therefore, a dead time compensation is reqired to eliminate the dc component. A dead-time compensation techniqe discssed in [9] is sed to remoe the dc component of the circlating crrent Experimental Reslts A two parallel-connected inerters with indctance of the choke in each phase eqal to 6.8 mh (L = 6.8 mh) are spplying a three-phase load of 20 Ω. Since the circlating crrenepends only on the CM oltage, the choice of load does not inflence the circlating crrent. The inerters are operated with dc-link oltage eqal to 500 V. The carrier freqency sed for modlation is eqal to 2.5 khz. The carrier waeforms of the two inerters are 180 phase shifted. The modlation index sed for the experiment is eqal to 1. The sm of the phase crrents of inerter 1, when SVPWM is sed, is shown in Fig. 5(a). The deadtime sed for the experiments is 2 µs. The aerage ale of the sm of the crrents, i.e., three times the

7 circlating crrent is zero. The rms ale of the circlating crrent is 0.88 A. Phase A crrent of inerter 1, inerter 2, and the load crrent are shown in Fig. 5(b). The sm of the phase crrents of inerter 1 for DPWM3 is shown in Fig. 6(a). Since the dead-time of 2 µs is sed, the aerage ale of the sm of the crrents, i.e., three times the circlating crrent is eqal to 3.23 A. Phase A crrent of inerter 1, inerter 2, and the load are shown in Fig. 6(b). A standard dead-time compensation techniqe is sed with DPWM3 and the reslts are shown in Fig. 7. It can be seen that the aerage ale of the circlating crrent is zero. The rms ale of the circlating crrent is 0.77 A. There is a redction of 12.5% in the rms ale of the circlating crrent, and the dc offset is eliminated. ia1 + ib1 + ic1 (a) (b) Fig. 5. (a) Sm of the phase crrents of inerter 1, (b) phase A crrent of inerter 1, inerter2, and the load for SVPWM (m = 1). ia1 + ib1 + ic1 (a) (b) Fig. 6. (a) Sm of the phase crrents of inerter 1, (b) phase A crrent of inerter 1, inerter2, and the load for DPWM3 (m = 1). ia1 + ib1 + ic1 (a) (b) Fig. 7. (a) Sm of the phase crrents of inerter 1, (b) phase A crrent of inerter 1, inerter2, and the load for DPWM3 with the dead-time compensation. Conclsion This paper presents an analysis of the CM oltage for two parallel-connected inerters which cases the circlating crrent. The analysis shows that the aerage ale of the circlating crrent oer a switching period will be zero if the reference oltage signals for both conerters are the same. It means

8 that there will not be any low order harmonics in the circlating crrent in this condition. It is shown that the DPWM with the dead-time cases a dc component in the circlating crrent, and it can be made zero if the dead-time compensation is proided. The experimental reslts are presented to erify the analysis. References [1] Fkda S., Matsshita K.: Control method for parallel-connected mltiple inerter systems, in Proc. 7th Int. Conf. Power Electron. Variable Speed Dries, London, U.K.1998, pp [2] Asiminoaei L., Aeloiza E., Enjeti P. N., and Blaabjerg F.: Shnt actie-power-filter topology based on parallel the interleaed inerters, IEEE Trans. Ind. Electron. ol. 55 no. 3 pp Mar [3] Absara M. A. and Sharkh S. M.: Design and control of a grid-connected the interleaed inerter, IEEE Trans. Power Electron. ol. 28 no. 2 pp Feb [4] Xiaolin Mao, Jain A. K., and Ayyanar R.: Hybrid the interleaed space ector PWM for ripple redction in modlar conerters, IEEE Trans. Power Electron. ol.26 no.7 pp Jly 2011 [5] Haa A.M., Kerkman R. J., and Lipo T. A.: Simple analytical and graphical methods for carrier-based PWM-VSI dries, IEEE Trans. Power Electron. ol. 14 no. 1 pp Jan [6] Zhihong Ye, Boroyeich D., Jae-Yong Choi, and Lee F. C.: Control of circlating crrent in two parallel three-phase boost rectifiers, IEEE Trans. Power Electron. ol.17 no.5 pp Sep 2002 [7] Kn Xing; Lee F. C., Borojeic D., Zhihong Ye, and Mazmder S.: The interleaed PWM with discontinos space-ector modlation, IEEE Trans. Power Electron. ol.14 no.5 pp Sep 1999 [8] Chen T. P.: Circlating zero-seqence crrent control of parallel three-phase inerters, IEE Proc. Electric Power Applications ol. 153 no. 2 pp March 2006 [9] Holmes G. and Lipo T.: Plse Width Modlation for Power Conerters, Principles and Practice, ser. IEEE Press Series on Power Engineering. New York: Wiley-Interscience 2003