Reduction of DC-link current harmonics for Three-phase VSI over Wide Power Factor Range using Single-Carrier-Comparison Discontinuous PWM

Transcription

1 Reduction of DC-link current harmonics for Three-phase VSI oer Wide Power Factor Range using Single-Carrier-Comparison Discontinuous PWM Koroku Nishizawa, Jun-ichi Itoh, Akihiro Odaka, Akio Toba, and Hidetoshi Umida Nagaoka Uniersity of Technology 63- Kamitomioka-cho, Nagaoka city Niigata, Japan Tel., Fax: +8 / (258) koroku_nishizawa@stn.nagaokaut.ac.jp, itoh@os.nagaokaut.ac.jp URL: Fuji Electric Co., Ltd. Fuji-cho, Hino city Tokyo, Japan Tel.: +8 / (42) Fax: +8 / (42) odaka-akihiro@fujielectric.com, toba-akio@fujielectric.com, umida-hidetoshi@fujielectric.com URL: Keywords «DC-link current harmonics», «Three-phase oltage source inerter», «Discontinuous PWM» Abstract This paper proposes a noel discontinuous PWM (DPWM) in order to reduce dc-link current harmonics of a oltage source inerter (VSI) oer wide load-power-factor range. This modulation method, which requires only one carrier, contributes to a lifetime extension of smoothing capacitors in a motor drie system. Furthermore, by realizing this modulation method with only one carrier, a high cost hardware such as a field-programmable gate array (FPGA) is not necessary. By adding an offset to oltage references of conentional DPWM, and shifting two unclamped oltage references in eery half control period, the dc-link current harmonics are reduced een when load power factor changes. It is clarified by experiments that the proposed DPWM reduces the dc-link current harmonics by 8.4% at most at modulation index of.75 and load power factor of.89. I. Introduction Three-phase AC motors are widely used in both the industrial and household applications []-[7]. Recently, lifetime extension of AC motor drie systems has been actiely researched [8]-[9]. Generally, electrolytic capacitors are used as a smoothing capacitor in dc-link of three-phase VSI. The smoothing capacitor absorbs inerter dc-link current harmonics, and eentually deteriorates as a result of exothermic reaction of its electrolyte. Therefore, the lifetime of the smoothing capacitor is the most critical issue for the lifetime extension of the whole motor drie system. In order to extend the lifetime of the smoothing capacitor, a method applying film capacitors instead of the electrolytic capacitor as the smoothing capacitor has been proposed []. Howeer, this method makes the motor drie system bulkier because of low energy density of the film capacitors compared to the electrolytic capacitors. On the other hand, it is also possible to extend the lifetime of the smoothing capacitor by reducing the dc-link current harmonics of VSI. Therefore, modulation methods of VSI, which reduce the dc-link current harmonics of VSI, hae been also proposed [8]-[9], []. In [8]-[9], double carriers, which consist of an original triangular carrier and a second triangular carrier whose phase is opposite to the

2 first one, are used for the modulation as a double-carrier-comparison pulse width modulation (PWM). In particular, the dc-link current harmonics are reduced by minimizing the zero ector period by comparing only one oltage reference with the inerse triangular carrier and comparing the other oltage references with the original carrier. Howeer, this method leads to a constraint of the digital hardware due to the generation of the inerse triangular carrier. Furthermore, when the load power factor becomes lower than.866, the dc-link current harmonics cannot be reduced by these methods. As another approaches to minimize the dc-link current harmonics, a noel space ector PWM (SVPWM) has been proposed in []. In this SVPWM, the output oltage space ectors are selected in order that the zero ector period is shortened. Besides, by changing the output oltage space ectors according to polarities of output phase currents, the SVPWM in [] can adapt to the ariation of the load power factor. Howeer, the employment of the proposed SVPWM also leads a constraint of the digital hardware because the SVPWM needs to not only compare the on-duties of the selected output oltage space ectors with single carrier but also decide the gating signals based on the carrier comparison results in order to realize the optimized combinations of the output oltage space ectors for the reduction of the dc-link current harmonics. This paper proposes a noel carrier-comparison DPWM which uses only one carrier in order to reduce the switching-frequency-order dc-link current harmonics of VSI and eliminates the need of the complex digital hardware. In other words, the proposed DPWM can be simply implemented by the general-purpose micro-computer for power electronics. In order to use just only one carrier, two unclamped phase oltage references of the conentional DPWM are shifted in eery half control period. This leads to a smaller fluctuation of the dc-link current around its aerage alue, which reduces the dclink current harmonics. Furthermore, by adding an offset to all oltage references of the DPWM in order to optimize the phase of clamped oltage reference and its clamped alue, the dc-link current harmonics are reduced een when the load power factor aries. This paper is organized as follows; first, the reduction method of the dc-link current harmonics by using the noel oltage references of the DPWM is introduced. Next, the mechanism to adapt the ariation of the load power factor is explained. Finally, the effectieness of the proposed DPWM is confirmed by simulation and experiment. II. Proposed PWM method to reduce dc-link current harmonics of VSI A. Conentional discontinuous PWM Fig. shows a three-phase VSI employed in the motor drie system. The three-phase VSI consists of three half bridges. If the semiconductor switching deices are assumed to be ideal, the conduction status of each half bridge can be represented by the binary switching functions as s x, (Sxp : ON, Sxn : OFF), ( x u,, w) ()., (Sxp : OFF, Sxn : ON) i con i in i C S up S p S wp E dc + Cdc i u i u Motor i w w wu load S un S n S wn Fig.. Three-phase two-leel VSI employed in motor drie system.

3 Output phase currents of the VSI at steady state operating condition can be expressed as iu I i I iw I m m m cos 2 ft cos2 ft 3 cos2 ft 3 (2), where, I m is the maximum alue of the output phase current, f is the fundamental frequency, and φ is the load power factor angle, i.e. the phase difference between the phase oltage and phase current, respectiely. Fig. 2 shows the normalized oltage references of the continuous PWM (CPWM) and DPWM and an offset for the DPWM at the modulation index of.8. These oltage references of the DPWM are obtained by adding the offset offset to the oltage references of the CPWM [2]. The oltage references of the CPWM and DPWM and the offset are expressed as u w.cpwm.cpwm.cpwm m cos 2 ft m cos 2 ft m cos 2 ft 3 3 (3),, x u, w (4), x. DPWM x.cpwm offset, offset and max min max min max[ min[ if if max min u.cpwm u.cpwm, <, min max,,.cpwm.cpwm,, w.cpwm w.cpwm ] ] (5), where, m is the modulation index. Normalized oltage references [-] x.cpwm x.dpwm offset u w deg. 2 ft [deg.] (zoomed at Fig. 3 and Fig. 4) Fig. 2. Normalized oltage references of CPWM, conentional DPWM and offset at m =.8.

4 Fig. 3 shows the zoomed-in waeform of the dc-link current of VSI i in and the switching functions s u ~ s w with the conentional DPWM at the modulation index of.8, the phase angle of 5 degrees and the unity load power factor. The instantaneous alue of the dc-link current of VSI is the superposition summation of the switched current pulses from each phase leg [3] and calculated as i DC sx ix. in (6). xu,, w The shaded area in the instantaneous waeform of the dc-link current of VSI in Fig. 3 indicates the time integral of the difference between the instantaneous alue and aerage alue of the dc-link current of VSI. This difference is absorbed by the smoothing capacitor. Therefore, the shaded area in Fig. 3 expresses the instantaneous root-mean-square (RMS) alue of the current flowing into the smoothing capacitor, which is calculated as i C. RMS 2 T i T s i and i in. RMS in in. RMS T s s 3 m I 4 m i T 2 in s cos Ts i 2 in dt (7). where, T s is the control period, I m is the maximum alue of the output phase current of VSI and φ is the load power factor angle. It is obious that the shaded area, expressing the dc-link current harmonics of VSI, becomes larger when the fluctuation of the dc-link current around its aerage alue is large [4]. In the case of the conentional DPWM, the center of the gate pulses is the same as the center of the control period. As a result, the oerlapping period of the gate pulses becomes the longest at any time. This leads to the large fluctuation of the dc-link current around its aerage alue, i.e. the large dc-link current harmonics. B. Proposed discontinuous PWM The operations of the proposed DPWM change corresponding to the load power factor. At the unity load power factor, two unclamped oltage references of the conentional DPWM are shifted in eery half control period to reduce the dc-link current harmonics. On the other hand, when the load power factor becomes low, first, three oltage references is added with an offset, then, two unclamped oltage references are shifted in half control period. Triangular carrier u.dpwm.dpwm - w.dpwm s u s s w i in i u +i i u i in T s Fig. 3. Zoomed-in waeforms of dc-link current and switching functions with conentional DPWM at m =.8, 2πft = 5 deg., cos φ =.

5 B-I. Operation at unity load power factor Fig. 4 shows the zoomed-in waeform of the dc-link current of VSI and the switching functions with the proposed DPWM at the modulation index of.8, the phase angle of 5 degrees and the unity load power factor. In the proposed DPWM, the fluctuation of the dc-link current around its aerage alue is reduced by displacing the center of the gate pulses. Note that the proposed oltage references are realized based on the premise that the oltage references can be updated at the positie peak and negatie peak of the carrier by the general-purposed micro-computer for power electronics. In particular, the oltage references of the proposed DPWM for the reduction of the dc-link current harmonics are generated as follows:. Splitting the control period into DOWN and UP periods. 2. Shifting two oltage references, other than the clamped oltage reference of the DPWM, to reach or - one after the other in these periods as In DOWN period: a b 2 2 In UP period: a b 2 2 if if if if if if if if, <., <., <., <. (8) (9) where, a and b indicate phases whose the oltage references are not clamped, i.e. the u and phases in Fig. 4 for example, and are the conentional oltage references, a and b are the shifted oltage references in the proposed DPWM. Note that the aerage alues of these shifted oltage references in the control period are as same as those of the conentional oltage references. With these shifted oltage references, the oerlapping period of the switching functions is shortened. Consequently, this leads the reduction of the dc-link current harmonics. u.dpwm.dpwm w.dpwm - Triangular carrier u w DOWN period UP period s u s s w i in i u +i i u i i in Fig. 4. Zoomed-in waeforms of dc-link current and switching functions with proposed DPWM at m =.8, 2πft = 5 deg., cos φ =. T s

6 Howeer, note that the reduction effect on the dc-link current harmonics of the proposed DPWM depends on the load power factor because the instantaneous alue of the dc-link current of VSI depends on the output phase currents. Therefore, it is necessary to deal with the ariation of the load power factor in order to reduce the dc-link current harmonics of VSI oer wide power factor range, which is a typical requirement of the motor drie system. B-II. Operation oer wider load-power-factor range Table I shows the definitions of the sectors which are determined by the combination of the detected output phase currents of VSI. These sectors (A~F) are necessary to recognize the conditions of the output phase currents. Fig. 5 shows the conentional and shifted oltage references at the modulation index of.8 and the load power factor of.966 (φ = 5 deg.). In order to employ the proposed DPWM to any condition of the load power factor, first, three conentional oltage references x.dpwm (x = u,, w) are added with the offset offset.2 to obtain the oltage references with the offset x.pdpwm. Note that the offset alue offset.2 is optimized according to the conditions of the output phase currents and the clamped phase. In the case of sector B, for example, where i u and i are positie and i w is negatie, the switching function of w phase must be to obtain the minimum fluctuation of the dc-link current around its aerage alue. If the switching function of w phase becomes during sector B, the instantaneous alue of the dc-link current becomes negatie, which leads to the large fluctuation of the dc-link current around its aerage alue, i.e. the large dc-link current harmonics. Next, two unclamped phase oltage references are shifted in eery half control period according to (8)-(9), which results in the oltage references x of the proposed DPWM. TABLE I SECTOR DEFINITIONS OF PROPOSED DPWM. Sector Current polarity (P: Positie, N: Negatie) Optimized clamped alue i u i i w K OCV A P N N B P P N - C N P N D N P P - E N N P F P N P - A B Proposed Sector E C D Output phase currents F A i u i i w Voltage references of conentional DPWM u.dpwm.dpwm w.dpwm Adding offset offset.2 Voltage references with at = 5 deg. offset.2 u.pdpwm.pdpwm w.pdpwm Voltage references of proposed DPWM at = 5 deg. u w 2 ft Fig. 5. Proposed oltage references at m =.8, cos φ =.966 (φ = 5 deg.). x.pdpwm are generated by adding an offset offset.2 to x.dpwm in order to keep the clamped period of the oltage reference at each proposed sector. The oltage references of the proposed DPWM x are finally generated by shifting two unclamped oltage references of x.pdpwm in eery half control period.

7 F A Proposed Sector B C D Output phase currents E F i u i i w Voltage references of conentional DPWM u.dpwm.dpwm w.dpwm Adding offset offset.2 Voltage references with at = 45 deg..pdpwm offset.2 w.pdpwm u.pdpwm Voltage references of proposed DPWM at = 45 deg. u w Applying conentional DPWM 2 ft Fig. 6. Proposed oltage references at m =.8, cos φ =.77 (φ = 45 deg.). In gray periods, the oltage references of the conentional DPWM are applied to aoid the oermodulation operation due to adding the offset.2. In the proposed DPWM, by adding the offset to all oltage references of the conentional DPWM, the phase of the clamped oltage reference and its clamped alue are adjusted optimally for the reduction of the dc-link current harmonics of VSI at each proposed sector. The oltage references x.pdpwm of the proposed DPWM and the offset offset.2 adding to the conentional oltage references x.dpwm is calculated as x.pdpwm and x.dpwm offset.2 K K K offset.2 OCV OCV OCV, x u,, w u.pwm.pwm w.pwm, if sector A,D, if sector B, E, if sector C,F. (), where, K OCV is the optimized clamped alue of the oltage reference at each proposed sector, as shown in table I. Fig. 6 shows the proposed oltage references at the load power factor of.77 (φ = 45 deg.). When the load power factor is lower than.866 (φ < 3 deg.), the periods when the absolute alues of the proposed oltage references x.pdpwm becomes more than due to adding the offset offset.2 at each sector. Therefore, the oltage references x.dpwm of the conentional DPWM are applied in these periods as shown in the shaded areas in Fig. 6, in order to aoid the oermodulation operation. Accordingly, the phase of the clamped oltage reference is not the optimized alue for the reduction of the dc-link current harmonics in these periods. Thus, the shifting of two unclamped oltage references in eery half control period are not performed in these periods. III. Simulation and experimental results The performances of the conentional and proposed DPWM are inestigated by simulation and experiment. The switching frequency of VSI is khz. In the experiment, a three-phase induction motor (MVK85A-R, Fuji Electric Co., Ltd.), the rated power of which is 3.7 kw, is used as a test motor. The load power factor is aried from.259 to.89, in the case of driing mode, by controlling the torque of a load motor.

8 Fig. 7 shows the u-phase oltage reference, the measured line oltage, the dc-link current and u- phase output line current of VSI with each modulation method at the modulation index of.75 and the load power factor of.89. When the load power factor is.89, the applying interal of the proposed DPWM is long and two unclamped oltage references are shifted in half control period as shown in Fig. 7(b). It is confirmed that the width of the step change in the dc-link current of VSI is reduced by applying the proposed DPWM. On the other hand, the switching-frequency-order harmonic components of the output line oltage are worsened by the proposed DPWM as it could be predicted since an instantaneous oltage error during the control period is higher with the gate pulses of the proposed DPWM than those with the conentional DPWM. Fig. 8 shows the harmonic components of the dc-link current of VSI under the same conditions as Fig. 7. The alue of % at the ertical axis means the maximum alue of the output phase current. By applying the proposed DPWM, the switching-frequency-order harmonic components of the dc-link current is reduced by 5.49%. Fig. 9 shows the simulation and experimental results of the dc-link current harmonics with each modulation method when the modulation index and the load power factor is aried respectiely. Note that the dc-link current harmonics are ealuated as I in(p.u.), which is the RMS alue of the dc-link current (I in.rms) normalized by the maximum alue of the output current (I m) of VSI. 2 I in. RMS I in(p.u.) i in. k (), I m I m k 2 where, k is the harmonic order and i in.k is the k-order component of the dc-link current harmonics. The fundamental component of the dc-link current harmonics is 5 Hz at rated load. The harmonic u.dpwm [2. -/di.] u [2. -/di.] u [5 V/di.] u [5 V/di.] i in [2 A/di.] i in [2 A/di.] i u [2 A/di.] [ ms/di.] i u [2 A/di.] [ ms/di.] (a) With conentional DPWM. (b) With proposed DPWM. Fig. 7. u-phase oltage reference, line oltage, dc-link current and u-phase output line current of VSI at m =.75 and cos φ =.89. Input current [%].. I 2.9 % in(p.u.) =.42 [p.u.] I in(p.u.) =.336 [p.u.] 5.4 %.. Input current [%].. Frequency [Hz] Frequency [Hz] (a) With conentional DPWM. (b) With proposed DPWM. Fig. 8. Harmonic components on dc-link current of VSI at m =.75 and cos φ =.89 (under same conditions of Fig. 7). The fundamental frequency is 3 Hz. By the employment of the proposed DPWM, the switching-frequency-order harmonic component is reduced by 5.5%.

9 THD of i u [%] I in(p.u.) [p.u.] I in(p.u.) [p.u.] components of the dc-link current up to 2 th -order of the switching frequency are considered in this ealuation because the switching frequency harmonic components of the dc-link current with the conentional and proposed DPWM aboe 2 th -order are small and comparable as shown in Fig. 8. The dc-link current harmonics are reduced oer entire range of the modulation index and the load power factor by applying the proposed DPWM. At the load power factor of.89, i.e. the high load power factor, the alue of I in(p.u.) is reduced by 8.4% at most by applying the proposed DPWM compared to that of the conentional DPWM. It is also confirmed that as the load power factor becomes lower, the dc-link current-harmonic-reduction effect of the proposed DPWM decreases because the applying interal of the proposed DPWM is short as shown in Fig. 6. Howeer, when the load power factor is low, the dc-link current harmonics are also low. On the other words, the large dc-link current harmonics in the case of the high load power factor which can be drastically reduced by applying the proposed DPWM should be focused. Fig. shows the total harmonic distortion (THD) of the u-phase output line current at the load power factor of.89. The harmonic components of the u-phase output line current up to 4th-order of the fundamental frequency are considered in this ealuation. Although the proposed DPWM reduces the dc-link current harmonics, it also worsens the output oltage harmonics as a trade-off as shown in Fig. 7. Howeer, the worsened components by the proposed DPWM is the switching-frequency-order harmonic components. This means that the impacts of the employment of the proposed DPWM on the low-order harmonic components of the output line oltage and phase current is low. Therefore, the load current qualities of the conentional and proposed DPWM are comparable..5.4 Lines : Sim. results Plots : Exp. results cos φ =.89 (φ = 35 deg.).5.4 Lines : Sim. results Plots : Exp. results cos φ =.89 (φ = 35 deg.) cos φ =.77 (φ = 45 deg.) cos φ =.259 (φ = 75 deg.).2. cos φ =.77 (φ = 45 deg.) cos φ =.259 (φ = 75 deg.) Modulation index m [-] (a) With conentional DPWM Modulation index m [-] (b) With proposed DPWM. Fig. 9. Simulation and experimental results of dc-link current harmonics with each modulation method when modulation index and load power factor are aried respectiely cos φ =.89 (φ = 35 deg.) Conentional DPWM (f sw = khz) Proposed DPWM (f sw = khz) Modulation index m [-] Fig.. Measured total harmonic distortion of u-phase output line current with each modulation method at cos φ =.89. The switching frequency is khz.

10 IV. Conclusion This paper proposed the noel DPWM to reduce the dc-link current harmonics of VSI oer entire load power factor range. This modulation method, which required only one carrier, contributed to the long lifetime of the smoothing capacitor in the motor drie system. By realizing this modulation method with only one carrier, high cost hardware such as FPGA was not necessary. The dc-link current harmonics were reduced by adding an offset to the all oltage references of the conentional DPWM, and shifting two unclamped oltage references in eery half control period. These optimized the phase of the clamped oltage reference and its clamped alue for the reduction of the dc-link current harmonics of VSI een when the load power factor aried. The effectieness of the proposed DPWM was confirmed by the simulation and experiment. These results confirmed that the dc-link current harmonics were reduced by 8.4% at most at the load power factor of.89 by applying the proposed DPWM. Moreoer, it was also confirmed that the dc-link current harmonics were reduced oer entire range of the load power factor. References [] M. Fleischer, and K. Kondo, Reduced Model Identification and Parameter Estimation for Traction Drie- Trains, IEEJ Trans. Ind. Appl., ol. 4, no. 4, pp , 25. [2] K. Tobari, and Y. Iwaji, Quick-Response Technique for Simplified Position Sensorless Vector Control in Permanent Magnet Synchronous Motors, IEEJ Trans. Ind. Appl., Vol. 4, No. 5, pp , 25. [3] T. Nagano, and J. Itoh, Parallel Connected Multiple Motor Drie System Using Small Auxiliary Inerter for Permanent Magnet Synchronous Motors, IEEJ Trans. Ind. Appl., Vol. 4, No., pp. 4-48, 24. [4] K. Sun, Q. Wei, L. Huang, and K. Matsuse, An Oermodulation Method for PWM-Inerter-Fed IPMSM Drie With Single Current Sensor, IEEE Trans. Ind. Electron., Vol. 57, No., pp , 2. [5] Takashi Yamaguchi, Yugo Tadano, and Nobukazu Hoshi, Using a Periodic Disturbance Obserer for a Motor Drie to Compensate Current Measurement Errors, IEEJ Trans. Ind. Appl., Vol.4, No.4, pp , 25. [6] Ryoh Saitoh, Yuki Makaino, and Takumi Ohnuma, Adaptie Signal Injection Method Combined with EEMFbased Position Sensorless Control of IPMSM Dries, IEEJ Trans. Ind. Appl., Vol.4, No.4, pp , 25. [7] Keitaro Ueda, Shigeo Morimoto, Yukinori Inoue, and Masayuki Sanada, A Noel Control Method in Fluxweakening Region for Efficient Operation of Interior Permanent Magnet Synchronous Motor, IEEJ Trans. Ind. Appl., Vol.4, No.5, pp , 25. [8] J. Hobraiche, J.-P. Vilain, P. Macret, and N. Patin, A New PWM Strategy to Reduce the Inerter Input Current Ripples, IEEE Trans. Power Electron., ol. 24, no., pp. 72-8, 29. [9] T. D. Nguyen, N. Patin, and G. Friedrich, Extended Double Carrier PWM Strategy Dedicated to RMS Current Reduction in DC Link Capacitors of Three-Phase Inerters, IEEE Trans. Power Electron., ol. 29, no., pp , 24. [] Marko Hinkkanen, and Jorma Luomi, Induction Motor Dries Equipped With Diode Rectifier and Small DC-Link Capacitance, IEEE Trans. Ind. Appl., ol. 55, no., pp , 28. [] K. Nishizawa, J. Itoh, A. Odaka, A. Toba, and H. Umida, Reduction of Input Current Harmonics based on Space Vector Modulation for Three-phase VSI with aried Power Factor, IEEE ECCE26 Conf., EC-38, 26. [2] M. H. Bierhoff and F. W. Fuchs, DC-Link Harmonics of Three-Phase Voltage-Source Conerters Influenced by the Pulsewidth-Modulation Strategy-An Analysis, IEEE Trans. Ind. Appl., ol. 55, no. 5, pp , 28. [3] B. P. McGrath, and D. G. Holmes, A General Analytical Method for Calculating Inerter DC-Link Current Harmonics, IEEE Trans. Ind. Appl., Vol. 45, No. 5, pp , 29. [4] T. Takeshita, Output Voltage Harmonics Suppression of Matrix Conerters Using Instantaneous Effectie Values, IEEE ECCE2 Conf., 27_839, 2.