High Power Amplifier with Maximized Efficiency

Transcription

1 High Power Amplifier with Maximized Efficiency by Bumjin Kim Senior Project ELECTRICAL ENGINEERING DEPARTMENT California Polytechnic State University San Luis Obispo 2007

2 i TABLE OF CONTENTS Section Page Acknowledgements. iv I. Introduction... 1 II. Background.. 2 III. Requirements.. 5 IV. Theory. 7 V. Simulation.. 11 VI. Construction.. 28 VII. Testing. 30 VIII. Conclusions and Recommendations IX. Bibliography Appendices A. Parts List B. Cost and Time Schedule Allocation... 58

3 ii LIST OF TABLES AND FIGURES Table Page 1. Initial Design Goals Element values for matching networks Summary of Final Power Amplifier Result Power Level of Harmonics. 43 Figures 1. Basic Topology of Power Amplifier 7 2. Output Network of Third Harmonic Peaking Voltage and Current Waveforms IV curve of GaN transistor S-parameter of GaN transistor, V DS = 28V, I DQ =100mA Smith Chart reflection coefficient selector for Load and Source Pull Analysis Result of Load and Source Pull Analysis Smith Chart Utility on ADS for matching technique Line Calc feature on ADS ADS Amplifier Design Simulation Template Final Schematic of Power Amplifier Result of Final Schematic of Power Amplifier. 21

4 iii 13. Result of Power Sweep Resonator for Class F Operation Result of Class F Power Amplifier Schematic of Layout Layout of Power Amplifier Power Amplifier Test Set up Block Diagram S-parameter of 3 db attenuator S-parameter of 6 db attenuator S-parameter of High Power attenuator S-parameter of cascaded High Power attenuator and 20-dB attenuator Final Set Up of Power Amplifier Efficiency and PAE as a function of Vds Power Sweep Power Level of Third Harmonic 42

5 iv ACKNOWLEDGEMENTS Very special thanks go to the professors at Cal Poly, who assisted me in this very challenging project. This project could not have been successfully completed without the assistance of Dr. Cheng Sun, Dr. Dennis Derickson, and Dr. Dean Arakaki. I am grateful for their support.

6 1 INTRODUCTION As the wireless communication becomes ever more preferable, there has been an increased attention and demand for low-cost, high-efficiency, and compact systems. Among all the necessary parts involved in the wireless communication systems, RF power amplifier is known to be one of the most critical building blocks in the signal transmitters and is the most power-consuming component in the system. Thus, there has been a quite a bit of research on achieving a very efficient power amplifier. I have chosen to design and build an efficient high power amplifier that operates in the microwave frequency range. The final design will be entered into the Power Amplifier Design Contest hosted by IEEE MTT-S held during the International Microwave Symposium This report covers exclusively the progress of the project from the given requirements to the actual testing and verifications.

7 2 BACKGROUND Power Amplifier In general, a power amplifier uses a DC power supplied by DC supply to amplify an RF output power. Basically, a power amplifier is composed of an active device, usually a single bipolar junction transistor (BJT) or a field effect transistor (FET), DC feed, output-matching network, and input-matching network. The active device acts as a current source driven by the appropriate DC bias and the input signal. The input and output matching networks optimizes the source and the load to the transistor impedances to provide maximum gain. The overall efficiency of the transistor is defined as the ratio of RF power received by the load to the DC power fed into the amplifier. On top of the efficiency measurement of the power amplifier, another important parameter for high efficient power amplifier is power added efficiency (PAE). Power added efficiency is a measurement of maximum output RF power to input RF power over the DC power fed into the amplifier. Thus, it is important to be able to transfer the maximum amount of DC power to the load as RF power. Class F Amplifier Generally, power amplifiers are categorized by different classes of amplifiers (A, B, AB, C, D, E, F, F -1, and S). The classes of operation differ in method of

8 3 operation, efficiency, linearity, and power-output capability. The classes are categorized according to the conduction angle of the transistor. If the conduction angle of the drain/collector of the transistor is 180 degrees, then the amplifier is said to be class A. If the conduction angle is between 90 and 180 degrees, then the amplifier is said to be class AB and so on. As the conduction angle of the drain/collector of the transistor decreases, the efficiency of the amplifier increases. For example, the maximum ideal efficiency of class A amplifier is 50% while the ideal efficiency of class B is 78.5%. However, as the efficiency of the amplifier increases, the linearity of the amplifier decreases at the same time. So the tradeoff exists. Of all different classes of amplifiers, class F is recognized as the most efficient. Ideally, the efficiency of the amplifier can be increased from 50% to the maximum of 100% by class F topology. The class F amplifier achieves such high efficiency by using harmonic resonators in the output network to shape the drain/collector waveforms such that the load appears to be a short at even harmonics and an open at odd harmonics. The drain/collector voltage waveform includes one or more odd harmonics to approximate a square wave, whereas the drain/collector current waveform includes one or more even harmonics to approximate a half a sine wave. Because there is no overlap between the drain/collector voltage and current waveform, a maximum drain efficiency of 100% can be achieved. A more detailed description of the theory of class F amplifier will be discussed in the later sections.

9 4 GaN Transistor Realistically, the efficiency of the amplifier is limited by the characteristics of the transistor. The maximum efficiency of 100% of a class F amplifier can only be achieved by assuming that the transistor is an ideal current source. Several different transistors were designed and tested. Among the many different device types, a GaN HEMT seems to be promising for high power amplifiers. Gallium Nitride device has a very large band gap which permits them to be operated at high drain voltages for high power density. Thus, smaller devices can be used to achieve a given power level.

10 5 REQUIREMENTS Before the actual design of a high power amplifier, initial design goals must be defined. The specifications set by the PA design competition are the following: The power amplifier design may use any type of technology, but must be the result of student effort both in the amplifier design and fabrication. The PA mechanical design should allow for internal inspection of all relevant components and circuit elements. The RF ports should be standard coaxial connectors, type N or SMA. The PA must operate at a frequency of greater than 1 GHz but less than 20 GHz, and have an output power level of at least 5 Watts, but less than 100 Watts. All amplifiers should require less than 25 dbm of input power to reach the output level required for maximum efficiency. Amplifier entries should be submitted with measured data, including DC supply requirements, frequency, RF drive, output power, and PAE. PAE will be defined as (RFout-RFin)/DC. Measurements will be under CW operation at room ambient conditions into a 50 Ohm load. Only the power at the fundamental CW frequency will be included in the measurement of output power.

11 6 The decision will be based solely on the amplifier s power added efficiency measured during official testing at IMS2007. Award certificates will be presented to all participants at the Student Awards Luncheon. The decision of the judges will be final. As the above describes, the specifications have wide ranges. Thus, more detailed and concise design goals must be chosen. Initial design goals are shown in table 1 below. Table I. Initial Design Goals Frequency 2 GHz Pin 25 dbm Max Pout 39 dbm Gain 14 db PAE Maximum (>60%) The goals are chosen based on the expected performance of a transistor. Since the transistor that will be used for this project is chosen to be a GaN HEMT transistor provided by CREE, the initial goals are developed from the datasheet of the transistor. According to the datasheet, the transistor seems to offer the highest efficiency at operating frequency of 2 GHz. At that frequency, the small-signal gain of the transistor is typically around 16 db. This is plenty of gain for the desired design goal. Therefore, the initial goals shown above are reasonable start of the design process.

12 7 THEORY As the introduction section indicates, there are various types of power amplifiers. Designers must choose what type to use based on the application. The one that is chosen for this project is Class F amplifier along with GaN transistor. There are further researches currently going on to further realize the qualities of GaN transistor. Thus, the material that s already been covered in the background section is the brief description of the characteristics of GaN transistor and would suffice for the purpose of this report. Instead this section of the report will cover the operation of Class F amplifiers in more detail. The figure above shows the basic topology of a power amplifier. As the figure shows, the power Figure 1. Basic Topology of Power Amplifier amplifier is composed of four most important components: DC feed through RF Choke, transistor, input matching network, and output matching network. It is the designer s choice to choose the type of transistor and to design input and output matching networks according to the applications. For Class-F power amplifiers, many researches have been done focusing on the output matching network. As indicated earlier, Class-F amplifiers use harmonic resonators at the drain of the transistors to trap infinite number of

13 8 harmonics to eventually eliminate the overlap between the voltage and the current waveforms. However, due to increased components and increased parasitic considerations, many current theologies only consider second and third harmonics (method called Third Harmonic Peaking). The figure above depicts the output network of typical third harmonic peaking. The pair of parallel tuned LC oscillation is set up to resonate at the fundamental and the third harmonics. The L3, C3 resonator Figure 2. Output Network of Third Harmonic Peaking is designed to resonate at the third harmonic, resulting in blocking out the third harmonic resonant from being transmitted to the load while passing the second harmonic. The L, C 0 0 resonator provides optimum load at the fundamental frequency. By the insertion of the third harmonic peaking, the drain voltage waveform transforms from a perfect sinusoidal waveform to a distorted square waveform, and the drain current waveform transforms to a distorted half-sinusoidal waveform. Figure 3. Voltage and Current Waveforms

14 9 As the above figure indicates, as more and more number of harmonics is added to the drain of the transistor, the voltage waveform becomes a square wave and the current waveform becomes a half-sine wave. Another thing to notice is that as the drain voltage becomes a perfect square wave and the drain current becomes a perfect half sine-wave, there appears to be no overlap between the two waveforms. This is the critical building block of what makes an amplifier class F. The concept of non-overlapping waveforms can be easily understood by the efficiency calculation. Generally, the efficiency of the amplifier is defined as the ratio of the fundamental power delivered to the load and the DC power supplied to the transistor. Thus, to achieve an ideal condition of 100% efficiency, DC power supplied should equal the fundamental power delivered to the load. For this condition to be true, consider power dissipated by the drain of the transistor as the following: P diss 1 = T T 0 v DS ( t) * i D ( t) dt = P DC P out, f n= 2 P out, nf, where P 1, nf Vn * In * cos( θ ) 2 out = Solving for P, DC P DC = P diss + P out, f + = n 2 P out, nf, and putting the above expression into the efficiency expression, η = P out, f P DC = P diss + P P out, f out, f + n= 2 P out, nf Thus, the maximum efficiency can be achieved if both the power dissipated and the powers of the harmonics are minimized. To minimize the power dissipated, the

15 10 overlap between the drain voltage and the drain current needs to be minimized. To minimize the powers of the harmonics, the output matching network should be designed to include all the harmonics. However, for realistic class-f amplifier, only second and third harmonics are controlled and the overlap between the voltage and the current exists. Therefore, the overall efficiency of the amplifier becomes P out, f out, f η. = P DC = P diss + P out, f P + P out,2 f + P out,3 f Since the overlap causes P diss to be greater than 0 and second and third harmonic powers are also greater than 0, the overall efficiency degrades from being 100%. Prior experiment shows that maximum efficiency is 81.7%. The maximum efficiency of Class B amplifier on the other hand is 78.5%. Thus, there is a slight improvement from operating an amplifier in Class B to Class F. The simulation results covered in later sections will reveal the differences between the two classes of operations.

16 11 SIMULATION The entire simulation is performed on an Advanced Design System (ADS) supported by Agilent. This specific simulator is chosen because it is not only widely used in microwave fields but also it provides special features such as scattering parameter measurements and harmonic balance measurements. It also directly translates the circuit schematic to the actual circuit layout on a proto board. Thus, ADS is a very powerful tool in designing for RF/microwave circuitry. Before the actual circuit design, there are several preliminaries that must be fulfilled. First step is to determine the device that will be used in the circuit. As mentioned in the earlier sections, gallium nitride transistor is chosen for this circuit because of its high efficiency capability. Once the device is known, next step is to acquire the accurate ADS model for such device. Cree, Inc. provided sample GaN transistors for this project. Fortunately, they also had a built in ADS device model for customer to design own circuits. Once the device model is obtained, the next step is to verify that the model is valid by comparing the simulated data to the given characteristics in the datasheet. DC Bias (load line) The first set of simulation is simply to determine the DC bias condition for this transistor. The datasheet specifies that the gate-source threshold voltage is

17 12 from -1.8V to -3.0V and the drain-source voltage is recommended to operate at 28V rail. Thus, the simulation is set up to vary the gate-source voltage by the given range and the drain-source voltage is varied from 0V to 40V. The simulation generated an I-V curve for the transistor displaying the load line (figure 4). The I- V curve of the transistor will be important information that will be used to determine the DC bias condition of the Figure 4. IV curve of GaN transistor amplifier. For the amplifier design simulation, I have chosen to supply gate-source voltage with -2.7V and drain-source voltage with 28V. This bias condition, as the I-V curve indicates, is near cut-off. This means that the amplifier is class B type. S-Paramter The next step is to verify that the ADS model for the transistor gives correct scattering parameter compared to ones given in the data sheet. The next simulation is set up to perform s-parameter with 50 ohm terminations on both gate and drain of the amplifier while the source is grounded. The s-parameters given in the data sheet have three different bias conditions. All three cases were simulated and verified. The DC bias conditions are determined from the I-V curve generated earlier.

18 13 Figure 5. S-parameter of GaN transistor, V DS = 28V, I DQ =100mA Even though the design of power amplifier requires large-signal models of the transistor such as load pull analysis or power contour curves, this specific transistor did not have such information available. However, small-signal models proved to be accurate to the actual device. Thus, since the simulated data and the given data were close proximity to each other, ADS transistor model is accurate to the actual transistor. Load and Source Pull Analysis Once the ADS device model for the transistor is validated, the amplifier is ready to be designed. The first step in designing the amplifier is to characterize the input and the output impedance of the transistor. This is because to obtain the best power added efficiency, the transistor needs to be very well matched at given frequency and driving input power. To obtain such characteristics of the transistor, analysis called load pull and source pull analysis must be performed. These two analyses were followed from the template within the ADS simulator. Since all the

19 14 following simulations involve large-signal parameters, special simulation called harmonic balance is used in ADS. The way that the template for load and source pull analysis work is that they use a real and an imaginary index inside a smith chart to sweep across a specified area within a smith chart and the simulator draws out the power delivered and power added efficiency contours and selects appropriate input and output impedances (figure 6). Technically only load pull analysis can be performed to obtain both the input and the output impedances of the transistor. However, to be more accurate in the design process, both load pull and source pull analyses were performed (figure 7 and 8). Figure 6. Smith Chart reflection coefficient selector for Load and Source Pull Analysis As the figure above shows, the designer can choose the region of sweep. It is recommended to make the sweep radius large to include all the possible range of the smith chart first, then once the first set of simulation is complete, narrow down the

20 15 sweep range to the point where the highest PAE occurs. This way would produce more accurate PAE contours and eventually would lead to accurate load and source impedances to be used in the design process. Figure 7. Result of Load Pull and Source Pull Analysis Overall, this simulation is convenient in that it generates the load impedance contour of both the power delivered and the power added efficiency. In addition, analysis shows the exact load impedance value with corresponding power delivered and PAE. For the load impedance, the impedance value of j Ohms will provide 72.95% PAE and dbm power delivered. As for the source impedance, the impedance value of j4.578 Ohms will provide 50.16% PAE and dbm power delivered. These impedances will be directly used in the design of the input and the output matching networks for the amplifier. Matching Network Design

21 16 The next step in the simulation is the design of the matching networks. The idea of the matching networks is to match the arbitrary impedance from the generator to known impedance at the load. Generally, the known load impedance is 50 Ohms and the arbitrary impedance is the impedance at the input and the output of the transistor. When the impedances of the transistor are matched to load, it will be much convenient to match it to a bigger system since all the components will be matched to the same impedances. There are several ways to design the matching networks. The simplest technique is to use the lumped circuit elements. Another method is to use microstrip line either single-stub or double-stub matching technique. I have chosen to use microstrip line method over the lumped circuit element matching method because of the ease of implementation of the actual circuit on the board. As mentioned earlier, there are two types of matching for microstrip line matching: single-stub and doublestub matching. For such matching technique, the conventional way is to use smith chart. However, ADS conveniently provides smith chart utility tool (figure 9) that could be used to match the arbitrary source to any load with various components that could be placed on the schematic.

22 17 Figure 8. Smith Chart Utility on ADS for matching technique Both single-stub and double-stub matching techniques were considered. However, single-stub matching were chosen over the double-stub matching because the double-stub matching seemed to have longer stub length and longer line length overall. Thus, it made the overall circuit bigger. However, with the single-stub matching, the circuit stayed relatively compact. In addition, this matching technique is reasonably stable and that it still provides ease of tuning after the circuit is built. As the figure above shows, the two open-circuited stubs were chosen. This is because the open circuit is easier to implement on the actual circuit board and the split of stub into two will shorten the length of the stub, which would eventually take up less space on the board. Considering all the details indicated above, both the input and the output

23 18 matching networks are designed. The smith chart utility shown in the figure gives the phase shift value respect to the length of the strip line in degrees. The actual value of the length and width of the strip line can be easily determined from another special feature called LineCalc (figure 10). This feature will calculate the length and the width of the strip line with respect to the given material relative dielectric, height of the dielectric material, the cutoff or the operating frequency, and the characteristic impedance of the strip line. Figure 9. Line Calc feature on ADS The Smith Chart Utility combined with LineCalc provides accurate elements of the circuit. The final element values such as stub lengths and line lengths are summarized below.

24 19 Table II. Element values for matching networks Input Matching Network Output Matching Network Phase Shift ( 0 ) Length (mils) Phase Shift ( 0 ) Length (mils) Stub mils Stub mils Line mils Line mils All the strip lines are determined based on the assumption that the board that will be used is Duroid and its relative dielectric constant is 2.33 and the height of duroid is 31 mils. Also, all the strip lines are characterized to have 50 ohm characteristic impedance. Due to this assumption, the width of all the strip lines is 91.8 mils. These element values will be entered in to the final schematic of the amplifier to finish the design of the amplifier. As will be seen soon, the values of those elements described above will be changed or optimized to meet the goals set by the simulation. Since the most important goal of the amplifier is to provide the maximum PAE, the simulation will optimize those element values to acquire the highest PAE. Detailed description of these simulation steps will be described in the following. Another thing to note is that the operating frequency has changed. Originally, the amplifier is designed at 2 GHz. But once the operating frequency is lowered, higher efficiency was achieved. In addition, with the current available equipments in the laboratory, lower frequency is desired. All the analysis and designs shown are based on an operating frequency of 1.7 GHz.

25 20 Power Amplifier All the simulations to design a power amplifier are followed on the basis of the templates given provided in ADS. There are various simulation templates such as load pull, source pull, single-tone harmonic power sweep, and even example amplifier designs by class of operation (figure 11). Since the important criteria to be carefully watched are the drain voltage and current waveforms, output voltage and current waveforms, fundamental Figure 10. ADS Amplifier Design Simulation Template power delivered to the load, efficiency, and power added efficiency, the template is modified accordingly to calculate and to display those values. The final schematic of the amplifier with both input and output matching networks and the quarterwavelength bias lines at the input and at the output is shown in the figure below (figure 12). Figure 11. Final Schematic of Power Amplifier

26 21 The figure above shows the schematic capture of the power amplifier. The strip line element values are optimized to achieve the highest power added efficiency. In order to accurately calculate PAE, the voltage nodes must be defined and the current meters must be added. Current meters are placed at gate and drain voltage sources, at input and output, and at the drain of the transistor. Then according to the equations given in the template, the accurate supply power, input power, output power, gain, efficiency, and power added efficiency are accurately calculated. Then, once the circuit is simulated, the results page is set to display the drain voltage and current waveforms, the output voltage and current waveforms, and the values of input power, output power, supply power, gain, efficiency, and PAE (figure 13). Figure 12. Result of Final Schematic of Power Amplifier

27 22 The results show that the input power is W (25 dbm), DC supply power is W, output power is W ( dbm), gain is db, PAE is %, and efficiency is %. Another thing to notice is that all the waveforms are distorted. This means that the signal contains multiple frequencies or harmonics. This is because the amplifier is biased at near cutoff so that it is operating as class B. As described earlier, when the amplifier is operating in the cutoff region, there are some harmonic frequencies that are introduced. This is confirmed with the simulation results. The drain voltage and current waveforms are especially distorted so much that the signal does not seem like a sinusoidal anymore. In addition, those two waveforms have very minimal overlap. This means that minimal amount of power is dissipated in the drain of the current. Thus, it eventually leads to high efficiency. This is exactly what is observed in the simulation result. After obtaining the highest PAE possible at the input power of 25 dbm, power sweep simulation is performed to verify that indeed the amplifier outputs a maximum PAE at the input power of 25 dbm. The simulation sweeps the input power from 5 dbm to 30 dbm and plots PAE vs. output power, gain vs. output power, and output power vs. input power (figure 14). As the plot indicates, the amplifier falls into Figure 13. Result of Power Sweep

28 23 saturation when the input power reaches beyond 21 dbm. This is shown again in the gain vs. output power curve. As the output power is increased, the gain of the amplifier starts to decrease while having a constant gain at low end. The output power vs. input power curve indicates that the rough approximation of 1 db compression is 40 dbm at the output. The most interested point is PAE curve. As the curve indicates, when the output power is at around 40 dbm, PAE of the amplifier is at maximum. Since output power of 40 dbm is reached when the input power is around 25 dbm, the highest PAE of close to 80% is indeed achieved at the input power of 25 dbm. Therefore, the overall simulation results show that the design of the power amplifier see very promising to achieve the maximum PAE. Comparison of Class B and Class F The amplifier designed earlier is considered to be class B, because the DC bias point is near the cutoff region. This is verified with distorted voltage and current waveforms at the drain of the transistor. The next set of simulation observes the operation of class F amplifier. Again, class F amplifier involves adding of couple of resonating tanks at the output of the transistor, the first simulation involves finding the correct values for the resonators. The values are calculated from the equations given[8] and the resonator tank circuit is simulated (figure 15).

29 24 Figure 14. Resonator for Class F Operation The idea of the resonator circuit is to provide the same load at the fundamental frequency, short at the second harmonic, and open at the third harmonic. As the S- parameter simulation indicates, input impedance of 50 Ohms is observed at the fundamental frequency. Likewise, at the second and third harmonics, the impedance of 4.6 Ohms and Ohms is observed. Thus, the values indicate that the resonator circuit acts as intended. Class F Amplifier Class F amplifiers are usually biased at near cutoff just like in class B amplifiers. Thus, to compare the results of different class of operation of the amplifier, the matching networks that are already designed for class B are to be remained unchanged while the resonator circuit is added to the input side before the input matching network and the output side after the output matching network for class F operation. Then, only the resonator circuit element values are optimized to achieve the highest PAE.

30 25 Figure 15. Result of Class F Power Amplifier The results of the class F amplifier show that the power delivered is dbm, gain is db, DC power is W, efficiency is %, and PAE is %. As the theory indicates, indeed class F operation has slightly greater efficiency from the observed increase in PAE compared to the results from class B operation. The increase in efficiency can be from increase in power delivered to the output. The DC power has also increased slightly, but the delivered power seems to have a greater contribution to the overall increase in PAE. In turn, the increase in the output delivered power is from the linearity of the output curve. As the output voltage and current waveforms show, the waveforms display almost a perfect sinusoidal wave with unnoticeable distortions. Thus, less power is being distributed to the harmonics. From the comparison of the results of two different classes of operation, class B and class F amplifiers have the same bias conditions but class F filters out the harmonic

31 26 frequencies that contribute to the overall power delivered, and rather traps those harmonics into the drain of the transistor to have more distorted voltage and current waveforms to further reduce the dissipated power. However, one downside of class F operation is the actual circuit implementation. Since the resonator circuit is designed with lumped circuit elements, it would be very difficult to find the exact values of those elements and to physically mount them on the test board. Thus, it would be much easy to implement if microstrip line equivalent circuit can be realized. Therefore, the operation of class F amplifier is only verified on the simulation and will not be fabricated on the actual board for a test. Layout Once the design of the amplifier is completed, the next step is to fabricate that design and test it on an actual test bench to verify the results obtained from the simulation. ADS conveniently provides a layout function that directly translates strip lines to a copper trace according to the length and the width of each trace. To correctly layout the trace, all the power supplies, terminations, and simulation blocks are removed (figure 17). Figure 16. Schematic of Layout

32 27 Once the schematic is modified, the layout feature directly translates those strip lines to the actual sizes of the traces. From the layout window, there are additional layer that could be added such as pc1 layer that designate the overall size of the amplifier and test layer for adding text to the amplifier. For this amplifier design, since there is no size requirements, additional copper traces are added to the input and the output to provide more room for tuning after the fabrication. The overall size of the amplifier is set to be 3 x 5. The final layout of the amplifier is shown in the figure below. The final layout shows added layer of text containing the information of the project, added copper pad at the ends of each stub and at the power supplies, and the split of input and output side. The overall board is split into two because when the actual board is fabricated, the transistor can easily slip in between the input and the output boards. This makes the mounting of the transistor and the board to the heat sink easier. The layout completes the simulation portion of the project. Figure 17. Layout of Power Amplifier

33 28 CONSTRUCTION The board is fabricated on RT Duroid board with height of 31 mils as is specified in the simulation. Once the fabrication is complete, the next step is to put together the components to test the amplifier. First part is to obtain all the necessary parts to assemble the final power amplifier. The most important component is heat sink. Since the amplifier outputs a significantly high power and requires even higher supply power, a heat sink with good thermal conductivity must be installed to dissipate power. For the heat sink, a 3 x 5 aluminum block is chosen. The size is matched to the final board size and the aluminum is a good conductor of heat and electricity. To securely mount the transistor and the board on to the heat sink, holes are drilled in to the heat sink. Then, thermal grease is applied to the transistor and the heat sink to be well thermally conducted, on top of being mechanically tightly fastened. As for the boards, four 100 pf DC blocking capacitors are placed at the indicated locations and two approximately 1 uh wire-wound RFC are placed at the supplies. In addition, couple of leads for ground connections and voltage supply connections is soldered, as well as SMA connectors at the input and the output of the amplifier. The final realization of the amplifier is shown below (figure 18).

34 29 Figure 18. Power Amplifier Two exact same amplifiers are constructed. This is because the amplifier is designed to have the best efficiency only when the input power to the amplifier is around 25 dbm. However, the signal generator is only capable of outputting 13 dbm. Thus, there must be a pre-amp to boost up the signal up to 25 dbm with an input of 13 dbm or less. Then, the second amplifier will be cascaded to the pre-amp and will act as the device under test (DUT).

35 30 TESTING 1.7GHz Signal Generator 3 db attenuator Preamp 6 db attenuator DUT High Power attenuator Spectrum Analyzer Figure 19. Test Set up Block Diagram Instrument Measurement Now that the amplifier is built, it is ready to be put to the test. Before the amplifier can be verified, a very carefully thought out procedure must be defined. The figure above is the basic set up of the experiment. Because the amplifier is capable of outputting such a high power (around 10 W), it is very well capable of damaging the measuring instruments. First step in testing procedure is to gather information about the test equipments. Since the amplifier operates at a frequency of 1.7 GHz, there must be a signal generator that can generate a stable sinusoidal wave at 1.7 GHz. In microwave lab, there is a signal generator that can produce 10 khz to 2.0 GHz signal with output power up to 13 dbm by Marconi Instruments (signal generator 2031). Once the signal generator is obtained, it must be tested for correct output of power. Even if it doesn t, it needs to be calibrated with other measuring equipments for accurate measurement.

36 31 To observe the signal, spectrum analyzer is chosen. This is because the spectrum analyzer will show a spike at a corresponding frequency and the spike will also have a peak value that is equal to the power of the signal. Thus, the spectrum analyzer is a very useful tool to measure the signal because multiple peaks at different frequencies mean that the signal contains multiple frequencies. The spectrum analyzer that will be used in the experiment must have a wide range at least up to 5.1 GHz (this frequency is the third harmonic) or higher. Again in the microwave lab, there is a spectrum analyzer that has a range from 9 khz to 22 GHz (HP 8593A). It is capable of input power up to 30 dbm. Thus, output power from the amplifier must be less than 30 dbm to not damage the spectrum analyzer. Two most critical measurement tools are obtained. The next important equipment is attenuator. Since the output of the amplifier has a potential to damage expensive measurement instruments, the signal must be attenuated. The attenuator must have a low reflection and a constant attenuation independent of frequency. Thus, all the attenuators that will be used in the experiment must be calibrated by measuring their s-parameters. All the s-parameter measurement is done on Anritsu MS4622B Vector Network Analyzer. As the block diagram above shows, there must be at least three attenuators. The-3 db attenuator at the input is to block all the possible reflections from the preamp to the signal generator, because the significant reflection may also damage the instrument. Thus, the 3-dB attenuator must have very low reflections at both ends.

37 32 S11 S22 S12 and S21 for 3 db attenuator Magnitude (db) S12 S Frequency (GHz) Figure 20. S-parameter of 3 db attenuator As the s-parameter of 3-dB attenuator shows, 3-dB attenuator is very suitable for the testing purpose because of its very low reflections (S11 and S22). The same requirement goes for the 6-dB attenuator placed after the preamp. It will mainly serve

38 33 as to block off all the reflections from the output of the preamp to the input of DUT and to reduce the power signal from the preamp to about 25 dbm. S11 S22 S12 and S21 for 6 db attenuator Magnitude (db) S12 S Frequency (GHz) Figure 21. S-parameter of 6 db attenuator

39 34 The last attenuator is the most important component. The high power attenuator must be able to handle high input power and have the same capabilities as the other attenuators. The one found in microwave lab is said to have the capability to handle 10 W. Since DUT can output around 10 W of power, this attenuator is very well suited for the experiment. Then, just like the other attenuators, it must have low reflection coefficients and stable attenuation. S11 S22

40 35 S12 and S21 for High Power Attenuator Magnitude (db) S12 S Frequency (GHz) Figure 22. S-parameter of High Power attenuator The s-parameter measurement of the high power attenuator shows that the attenuator has a very high reflection coefficient for S22. Also, the attenuator has a very wide ripple range of attenuation at around 30-dB. The attenuation of 30-dB clears any damage of the instrument, but if higher attenuation can be achieved, it is much more desired. Thus, to solve the reflection problem and to add more attenuation, additional 20-dB attenuation is connected at port 2 of the high power attenuator. This 20-dB attenuator must have low reflections at both ports and a stable attenuation. When both attenuators are cascaded, the overall attenuator became much more stable and appropriate for the experiment.

41 36 S11 S22 S12 and S21 for Combination of High Power Attenuator and 20 db attenuator Magnitude (db) S12 S Frequency (GHz) Figure 23. S-parameter of cascaded High Power attenuator and 20-dB attenuator The combined attenuator has a much more stable attenuation without any ripples and very low reflections at both ports. The total attenuation at 1.7 GHz is

42 db. This will be important value in converting from the signal observed at the spectrum analyzer back to the actual output power at DUT. The next very important equipment is the power supply for DC power. The amplifier requires at least 28 V with high supply current of at least 0.5 A. HP6294A DC power supply has 0-60V with 0-1A supply capability. This is well suited for the purpose. This completes all the necessary equipment collection and calibration process. Next step is the actual experiment. Test of Each Stage Before the final set up, each amplifier is tested separately to determine which amplifier to use as preamp and as DUT. Even though they are identical design, they may have slightly different behavior. Thus, each stage is tested separately with an input of 1.7 GHz signal with input power of 13 dbm. At the first instance, the amplifier seems to be able to amplify the signal, but as the drain voltage is increased, the amplifier falls into low frequency oscillation of around 8 MHz. This indicated that the amplifier is in unstable region. To fix the problem, a large capacitor (1uF) is place in parallel to 100 pf capacitor placed at the gate DC supply. This seemed to cure all the low frequency oscillation. There is one interesting observation that was made. As the gate bias voltage is changed around, the oscillation is disappeared. Since, the amplifier is desired to have a stable condition regardless of little change in the bias condition, the amplifier that has less variation to the bias voltage is chosen as DUT.

43 38 Final Set Up Now that all the necessary components are determined, the final circuit is ready to be tested. Final test is set up according to the block diagram shown in figure 20 above. Figure 24. Final Set Up of Power Amplifier The figure above shows the final set up of all the components to measure the performance of the power amplifier. There are two additional components inserted in the test set up. They are directional couplers and power meters. Directional coupler splits the signal power into two ports. The power sent in from the input gets coupled to the incident port with 20-dB attenuation from the input and to the output. The through line from input to output has no attenuation when other ports are terminated. Thus, the directional coupler enables the use of power meters to accurately measure

44 39 the power of the signal. Thus, two directional couplers are installed to monitor the input power to DUT and the output power of DUT on top of spectrum analyzer measurement. When calibrated correctly, both power readings from the spectrum analyzer and the power meter at the output should measure the same value. Final Result Power In (dbm) Power Out (dbm) Table III. Summary of Final Power Amplifier Result DC Power Vds Ids power Efficiency Out (W) (V) (ma) (W) (%) PAE (%) First row of the table shows the initial value of the amplifier without tuning of the microstrip traces. It shows that initially the amplifier is capable of outputting 7.8 W and consumes DC power of 14.7 W which results in PAE of 51%. Even though the output power is greater than 5 W, the efficiency is low compared to the simulation result. Thus, to increase the efficiency, the amplifier is tuned by adding capacitances at both the input and the output. The tuning process is a rigorous work because there is no formula to find the point when the PAE increases. The final result after tuning is displayed on the second row of the table above. The tuning increased the output power to almost 10 W and decreased the DC power consumption to 13.7 W. This ultimately results in PAE of 69.2%. This is a significant improvement from the initial results. Even though the simulation result shows greater PAE of 77.6%, the actual power amplifier is very close to the simulation. Further tuning can be done to increase

45 40 the efficiency of the power amplifier to better meet the simulated results, but to scope of this project and due to the time constraints, the final result stays as the ones shown in table III. The results shown above are for one bias point. The amplifier can have various PAE as the drain voltage is varied. To see if this is true and to find the bias point that makes the amplifier the most efficient, both efficiency and PAE are plotted vs. the drain voltage (figure 26). The figure shows that as the drain voltage is varied, the overall efficiency stays relatively constant, but PAE has a bell-shape curve. This deviation is due to the output power. As drain voltage is increased, greater output power is observed. But once the transistor power completely saturates, output power no longer increases and PAE is decreased. The plot shows that the highest PAE is achieved when drain voltage is biased at around 30 V. Figure 25. Efficiency and PAE as a function of Vds

46 41 The amplifier can also have a varying output power as a function of input power. The curve below shows the power sweep curve as well as the corresponding PAE (figure 27). As the figure shows, as the input power is swept from 23 dbm to 25.5 dbm, the output power increases fairly linearly. This means that over that range of input power, the amplifier has a constant gain. Also notice that PAE during that range is fairly stable. However, when the input power is decreased below 23 dbm and increased beyond 25.5 dbm, the amplifier falls into oscillation. Power Output and PAE vs. Power Input Pout (dbm) PAE (%) Pout (dbm) PAE (%) Pin (dbm) Figure 26. Power Sweep 50 To distinguish the operation of the amplifier from class B to class F, harmonic power levels are observed. Theoretically, for class F amplifier, according to the thirdharmonic peaking method, the third harmonic is trapped inside the drain of the amplifier and does not show up on the output of the amplifier. Thus, the output waveform should display much linear, less distorted waveform. This is confirmed

47 42 from the simulation results. Since the actual fabrication and testing is only done with the class B amplifier design, at the output of the amplifier, there should be third harmonic power. The figure below shows the result of the spectrum analyzer centered at the frequency of 5.1 GHz (figure 28). Table IV. Power Level of Harmonics Frequency (GHz) Pout (dbm) Pout (dbc) Figure 27. Power Level of Third Harmonic As the figure shows, there is power being delivered at third harmonic. Even though the power level at third harmonic compared to the power level at the fundamental frequency is significantly low, third harmonic still exists. Thus, this amplifier is operating in class B.

48 43 CONCLUSIONS AND RECOMMENDATIONS The original specifications for this power amplifier design is to design a highly efficient amplifier with PAE of greater than 60%, gain of 14 db with a maximum input power of 25 dbm, and operating frequency at 2 GHz. Other than the operating frequency goal, all the other specifications are successfully simulated and tested on an actual board. The frequency is changed only because of the capabilities of the measurement equipments to measure the performance more accurately. The simulation results shows that with the model provided by CREE, Inc. the amplifier can achieve up to PAE of 77%. This result is closely matched to the actual fabricated board, which achieves a PAE of 69%. Thus, the results that are obtained could not have been precise without accurate modeling of the device and careful construction of the entire circuit board. However, the distinction between the classes of operation is still not clear. The simulation results shows that for both class B and class F operation, the drain waveforms seem equally distorted if not more. Therefore, the only characteristic that separates between the two classes of operation is the waveform at the output. From the spectrum analyzer result, class F operation filters out the third harmonics and makes the output waveform more linear, whereas class B operation includes all the potential harmonics at the output waveform. However, as is shown in the actual board, the third harmonic power level is significantly lower than the fundamental power

49 44 level. Thus, it is still very hard to distinguish whether the class F operation still needs the tuning/trapping circuit at the output or at the input. Overall, considering the capabilities of the prior technology, this power amplifier has a significant improvement in terms of the efficiency. Even though much tuning and testing can be done to the power amplifier to reduce the reflected power, to remove the frequent instability, and to improve the gain, given the permitted time and effort, the project can be said to be successful.

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