P Channel Enhancement Mode Silicon Gate TMOS E FET SOT 223 for Surface Mount

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1 SEMICONDUCTOR TECHNICAL DATA Order this document by MMFT955E/D P Channel Enhancement Mode Silicon Gate TMOS E FET SOT 3 for Surface Mount This advanced E FET is a TMOS medium power MOSFET designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a drain to source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT 3 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds Low RDS(on).3 Ω max The SOT 3 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die Available in mm Tape and Reel Use MMFT955ET to order the 7 inch/ unit reel. Use MMFT955ET3 to order the 3 inch/ unit reel. G D S Motorola Preferred Device TMOS MEDIUM POWER FET. AMP VOLTS RDS(on) =.3 OHM 3 CASE 38E, STYLE 3 TO AA MAXIMUM RATINGS (TA = 5 C unless otherwise noted) Rating Symbol Value Unit Drain to Source Voltage VDS Gate to Source Voltage Continuous VGS ±5 Vdc Drain Current Continuous Drain Current Pulsed ID IDM..8 Adc Total Power TA = 5 C Derate above 5 C PD ().8. Watts mw/ C Operating and Storage Temperature Range TJ, Tstg 5 to 5 C Single Pulse Drain to Source Avalanche Energy Starting TJ = 5 C (VDD = 5 V, VGS = V, Peak IL=. A, L =. mh, RG = 5 Ω) EAS 8 mj DEVICE MARKING 955 THERMAL CHARACTERISTICS Thermal Resistance Junction to Ambient (surface mounted) RθJA 5 C/W Maximum Temperature for Soldering Purposes, Time in Solder Bath () Power rating when mounted on FR glass epoxy printed circuit board using recommended footprint. TMOS is a registered trademark of Motorola, Inc. E FET is a trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company TL C Sec Preferred devices are Motorola recommended choices for future use and best overall value. REV Motorola, Inc. TMOS 997 Power MOSFET Transistor Device Data

2 ELECTRICAL CHARACTERISTICS (TA = 5 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage, (VGS =, ID = 5 µa) V(BR)DSS Vdc Zero Gate Voltage Drain Current, (VDS = Vdc, VGS = Vdc) (VDS = Vdc, VGS = Vdc, TJ = 5 C) Gate Body Leakage Current, (VGS = 5 V, VDS = ) ON CHARACTERISTICS IDSS IGSS. 5 Gate Threshold Voltage, (VDS = VGS, ID = ma) VGS(th)..5 Vdc Static Drain to Source On Resistance, (VGS = V, ID =. A) RDS(on).3 Ohms Drain to Source On Voltage, (VGS = V, ID =. A) VDS(on).8 Vdc Forward Transconductance, (VDS = 5 V, ID =. A) gfs 7.5 mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS() (VDS = V, VGS =, f = MHz) Ciss µadc nadc Coss pf Crss 8 Turn On Delay Time td(on) 8 Rise Time Turn Off Delay Time Fall Time Total Gate Charge Gate Source Charge Gate Drain Charge SOURCE DRAIN DIODE CHARACTERISTICS() (VDD = 5 V, ID =. A tr 9 VGS =V V, RG= 5 ohms, RGS = 5 ohms) td(off) tf 3 (VDS = 8 V, ID =. A, VGS = Vdc) See Figures 5 and Qg 8 ns Qgs.8 nc Qgd 7.5 Forward On Voltage IS =. A, VGS = VSD. Vdc Forward Turn On Time IS =. A, VGS =, ton Limited by stray inductance dls/dt = A/µs, Reverse Recovery Time VR = 3 V trr 9 ns () Switching characteristics are independent of operating junction temperature. () Pulse Test: Pulse Width 3 µs, Duty Cycle %. Motorola TMOS Power MOSFET Transistor Device Data

3 ID, DRAIN CURRENT (AMPS) 8 5 V V V 8 V TJ = 5 C 7 V V 5 V VGS = V 8 VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) VGS(th), GATE THRESHOLD VOLTS (NORMALIZED VDS = VGS ID = ma 5 5 TJ, JUNCTION TEMPERATURE ( C) Figure. On Region Characteristics Figure. Gate Threshold Voltage Variation With Temperature ID, DRAIN CURRENT (AMPS) 8 55 C 5 C VDS = V C 5 C 55 C C 55 C 8 VGS, GATE TO SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN TO SOURCE RESISTANCE (OHMS) VGS = V C 5 C 55 C 8 ID, DRAIN CURRENT (AMPS) Figure 3. Transfer Characteristics Figure. On Resistance versus Drain Current RDS(on), DRAIN TO SOURCE RESISTANCE (OHMS) TJ = 5 C ID =. A VGS, GATE TO SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN TO SOURCE RESISTANCE (OHMS) VGS = V ID =. A TJ, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance versus Gate to Source Voltage Figure. On Resistance versus Junction Temperature Motorola TMOS Power MOSFET Transistor Device Data 3

4 FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain to source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a ambient temperature of 5 C and a maximum junction temperature of 5 C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. Motorola Application Note, AN59, Transient Thermal Resistance General Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turn on and turn off of the devices for switching times less than one microsecond. I D, DRAIN CURRENT (AMPS). s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT ms.. VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) DC VGS = V SINGLE PULSE TA = 5 C ms 5 ms Figure 7. Maximum Rated Forward Biased Safe Operating Area r(t), EFFECTIVE THERMAL RESISTANCE (NORMALIZED)... D = P(pk) RθJA(t) = r(t) RθJA RθJA = 5 C/W MAX. D CURVES APPLY FOR POWER PULSE TRAIN SHOWN. READ TIME AT t t TJ(pk) TA = P(pk) RθJA(t) SINGLE PULSE t DUTY CYCLE, D = t/t..e 5.E.E 3.E.E.E+ t, TIME (s) Figure 8. Thermal Response.E+ COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure defines the limits of safe operation for commutated source drain current versus re applied drain voltage when the source drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or half bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dis/dt is specified with a maximum value. Higher values of dis/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dis/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain to source voltage that the device must sustain during commutation; IFM is the maximum forward source drain diode current just prior to the onset of commutation. VR is specified at 8% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in Motorola s test circuit are assumed to be practical minimums. dvds/dt in excess of V/ns was attained with dis/dt of A/µs. Motorola TMOS Power MOSFET Transistor Device Data

5 5 V VGS 9% IFM dls/dt IS % trr ton IRM tfrr VDS(pk) VR.5 IRM VDS Vf VdsL Figure 9. Commutating Waveforms MAX. CSOA STRESS AREA I S, SOURCE CURRENT (AMPS) 5 3 dis/dt A/µs VGS VR + IFM + V RGS IS VDS DUT Li VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) 8 VR = 8% OF RATED VDSS VdsL = Vf + Li dls/dt Figure. Commutating Safe Operating Area (CSOA) Figure. Commutating Safe Operating Area Test Circuit BVDSS L VDS IL IL(t) VDD t RG VDD tp t, (TIME) Figure. Unclamped Inductive Switching Test Circuit Figure 3. Unclamped Inductive Switching Waveforms Motorola TMOS Power MOSFET Transistor Device Data 5

6 8 Crss VGS Ciss VDS TJ = 5 C f = MHz C, CAPACITANCE (pf) Coss 8 Ciss Coss Crss VGS VDS 5 GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Capacitance Variation with Voltage VGS, GATE TO SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nc) TJ = 5 C VDS = 8 V ID =. A Figure 5. Gate Charge versus Gate To Source Voltage +8 V VDD Vin 5 V 7 k ma N39 V k. µf SAME DEVICE TYPE AS DUT k N39 7 k FERRITE BEAD DUT Vin = 5 Vpk; PULSE WIDTH µs, DUTY CYCLE %. Figure. Gate Charge Test Circuit Motorola TMOS Power MOSFET Transistor Device Data

7 INFORMATION FOR USING THE SOT 3 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process inches mm SOT 3 The power dissipation of the SOT 3 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT 3 package, PD can be calculated as follows: PD = T J(max) TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 5 C, one can calculate the power dissipation of the device which in this case is 8 milliwatts. 5 C 5 C PD = = 8 milliwatts 5 C/W The 5 C/W for the SOT 3 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 8 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT 3 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power SOT 3 POWER DISSIPATION dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RθJA versus drain pad area is shown in Figure 7. R JA, Thermal Resistance, Junction to Ambient ( C/W) θ Board Material =.5 G /FR, oz Copper.8 Watts TA = 5 C.5 Watts*.5 Watts *Mounted on the DPAK footprint A, Area (square inches) Figure 7. Thermal Resistance versus Drain Pad Area for the SOT 3 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. Motorola TMOS Power MOSFET Transistor Device Data 7

8 Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of C. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 8 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The SOLDER STENCIL GUIDELINES SOLDERING PRECAUTIONS TYPICAL SOLDER HEATING PROFILE stainless steel with a typical thickness of.8 inches. The stencil opening size for the SOT 3 package should be the same as the pad size on the printed circuit board, i.e., a : registration. The soldering temperature and time shall not exceed C for more than seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5 C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD3 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was /3/ Tin Lead Silver with a melting point between C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 3 degrees cooler than the adjacent solder joints. C 5 C C 5 C STEP PREHEAT ZONE RAMP STEP VENT SOAK STEP 3 HEATING ZONES & 5 RAMP DESIRED CURVE FOR HIGH MASS ASSEMBLIES 5 C C STEP HEATING ZONES 3 & SOAK C C DESIRED CURVE FOR LOW MASS ASSEMBLIES STEP 5 HEATING ZONES & 7 SPIKE 7 C STEP VENT SOLDER IS LIQUID FOR TO 8 SECONDS (DEPENDING ON MASS OF ASSEMBLY) STEP 7 COOLING 5 TO 9 C PEAK AT SOLDER JOINT TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 8. Typical Solder Heating Profile 8 Motorola TMOS Power MOSFET Transistor Device Data

9 PACKAGE DIMENSIONS A F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: INCH..8 (3) L S H G 3 D B C M K J CASE 38E TO AA SOT 3 ISSUE H INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H.8... J K L M S STYLE 3: PIN. GATE. DRAIN 3. SOURCE. DRAIN Motorola TMOS Power MOSFET Transistor Device Data 9

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