N Channel Enhancement Mode Silicon Gate

Transcription

1 SEMICONDUCTOR TECHNICAL DATA Order this document by MTPN4E/D N Channel Enhancement Mode Silicon Gate This advanced high voltage TMOS E FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain to source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Avalanche Energy Capability Specified at Elevated Temperature Low Stored Gate Charge for Efficient Switching Internal Source to Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode Source to Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode G D S TMOS POWER FET AMPERES 4 VOLTS RDS(on) =.55 OHMS CASE 22A 6, Style 5 TO-22AB MAXIMUM RATINGS (TC = 25 C unless otherwise noted) Rating Symbol Value Unit Drain Source Voltage VDSS 4 Vdc Drain Gate Voltage (RGS =. MΩ) VDGR 4 Vdc Gate Source Voltage Continuous Gate Source Voltage Non repetitive VGS VGSM ±2 ±4 Vdc Vpk Drain Current Continuous Drain Current Pulsed ID IDM 4 Adc Total Power Dissipation Derate above 25 C PD 25. Watts W/ C Operating and Storage Temperature Range TJ, Tstg 65 to 5 C UNCLAMPED DRAIN TO SOURCE AVALANCHE CHARACTERISTICS (TJ < 5 C) Single Pulse Drain to Source Avalanche Energy Single Pulse Drain to Source Avalanche Energy TJ = C Repetitive Pulse Drain to Source Avalanche Energy THERMAL CHARACTERISTICS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient WDSR() WDSR(2) RθJC RθJA mj C/W Maximum Lead Temperature for Soldering Purposes, /8 from case for 5 seconds TL 275 C () VDD = 5 V, ID = A (2) Pulse Width and frequency is limited by TJ(max) and thermal response Designer s Data for Worst Case Conditions The Designer s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves representing boundaries on device characteristics are given to facilitate worst case design. E FET and Designer s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Motorola, Inc. TMOS 996 Power MOSFET Transistor Device Data

2 ELECTRICAL CHARACTERISTICS (TC = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage (VGS =, ID =.25 ma) V(BR)DSS 4 Vdc Zero Gate Voltage Drain Current (VDS = 4 V, VGS = ) (VDS = 32 V, VGS =, ) Gate Body Leakage Current Forward (VGSF = 2 Vdc, VDS = ) IGSSF nadc Gate Body Leakage Current Reverse (VGSR = 2 Vdc, VDS = ) IGSSR nadc ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID =.25 madc) () IDSS VGS(th) Static Drain to Source On Resistance (VGS = Vdc, ID = 5. A) RDS(on).4.55 Ohms Drain to Source On Voltage (VGS = Vdc) (ID = 5. A) (ID = 2.5 A, TJ = C) VDS(on) Forward Transconductance (VDS = 5 Vdc, ID = 5. A) gfs 4. mhos madc Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 V, VGS =, f =. MHz) Ciss 57 pf Coss 23 Crss 55 SWITCHING CHARACTERISTICS* Turn On Delay Time td(on) 25 ns Rise Time (VDD = 2 V, ID A, tr 37 RL = 2 Ω, RG = 9. Ω, Turn Off Delay Time VGS(on) = V) td(off) 75 Fall Time tf 3 Total Gate Charge Qg nc Gate Source Charge (VDS = 32 V, ID = A, VGS = V) Qgs Gate Drain Charge Qgd 23 SOURCE DRAIN DIODE CHARACTERISTICS Forward On Voltage VSD 2. Vdc Forward Turn On Time (IS = A, di/dt = A/µs) ton ** ns Reverse Recovery Time trr 25 INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead.25 from package to center of die) Internal Source Inductance (Measured from the source lead.25 from package to source bond pad) * Pulse Test: Pulse Width = 3 µs, Duty Cycle 2.%. ** Limited by circuit inductance. Ld nh Ls 7.5 nh 2 Motorola TMOS Power MOSFET Transistor Device Data

3 TYPICAL ELECTRICAL CHARACTERISTICS VGS = V 7 V 6 V 5 V VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) 2 V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) VDS = VGS ID =.25 ma TJ, JUNCTION TEMPERATURE ( C) Figure. On Region Characteristics Figure 2. Gate Threshold Voltage Variation With Temperature VDS = 5 V C 55 C VGS, GATE TO SOURCE VOLTAGE (VOLTS) Figure 3. Transfer Characteristics V BR(DSS), DRAIN TO SOURCE BREAKDOWN VOLTAGE (NORMALIZED) VGS = ID = 25 µa TJ, JUNCTION TEMPERATURE ( C) Figure 4. Breakdown Voltage Variation With Temperature RDS(on), DRAIN TO SOURCE RESISTANCE (OHMS).5.5 VGS = V 5 5 TJ = C 2 25 C 55 C R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) 3 2 VGS = V ID = 5 A TJ, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance versus Drain Current Figure 6. On Resistance Variation With Temperature Motorola TMOS Power MOSFET Transistor Device Data 3

4 SAFE OPERATING AREA INFORMATION. VGS = 2 V SINGLE PULSE TC = 25 C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) µs µs ms ms dc TJ 5 C VDS, DRAIN TO SOURCE VOLTAGE (VOLTS) 5 Figure 7. Maximum Rated Forward Biased Safe Operating Area FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain to source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25 C and a maximum junction temperature of 5 C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn on and turn off of the devices for switching times less than one microsecond. Figure 8. Maximum Rated Switching Safe Operating Area The power averaged over a complete switching cycle must be less than: t, TIME (ns) VDD = 2 V ID A VGS = V TJ(max) TC RθJC RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance td(off) tf tr td(on) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = SINGLE PULSE t, TIME (ms) P(pk) t t 2 DUTY CYCLE, D = t/t2 RθJC(t) = r(t) RθJC RθJC = C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t TJ(pk) TC = P(pk) RθJC(t) k Figure. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data

5 COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 2 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VR for a given commutation speed. It is applicable when waveforms similar to those of Figure are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. The time interval tfrr is the speed of the commutation cycle. Device stresses increase with commutation speed, so tfrr is specified with a minimum value. Faster commutation speeds require an appropriate derating of IFM, peak VR or both. Ultimately, tfrr is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain to source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 8% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances, Li in Motorola s test circuit are assumed to be practical minimums. 5 V 9% VGS IS % VDS IFM ton Vf IRM dls/dt tfrr VDS(pk) VR VdsL Figure. Commutating Waveforms RGS trr.25 IRM MAX. CSOA STRESS AREA DUT 2 + VR IFM IS Li + VDS di/dt 2 A/µs VGS 2 V VR = 8% OF RATED VDS VdsL = Vf + Li dls/dt Figure 3. Commutating Safe Operating Area Test Circuit VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 2. Commutating Safe Operating Area (CSOA) V(BR)DSS Vds(t) IO VDS L ID C 47 µf 25 V ID(t) VDD VDD t RGS 5 Ω Figure 4. Unclamped Inductive Switching Test Circuit tp t, (TIME) WDSR. 2 L I O 2.. V(BR)DSS V(BR)DSS VDD. Figure 5. Unclamped Inductive Switching Waveforms Motorola TMOS Power MOSFET Transistor Device Data 5

6 35 VGS = V 3 C, CAPACITANCE (pf) 25 2 Crss Ciss 5 5 VDS = V Coss VGS VDS GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 6. Capacitance Variation V GS, GATE TO SOURCE VOLTAGE (VOLTS) ID = A 2 25 V VDS = V QG, TOTAL GATE CHARGE (nc) 32 V Figure 7. Gate Charge versus Gate To Source Voltage +8 V VDD Vin 5 V 47 k ma 2N394 V k. µf SAME DEVICE TYPE AS DUT k 47 k 2N394 FERRITE BEAD DUT Vin = 5 Vpk; PULSE WIDTH µs, DUTY CYCLE % Figure 8. Gate Charge Test Circuit 6 Motorola TMOS Power MOSFET Transistor Device Data

7 PACKAGE DIMENSIONS H Q Z L V G B N D A K F T U R S J C T SEATING PLANE STYLE 5: PIN. GATE 2. DRAIN 3. SOURCE 4. DRAIN NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V.45.5 Z CASE 22A 6 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7

8 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLDC, Toshikatsu Otsuki, P.O. Box 292; Phoenix, Arizona F Seibu Butsuryu Center, Tatsumi Koto Ku, Tokyo 35, Japan MFAX: RMFAX@ .sps.mot.com TOUCHTONE (62) HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: NET.com 5 Ting Kok Road, Tai Po, N.T., Hong Kong Motorola TMOS Power MOSFET Transistor MTPN4E/D Device Data