CDR Status Report Özgür Çobanoğlu INFN & Univ. of Turin, Turin, Italy

Transcription

1 CDR Status Report Özgür Çobanoğlu INFN & Univ. of Turin, Turin, Italy

2 Content o Overview o Problem o Solution worlds o Analog Architectures o Brief Theory o Jitter Model o Digital Architectures o Questions System Hacker 2 System to be hacked

3 System Overview Start with the definition of the problem and continue with developing a solution. Done! 3

4 GBT Broadcast Network (BN) Gbt Matlab/Simulink, system level simulation Burst-mode phase locking Speed is not decided but not important in system level simulations Algorithm is the concern (see next pages) A begins to transmit data, frequency acquisition takes place for only once (aided acquisition) When Bs want to send data (burst-mode, ¼ of full speed), they can use the frequency that Rx is already locked via an internal path No need to re-lock the frequency (burst-mode, ¼ of full speed) but only the phase

5 GBT BN w/ Electrical Fan-Out 5 Gbt2006

6 Burst (or Packet) - Mode 6 Packet based switching & routing Packets with different power & time delay, fluctuate dynamically Each package has a header (preamble) to be used by the receiver for synchronization Payload is encoded (e.g. Manchester or Reed-Solomon) requiring a decoder

7 Burst (or Packet) - Mode 7 Time Division Multiple Access (TDMA) multiplexing scheme for communication in the remote terminal-central office direction (A & B). Remote terminals transmit to the central office in designated time slots, resulting in a bursty signal at the central office in which each burst may have a different symbol amplitude and phase. Amplitude and phase recovery are performed in a few bits using a preamble at the beginning of each burst. Gbt2006 =88bit/line General frame format (header, payload, correction words) Design requirement for a burst mode clock recovery system is to : determine the optimum clock phase with which to read the data determine which bit is the first data bit after the preamble (header) generate alarms that indicate that remote terminal transmitter must delay or advance its transmission by one bit

8 The Problem Burst-Mode Capable Work here! Simplified GBT Block Diagram 8 Gbt2006

9 Gogaert97 Why bother with CDR? 9

10 Worlds of Solutions PLL o o o Based Hardcore PLL Softcore PLL Etc. Oversampling Based o Frequency triggered o Phase Triggered o Etc. Other Instantaneous Methods o Delay based o VCO reset based o Etc. 10

11 Example for Continuous 11 Razavi Suitable for continuous mode but NOT for burst- mode. N=88 CDR architecture using external reference (retimer not shown) CDR must accomplish the task of phase alignment within 8 bits!!.. This was my starting point. The same circuit must be able to handle both the modes : packet & continuous I looked for analog designs able to do this job.

12 Example for Delay the Data 12 Must be 2 in 1 Provides Time Constant Adjustment for filter Wong96 Delay is limited and the loop can support only a limited set of non-ideality : error in (FCK-FDin) and burst length Suitable for burst mode but NOT for continuous mode. CDR must be able to handle continuous mode communication!!..

13 Example for Gated VCO Must be 2 in 1 Nogawa2005 Suitable for burst mode but NOT for continuous mode. CDR must be able to handle continuous mode communication!!.. 13

14 Blind Oversampling 14 Kim & Jeong 2003 I found it complex and rough in terms of jitter but the latest things I read are changing my idea But in any case the same circuit can not be used for both continuous & burst mode. So there would be a need for other -and this time probably- an analog circuit for continuous mode.

15 Blind Oversampling Cont'd Simulation results show the jitter tolerance as seen in the second picture, assuming : A priori knowledge of the transition probabilities the incoming data is a continuous 10 pattern (baud rate is equal to bit rate or the clock that produces the data stream) BER = Kim & Jeong slice the data with different phases store all these vales in a memory execute an algorithm to estimate bit boundaries select the best slice as data sample

16 Oversampling Example 16 Details of the Digital Algorithm Used Gogaert97 o Level Change Based ED o 25% Wander Tolerant o 310MHz

17 Semi Blind Oversampling Ierssel

18 Optional FSM Based Instantaneous 18 Analui2005 Every transition corrects the FSM state. Jitter accumulation is limited to 5 bits (CIB).

19 Summary PLL Delay-the-data 19 Finite State Mach. Gated VCO (Semi) Blind Oversampling CDR must employ two blocks to be able to handle both of the streams.

20 What we have today Ref. Rogers2002 Ng2003 Song2003 Coban2005 Lee2003 Savoj2003 Jitter [ps] Ref. Li2006 Nogawa2005 Yoshikawa2000 Banu1993 Analui2005 Dunlop1995 Eldering1994 Nakamura1996 Kimura2004 Yamaoka1997 Tech. [µm] Speed [Gb/s] Speed [Gb/s] Power [mw] Tech. [µm] SiGe Some recent pub. suitable for continuous mode CDR operation Some pub. suitable for burst-mode CDR operation 3.52Gb/s needed for continuous-mode 880Mb/s needed for burst-mode!!

21 Architectures I could think of 21

22 Architecture v0 22 If the clock error and burst length are limited then a variable delay can be used to lock the data to a local clock. FLL is always locked, burstmode receiver knows the freq. but not the phase Delaying the data is the fastest solution, Phase alignment is instantaneous (we have 8 bits as preamble, though) Dout FREQ %88 Either CK or Vctrl must connect the two blocks. The above one fails in continuous mode if FREQ & Din has different frequencies (wander). Wong96 Connection between the two loops is FREQ. Perfect for burst-mode but can we use it for continuous stream? NO!!

23 Architecture v1 23 Instead, an analog value is the connection. Connection between the two loops is VCONT. Nogawa05 At every data transition, jitter is reset We have 5 CIBs, jitter accumulation is limited to 5 bits in the worst case Gbt2006, Papotti02006 VCOs can be identical enough with proper layout Suitable for both types of communication (burst & continuous) Implemented in a similar tech., with 30ps delay in Gating 10Gb/s Either have 2 VCOs and Din passes through one block or have 1 VCO and Din goes to both (see next)

24 Architecture v1 Cont'd Measurement of a similar architecture 660 Mb/s Banu93 24

25 Architecture v1 Cont'd 25 Measurement of a similar architecture 10 Gb/s Nogawa05

26 Coarse Control Architecture v2 26 Fine Control Reset d/dt changes the time constant of the LPF, it is the memory for the delay line Red line is the reference frequency/phase which : locks to Din, slowly in continuous mode Din locks to it, instantaneously in burst mode Not even a single bit is lost independent of the mode : Right block can accept hundreds of Kbytes (Wong96) of data and this gives PLL enough time to take over.

27 The Architecture v3 Circuit which combines both functionality : 27 When Din is burst-mode, it accepts the data, phase alignment is instant, each data transition resets phase error (accumulation of 5 bits) Can be designed such that it can accept Kbytes of data, providing Fine Loop enough time to take over (we have 11Bytes, though) Continues operating even after Fine Loop locks When Din is continuous-mode, same thing happens Exactly the same circuit operates in two different modes Not even a single bit is lost!

28 28 Some of the Components PD FILTER VCO

29 Phase Detectors - PDs 29 They output a value depending on the phase difference between their inputs. Full vs Half vs Quadrature etc. rate PDs Linear vs Binary (Bang Bang or BB) vs Ternary (BB w/ hold state) PDs Alexander75 Full Rate Alexander Hogge85 Full Rate Hogge

30 PDs (Cont'd) 30 Difference between Vout1 and Vout2 gives a pattern independent output. Linear half rate PD Quarter rate PD Definition of a linear PD Lee2003

31 Half Rate PD Operates at both edges of the compared signals 31

32 Binary P/F Detector 32 Razavi Frequency Detector Fischette2004 Razavi

33 Binary P/F Detector 33 Operation Fischette2004 Note that frequencies of Ref and FbClk are different.

34 Binary P/F Detector Model Based Implementation Go Faster Go Slower Input (top) T=1.1 Input (bottom) T=1.0 It works, if both of the edges are seen by PFD. A delay after AND gate is needed to guarantee a smallest pulse width (see top plot) 34

35 Dead Zone of PFD Fischette

36 Dead Zone of PFD Go Faster Go Slower Input (top) T=1.1 Input (bottom) T=1.0 Go Faster has a non-delta value 36

37 A Possible Usage w/ Filter Gardner80 CP-PLL Add resistor to make it stable Add C2 to reduce ripple on control line 3rd order filter but loop is still Type II (there are two poles at the origin) We will come to this later. 37

38 Voltage Cont. Oscillator Walker Ring & Multivibrator types seem more suitable. 38

39 Low Swing Ring VCO 39 Barkhaussen Criteria \/ trip-point Oscillation freq. for small/large voltage models Razavi

40 Controlling Ring VCO 40 Self biasing to cancel out process dependencies Maneatis96 Time constant defines the large signal oscillation frequency Change on resistance of M3 & M4 (load) to alter the unit delay To preserve the swing at the output, alter tail current together with Vcont

41 Controlling Ring VCO Cont'd 41 Nogawa2005 OUT is independent of the delay. M3 & M4 are the negative resistances. Since the current through the load resistors R1-R2 is constant (Ib+Itune), the output voltage amplitude is independent of delay. Vdg is constant and the difference between logic 0 and logic 1. Changing the current Id changes the amount of negative resistance at the node.

42 Source Coupled VCO 42 Vdd High impedance, W/L is low gnd Vout_b Vout High Beta, W/L is high According to the amount of current Id Id C~fF for GHz f OSC= ID 1 = 2 t 4CV THN gnd

43 Model for Analog CDR 43

44 Equations H s = VCO s IN s = K VCO K PD F s s K VCO K PD F s 2 s H s = F s = scr 2 1 s T 2 1 = sc R 1 R 2 1 s T 1 1 i (s) s = s2 s2 2 w n s w n2 e s s s 1/ T 1 = 2 i (s) s s 2 w n s w n2 K VCO K PD 2 s 2 wn s wn 2 K VCO K PD T1 A must : K VCO K PD T K VCO K PD 1 T 2 2 K PD K VCO T1 Gardner High-Pass Charact. w n 2 w n= = e s 2 w n w n Circuit can not track fast variations This is the reason PLL is not good for burst mode. 44

45 Jitter Model for Analog CDR 45

46 Small Phase Error Effect of Metastability Din causes X and Y to develop a potential difference within sampling time and regenerative pair keeps these values Lee04 When CK=1, X and Y goes away from each other When CK=0, regenerative pair steers current according to the potential of X and Y If CK is set to 0 before complete switching of X and Y, regenerative pair confuses 46

47 High Level Jitter Model 47 Based on the model in the figure, jitter characteristics will be examined. Lee04 IN (Gain peaking<0.1db, w=fb/1250, ITU Standard)

48 VCO Phase Noise Jitter Generation (a) VCO phase noise addition, (b) effect of slewing because of VCO jitter VCO jitter transfer function and the corners Lee04 48

49 Optimizing Model Parameters Jitter tolerance & transfer model parameters could conflict with CDR loop parameters Both models can be further updated and become complicated Parameters in these models can be optimized with Evolutionary Algorithms (EA) : A good example to Multi Objective Optimization Problem (Co94) Even though, transistor level circuits can be designed and optimized by EAs, we will not have time for this but we could have time for the previous bullet Portable 49

50 Questions? 50 Is frequency acquisition (aided locking) needed? Can we stop the communication on red wire w/o stopping that of the blue one? What is the technical reason we use ¼ of the full speed for burst mode? (for oversampling we could need it but for other approaches we definitely not e.g. arch. v1 & v2) What is the precision of the reference clock? How much jitter and/or BER is acceptable? Do we have a detailed specification list?

51 References Gbt2006 : GBT13 Tentative Specification, (Gigabit Bidirectional Trigger and Data Link), F. Faccio, A. Marchioro, P. Moreira and G. Papotti, Version 0.15, CERN, 24 January 2006 Gogaert97 : A skew tolerant CMOS level-based ATM data-recovery system without PLL topology Gogaert, S.; Steyaert, M.; Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE May 1997 Page(s): Razavi : Design of ICs for optical communications, McGraw-Hill, ISBN Wong96 : A 10 Gb/s ATM data synchronizer Wong, T.Y.K.; Sitch, J.E.; Solid-State Circuits, IEEE Journal of Volume 31, Issue 10, Oct Page(s): Kim & Jeong 2003 : Multi-gigabit-rate clock and data recovery based on blind oversampling Jaeha Kim; Deog-Kyoon Jeong; Communications Magazine, IEEE Volume 41, Issue 12, Dec Page(s):68 74 Iersell2006 : A 3.2Gb/s Semi-Blind-Oversampling CDR, ISSCC 2006, Clock & Data Recovery, 18.5 Analui2005 : Instantaneous Clockless Data Recovery and Demultiplexing Analui, B.; Hajimiri, A.; Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on] Volume 52, Issue 8, Aug Page(s): Nogawa 2005 : A 10Gb/s Burst-Mode CDR IC in 0.13µm CMOS ISSCC 2005, Optical Communications, 12.5 Banu93 : A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission Banu, M.; Dunlop, A.; Solid-State Circuits Conference, Digest of Technical Papers. 40th ISSCC., 1993 IEEE International Feb Page(s): ,

52 References (Cont'd) Hogge85 : A self correcting clock recovery circuit Hogge, C.R., Jr.; Electron Devices, IEEE Transactions on Volume 32, Issue 12, Dec 1985 Page(s): Alexander75 : Clock recovery from random binary data, Electronic Letters vol. 11, pp , Oct Lee2003 : A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology Jri Lee; Razavi, B.; Solid-State Circuits, IEEE Journal of Volume 38, Issue 12, Dec 2003 Page(s): Gardner80 : Charge-Pump Phase-Lock Loops Gardner, F.; Communications, IEEE Transactions on [legacy, pre ] Volume 28, Issue 11, Nov 1980 Page(s): Maneatis96 : Low-jitter process-independent DLL and PLL based on self-biased techniques Maneatis, J.G.; Solid-State Circuits, IEEE Journal of Volume 31, Issue 11, Nov Page(s): Gardner : Phase lock techniques F. M. Gardner, John Wiley & Sons Lee2004 : Analysis and modeling of bang-bang clock and data recovery circuits Jri Lee; Kundert, K.S.; Razavi, B.; Solid-State Circuits, IEEE Journal of Volume 39, Issue 9, Sept Page(s): Co1994 : Optimization of phase-locked loop performance in data recovery systems Co, R.S.; Mulligan, J.H., Jr.; Solid-State Circuits, IEEE Journal of Volume 29, Issue 9, Sept Page(s):

53 References (Cont'd) Fischette2004 : 2004 ISSCC Tutorial, Dennis Fischette Pappotti2006 : An Error-Correcting Line Encoding ASIC for a HEP Rad-Hard Multi-GigaBit Optical Link PRIME2006 Conference Record Walker : Tutorial, CDR for Serial Digital Communication, Rogers2002 : A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS Rogers, J.E.; Long, J.R.; Solid-State Circuits, IEEE Journal of Volume 37, Issue 12, Dec Page(s): Ng2003 : A second-order semidigital clock recovery circuit based on injection locking Hiok-Tiaq Ng; Farjad-Rad, R.; Lee, M.-J.E.; Dally, W.J.; Greer, T.; Poulton, J.; Edmondson, J.H.; Rathi, R.; Senthinathan, R. Page(s): Coban2005 : A Gb/s quad transceiver with second-order analog DLL-based CDRs Coban, A.L.; Koroglu, M.H.; Ahmed, K.A. Page(s): Savoj2003 : A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector Savoj, J.; Razavi, B. Page(s): Cobanoglu :

54 Thanks a lot for your support. 54