A 900W, 300V to 50V Dc-dc Power Converter with a 30MHz Switching Frequency

Transcription

1 A 900W, 00V to 50V Dc-dc Power Converter with a 0MHz Switching Frequency John S. Glaser (glaser@research.ge.com) Jeffrey Nasadoski Electronic Power Conversion Lab General Electric Global Research Richard Heinrich Naval Electronics & Surveillance Systems Lockheed Martin Corporation Abstract Designers of power conversion circuits are under relentless pressure to increase power density while maintaining high efficiency. A primary path to higher power density is the use of increased switching frequency. In this paper it is argued that the use of switching frequencies in the VHF band (0MHz-00MHz) are a viable path to the achievement of substantive gains in power density. Evidence for this viewpoint is presented in the form of an unregulated 900W prototype dc-dc converter with a 0MHz switching frequency, an input voltage range of 270VDC to 0VDC, and an output voltage of 50VDC. This converter uses a quad module architecture with series input and parallel output to provide acceptable efficiency with the specified input voltage range. This converter operates with peak output power of 1kW at 0VDC input, and has an efficiency of >78% under nominal conditions, with maximum efficiency near 80%. I. INTRODUCTION Designers of DC-DC power converters are under relentless pressure to increase power density, efficiency, and reliability, reduce cost, and improve transient response, preferably achieving all these goals simultaneously. In reality, all these parameters must be balanced in a manner that best meets the needs of the application, and certain goals will have priority based on that application. For example, aerospace applications often have restrictions on overall system mass, which results in high power density as a primary goal. This paper promotes the use of switching frequencies in the VHF (very high frequency, 0MHz-00MHz) band as a promising approach to provide substantial gains in power density. A key contributor to power converter volume is the required energy storage, normally implemented with capacitors and inductors [1]. For a given energy storage technology, the size of the storage elements is usually a monotonically increasing function of the energy stored. Increased power density requires reduced stored energy and/or increased storage density. The latter is subject to fundamental material limitations such as breakdown voltage and permittivity for capacitors, and saturation flux density and permeability for inductors [2]. Improvement in the properties of magnetic and dielectric materials is a slow process. The alternative to increased energy density is the reduction of the stored energy per cycle. This is accomplished by increasing the switching frequency F SW. This works up to a point, but as F SW continues to increase, increased switching losses, proximity losses and core losses in magnetic components, and problems with parasitic reactances diminish these gains. While these issues can be mitigated to some extent, at a high enough frequency they dominate the converter design. Further increases in F SW eventually lead to reduced power density [1,, 4]. It has been proposed that a large jump in switching frequency to the VHF band and a move to a new set of topologies and architectures can provide a way to move beyond the limitations of present technology. The paper gives a short overview of approaches to VHF dc-dc power conversion. It shows an approach to /09/$ IEEE 1121

2 2 increase the practical bus voltage for such converters by a factor of two or more. Experimental evidence for this approach is presented in the form of an unregulated 900W prototype dc-dc converter with a 0MHz switching frequency, an input voltage range of 270VDC to 0VDC, and an output voltage of 50VDC. This converter uses a quad-module architecture with series input and parallel output to provide acceptable efficiency with the specified input voltage range. This converter has an efficiency of >78% under nominal conditions, with maximum efficiency near 80%. II. MOTIVATION FOR VHF SWITCHING FREQUENCIES The point was raised that increased power density via increased switching frequency has practical limitations. Thus, how does a >10X jump in F SW provide a path around these limitations? Figure 1 shows an estimated plot of power density versus F SW. Some caveats regarding this plot are in order: 1) This plot is meant to illustrate general trends, so please consider the numbers to be factor-of-two estimates, 2) the numbers are representative of kilowattscale converters with bus voltages of 00V, and ) power density numbers are fuzzy by nature. For conventional PWM switching converter technology, increased F SW leads to increased power density at lower frequencies, but the slope flattens out in the range of several hundred kilohertz. The main causes are magnetic component losses and semiconductor switching losses. Magnetic cores show increased losses and must be operated at lower flux densities, increasing component sizes. Winding eddy current losses, especially proximity losses, become large and difficult to mitigate. Switching losses become large, and circuit parasitic components contribute greatly to switching device stress. At a few MHz, one needs fully soft-switched converters, with a large penalty in device stress and conduction loss, along with single-layer magnetics with minimal proximity losses, and these requirements result in a significant size penalty. The result is that power density is actually reduced. Beyond a few MHz, one has already incurred the conduction loss penalty of full soft-switching, so to first order, switch losses no longer increase with F SW. We can then bound the problem by assuming the use of ~500W/in ~50W/in Power Density Conventional ~250kHz-500kHz Advanced Magnetic Core ~5MHz Air Core ~500MHz Frequency Figure 1. Estimate of dc-dc converter power density entitlement versus F SW for conventional and fully soft-switched converter technologies. single layer air core inductors. It was proposed that for a constant heat flux, a constant Q, and a solenoidal air core winding, the inductor volume varies inversely with F SW [5]. Using some estimated inductor sizes based on [6], and inverter topologies like [7, 8], which are in turn based on Class E/DE [9, 10, 11], we can very roughly estimate the power density of converters based on such magnetics, allowing one to position a line representing the limitation presented by air core inductors. Recent developments in magnetic materials may allow a reduction in inductor volume [12]. For this reason and based on available semiconductors, F SW near 0MHz is a promising area to investigate. Different voltages and powers will affect the breakpoints in the chart, but the general concept remains valid. III. APPROACHES TO VHF POWER CONVERSION Dc-dc converters can in general be modeled as an inverter which generates an AC power signal, followed by a rectifier and filter to convert the AC power signal back to DC. In the VHF range, inverters and rectifiers employ soft switching for both turn-on and turn-off, so that switching losses are kept at acceptable levels. The most common inverter topologies used in the HF or VHF band are either based on class D, E, or DE topologies [9,, 1, 7, 10, 11, 14]. Class E and DE topologies are distinguished by the use of resonant waveforms and switch transition timing such that all switching transitions are soft, and that any anti-parallel diodes of switches do not conduct. The latter means that bidirectional switches are not required, and implies the absence of reverse recovery losses. In Class DE, peak voltage stresses on the switches are advantageously limited to the bus voltage, but driving a high-side switch with the precise timing /09/$ IEEE 1122

3 required becomes difficult as F SW and the bus voltage increases. Class E avoids the high-side drive issue via the use of a single-ended ground-referenced switch, but the tradeoff is high device voltage stress. Furthermore, class E inverters are characterized by a fixed relationship between F SW, switch capacitance C SW, dc bus voltage V DC, and power P : P K 1 F SW C SW VDC 2 (1)!( #& '2,&!2 +%& /895:& /012!" <+ '( #$%& +% $%) < /456789:;7 '" +.-.) Figure 2. Class Φ ideal inverter for 150V in, 250W. /:&;>?16 *+ +,-. where K 1 is a constant determined by the converter passive component values. It can further be shown that the class E inverter loss due to the switch resistance R SW can be approximated by P loss K 2 P 2 V 2 DC R SW (2) where K 2 is another constant determined by the converter passive component values. Finally, the normalized loss is P loss P K 1K 2 F SW R SW C SW () The R SW C SW product is a figure of merit for a given switch technology. Thus, the maximum class E converter efficiency is rigidly tied to the converter specifications and the switch technology. An illustrative example can be given by considering a 1kW high-q class E inverter with a 00VDC nominal input, and a 90% drain efficiency with all losses in the switch. The resulting switch requirements translate to a 1200V switch with C SW < 19pF and R SW < 4.2Ω. A typical 1200V RF MOSFET is the IXYS IXZR08N120, with R DS,on 2.1Ω at room temperature, or an estimated 4.2Ω at operating temperature [15]. At 00V, C oss 80pF. The drain to case capacitance alone is pf; 19pF is far out of reach. Clearly, the standard class E topology is not suitable for this application. The topology used in this paper is the class Φ converter (Fig. 2), also referred to as a class EF 2 inverter [7, 8, 16]. This inverter has the advantage of low voltage stress compared to class E, as well as the ability to absorb some of the transistor output capacitance into the resonant network (Fig. ). A complete description of a dc-dc converter based on the class Φ inverter followed by a resonant rectifier is given in [7], along with an approximate but effective design procedure. The prop- Figure. Class Φ and E drain voltage waveform comparison for a 150V input, 250W inverter. erties of this converter are voltage stress on the active switch of approximately times the dc bus voltage, soft switching on all switch transitions, the ability to absorb substantial switch capacitance, and fast transient response due to low energy storage. The details of the converter operation are covered in the references and will not be repeated here. IV. METHOD TO INCREASE BUS VOLTAGE CAPABILITY Aerospace and naval applications often have nominal bus voltages of 270VDC or 00VDC, respectively. This requirement conflicts with the high voltage stress typical of VHF-capable inverters. While the Class Φ design reduces this stress substantially compared to class E, the peak transistor voltage is still 2 to 2.5 times higher than the bus voltage. Typical RF MOSFETs suitable for such converters tend to have breakdown voltages at 500V, 1000V, or 1200V. In this paper s application, the nominal bus voltage range is 00VDC±10%. With the class Φ topology, this means a peak transistor voltage up to 825V can be expected under normal operating conditions; the transistor used will need a breakdown voltage ~1kV. As discussed in [perrualt, kee] the R SW C SW product is a useful figure of merit for class E and derivative inverters. It is useful to examine the effects of breakdown voltage V BR on said product. If we assume the following: 1)silicon vertical MOSFET technology, 2) all resistance /09/$ IEEE 112

4 4 due to drift layer, ) all capacitance due to body diode, 4) uniformly lightly doped drift layer with step junction, 5) all structures are planar, and 6) the drift layer becomes fully depleted at the moment the breakdown voltage is reached, then R SW,sp W D qµ n N d (4) F S AC signal input S 1 V G + _ R SW Z in C SW N 1 P in 1 2 Z fd N P out Z L C SW,sp ɛ Si W D (5) Z1 Active switch Cell Z 2 V BR N 4 d (6) Figure 4. Generic single RF converter. where R SW,sp and C SW,sp area the specific (per area) values, and Eqs. 4, 5, and 6 are from [17]. Then R SW C SW R SW,sp C SW,sp ɛ Si qµ n N d (7) Note that die area has dropped out of the relationship. Equations 7 and 6 can be combined to yield 4 BR R SW C SW ɛ Si V qµ n (8) The penalty in normalized conduction loss is seen to increase as V 4 BR, i.e. a severe penalty is paid for substantially increasing the input voltage requirement. This has stymied the development of VHF converter topologies in medium voltage applications. A solution to this problem is the use of multiple dc-dc converter modules interconnected with series connection of inputs and parallel connection of outputs. The class Φ topology shares power naturally and thus will work well in such a system [18]. The implications of such a scheme can be seen with a simple analysis. Figure 4 shows a simple model of an ideal, lossless RF converter. The following is assumed: 1) Networks N 1 and N 2 are lossless and linear time-invariant, 2) all capacitive reactance in parallel with the switch is due to the switch and represented by C SW, ) all undesired losses are due to the series resistance R SW of the switch S 1, and 4) the losses of R SW are small enough not to disturb the operation of the converter. Then, for a given switching frequency and topology, the input can be appproximated by a real input impedance Z in, and all power not lost in R SW goes to the load. Then P in P V 2 G Z in (9) Now suppose we have a system of N ideal converter modules of the same topology as the converter of Fig. 4, where the inputs are connected in series and the outputs in parallel, as in Fig. 5. The N-module converter still processes the same power P in as the single converter of Fig. 4. Denoting the relevant variables for the individual modules of the N-module system via a, we can write P in P in N V G 2 V G 2 NZ in V 2 G Z in (10) V 2 G N 2 (11) Substitution of Eq. 11 into 10 allows one to show Z in Z in N (12) Given the assumptions listed previously, one may achieve the results of Eq. 12 by scaling all component impedances in networks N 1 and N 2 by N 1. Since the switch capacitance C SW is an intrinsic limitation of the converter, scaling impedances by N 1 means that we can increase C SW or F SW by a factor N if the other is held constant. The advantages of increased F SW have been discussed. Fixing F SW and increasing C SW is also advantageous, since for a given switch technology, this allows a larger die and corresponding reduction in R SW, which in turn leads to lower losses. For silicon MOSFETs, one can estimate the effect on efficiency of using multiple series input cells. For fixed F SW and keeping the same topology, the effect of multiple series input modules can be modeled by a single effective switch resistance R SW,eff single converter NR SW. From Eq. 8, we can write for a R SW 1 C SW 4 BR ɛ Si V qµ n (1) Replacing the single converter with an equivalent N-cell /09/$ IEEE 1124

5 5! "! " ()**+,! #!$ '$ %&! '$ " 012 " ' #%& #$ %& #$ /!!$ "!!$ " " #$ %& ()**+- # '$ %&!" '$ 012 ' #%& #$ %& #$ / ()**+. # '$ %&!" '$ ' 012 #%& #$ / Figure 5. Multi-cell converter with series input and parallel output connections. system with series inputs, with F SW, total power P in, and topology unchanged, we can write R SW,eff NR SW (14) N C SW N NC SW 1 C SW R SW N 4 ɛ Si 4 # / #. (V BR ) qµ n (15) ɛ Si ( VBR N ) 4 qµ n (16) 4 BR ɛ Si V 1 qµ n N 4 (17) (18) This shows that to first order, with silicon MOSFETs, the lower breakdown voltage enabled by series input multicell converters allows a net reduction in switch losses. As will be seen later, switch losses comprise the majority of losses in the design space targeted. V. CONVERTER DESIGN The converter module design is similar to the design presented in [7, 16]. The individual modules were designed for a voltage range of 15VDC-165VDC input, 50VDC output, 250W at 150VDC input. and F SW 0MHz. This allows the four-module system to meet the 270VDC-0VDC input voltage range. Figure 6 shows the module schematic. The design of the power stage was finalized using simulation tools. Transistor and diode models that captured non-linear capacitance and static I-V curves proved to be sufficient for optimzing the design, and minimal adjustment of the power components was required. The class Φ inverter stage is based on the IXYS IXZ210N50L 500V RF MOSFET, chosen due to its availability and low-inductance package design. The procedure in [7] was used, although the converter differs in that no autotransformer was used. The design was adjusted using a SPICE simulation, and the first iteration of the hardware was quite close to the planned design. The rectifier uses two parallel Cree CSD V SiC Schottky diodes with an inductor sized such that the impedance of the rectifier at F SW is real. Galvanic isolation was achieved through the use of a capacitor in the ground return of the inductor (4 0.22µF 500V X7R ceramic chip capacitors), necessary for the series stacked 4-module system. The gate drive was formed by using a parallel inductor to resonate with the MOSFET input capacitance at F SW. Additional resistance was added in parallel to bring the gate circuit input impedance to 50Ω. The input was driven with a sine wave from a lab RF amplifier, resulting in a sinusoidal voltage at the gate. A dc bias network was used to adjust the duty cycle. Finally, a coaxial low-leakage isolation transformer was used to provide necessary isolation for the series stacked 4- module system. Other construction details include the use of air core solenoidal inductors and porcelain or mica RF capacitors. The converter was constructed on a two-layer, standard FR4 printed circuit board. The four-module system was wired as shown in Fig. 7. Gate drive power from the amplifier passes through a transmission-line transformer based splitter to drive the four modules. The prototype system in this paper is an open-loop, unregulated system. A promising control method is the use of burst-mode control, i.e. cycle-skipping, which allows high efficiency even at light loads, albeit at the expense of bandwidth [1]. VI. SIMULATED AND EXPERIMENTAL RESULTS First, a single module was constructed according to the specifications given in Section IV. This module was tested and compared to a detailed simulation model that /09/$ IEEE 1125

6 6 Vin Vbus LF1 R9 Vbias -4 LS1 1k Vdrain L1 10n Rser250m Rser n 150 R 50 M1 LF2 IXZ210N50L 75n Rser700m Vgate 0.2 VC2 2n Rser10m R6 Vgate_in Cs2 500n L4 55n Rser200m Vgatedrive SINE(0 20 0e6) AC 0 0 R5 C 215 1n R4 Cstray C2 0p Rser0.1 Lser5n 18.8p Rser10m D2 CSD1000_GE Cs1 D1 1.8n CSD1000_GE Lrect Vout Cout Cout1 4.7! 20! R1 10 7n Rser100m 5.6k C1 0.88! Figure 6. Converter cell schematic Figure 7. tion. Figure 9. Four module converter system with series-parallel connec- Photograph of four-module converter system. Table I F OUR - MODULE CONVERTER SYSTEM DC MEASUREMENT DATA.!"#$ $*+,* $$,+ $00 $*,* $01 included circuit board and other parasitic components. Fig. 8 compares the measured and simulated waveforms for the transistor drain and rectifier anode voltages.!"#% $*%,$/1,$0/, $/1,/ $0%,%!"# %+.,% *..,0 **., *.$,+ **.,%!&'($ /-,-0 /-,-0 /-,-0 -,- -,-0 )45(678 )45(67; 9: < $/,.*.,/$ $*,-%.,%/ $*,1%.,$0 $*,1%.,$0 $*,-%.,$0 )"# 1-/ $$$% $*%% 1-. $% )&'(>?5@? +%/ 11% $.$. +./ $..$ A;5"#B688 C&(5@B688 1.,-2 +-,+2 +-,*2 +1,*2 +0,/2 +,02 +-,$2 ++,-2 +-,12 +1,-2 The measured waveforms include the near-sinusoidal gate voltage as well. Note the good agreement of the and RF gate drive power for 50V and 60V outputs. measured and simulated waveforms. Efficiencies measured are dc-dc efficiencies with careful Four additional converters cells were constructed with attention paid to the measurement setup, including addi- inputs and outputs connected as shown in 7. Figure 9 tional filtering on the meters to minimized errors due to shows a photograph of the dc-dc converter. The indi- EMI. Drain efficiency values do not include gate power; vidual modules were tested before combining into the total efficiency values include forward power measured four-module system. The only tuning performed was at the output of the RF amplifier supplying gate power, adjustment of LF2 to insure that the 2 harmonic as measured with an RF power meter. The maximum short was at 60MHz and adjustment of the gate parallel deviation from ideal input voltage sharing was.0% inductor for minimum reflected gate power. Waveforms over the input test range, indicative of excellent power and measurements of all converters were nearly identical. sharing between the 4 modules. No special adjustment Plots of efficiency and output power versus input of the converter cells was employed to obtain this result, voltage for the four-module system are shown in Fig. in keeping with the fact that such natural sharing is an 10 for an output voltage of 50V. Table I shows complete inherent property of the converter topology selected. nd DC measurement data including input voltage sharing /09/$ IEEE 1126 The results demonstrate the accuracy of the simu-

7 7 50V V(vdrain) V(n001) 00V 250V 200V 150V 100V 50V 0V -50V -100V -150V -200V 75ns 85ns 95ns 105ns 115ns 125ns 15ns 145ns 155ns 165ns 175ns (a) Experimental waveforms (b) Simulated Waveforms: top trace Vds, lower trace Vrect Figure 8. Comparison of measured and simulated waveforms. Both figures are 50V/div vertical and 10ns/div horizontal.,'5+&8:9 ))##+### )###+### '##+### &##+### %##+### $##+###!"#$%%&#'()$*+$*&,$*-'*./(0$ 124#&'5+65+ &), &#, %', %&, %%, %$, "##+### %",!"#!$#!%#!&#!'# (## ()# (!# ((# (*# ("# 7(&89 -./ :;; <.049:;; $#!# %#!#!"#$%&'%&()"**(+&%,-."/#(0(1245,'%. &# $#!"# '()*+, -./012 *4 *5 ) :;:<71 Figure 10. system. Efficiency and power versus input voltage for 4-converter Figure 11. Simulation-based module loss breakdown lations, the operation of the series-input-parallel-output architecture, and the achievement of usable efficiencies for converter operating in the VHF range. In particular, it is shown that input voltages up to 0VDC and powers up to 1kW can be achieved using 500V MOSFETs, with substantial design margins. VII. EFFICIENCY The efficiency values for the four-module system are state of the are for VHF dc-dc converters at the 1kW power level, but they are not yet comparable to commercially available converters. Figure 11 shows an estimated loss breakdown based on the detailed simulation model. It can be seen that the MOSFET accounts for the majority of the loss. The authors feel that the most promising technology to mitigate this loss is the development of wide-bandgap semiconductors [19], with a much lower R SW C SW than silicon MOSFETs of comparable voltage rating. VIII. CONCLUSION This paper has first presented an argument for the use of switching frequencies in the VHF band (0MHz- 00MHz) as a promising path to increase state of the art power densities by an order of magnitude for power levels in the hundreds of watts to kilowatts. Experimental evidence is provided by a prototype DC-DC converter with a nominal output power of 900W and a switching frequency of 0MHz. Operation of the converter over an input voltage range of 270V to 0V has been demonstrated, with a peak output power of 1kW. Efficiency is in the range of 75% to nearly 80% at an output voltage of 50V. The problem of high transistor voltage stress is addressed through the use of the class Φ (EF 2 ) topology in conjunction with a multi-module series-input/parallel /09/$ IEEE 1127

8 8 output scheme, allowing the use of commercial silicon RF power MOSFETs. While the efficiency and power density of this prototype is not directly competitive with present state of the art, it is shown that acceptable performance can be obtained. It is the authors opinion that this is enough evidence on which to pursue this path towards large increases in power density. REFERENCES [1] R. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Springer, January [2] J. D. Kraus, Electromagnetics, ser. McGraw-Hill Series in Electrical Engineering. McGraw-Hill, Inc., [] C. Xaio, An Investigation of Fundamental Frequency Limitations for HF/VHF Power Conversion, Ph.D. dissertation, Virginia Polytechnic Institute, July [4] J. Kassakian and M. Schlecht, High-frequency high-density converters for distributed power supply systems, Proceedings of the IEEE, vol. 76, no. 4, pp , April [5] D. Perreault, Architectures, topologies, and design methods for miniaturized vhf power converters, September 2008, presented at the 1st Annual PowerSoC Workshop, Cork, Ireland. [6] C. R. Sullivan, W. Li, S. Prabhakaran, and S. Lu, Design and fabrication of low-loss toroidal aircore inductors, Power Electronics Specialists Conference, PESC IEEE, pp , June [7] J. Rivas, Radio frequency dc-dc power conversion, Ph.D. dissertation, Massachusetts Institute of Technology, September [8] Z. Kaczmarczyk, High-efficiency class E,EF 2, and E/F inverters, IEEE Transactions on Industrial Electronics, vol. 5, no. 5, pp , Oct [9] R. Redl, B. Molnar, and N. Sokal, Class E resonant regulated dc/dc power converters: Analysis of operations, and experimental results at 1.5MHz, IEEE Transactions on Power Electronics, vol. 1, no. 2, pp , April [10] N. Sokal and A. Sokal, Class E-A new class of high-efficiency tuned single-ended switching power amplifiers, IEEE Journal of Solid-State Circuits, vol. 10, no., pp , June [11] S.-A. El-Hamamsy, Design of high-efficiency RF class-d power amplifier, IEEE Transactions on Power Electronics, vol. 9, no., pp , May [12] S. Lu, Y. Sun, M. Goldbeck, D. Zimmanck, and C. Sullivan, 0-MHz power inductor using nanogranular magnetic material, in Power Electronics Specialists Conference, PESC IEEE, 2007, pp [1] J. Rivas, R. Wahby, J. Shafran, and D. Perreault, New architectures for radio-frequency DC/DC power conversion, in IEEE 5th Annual Power Electronics Specialists Conference PESC 04, vol. 5, June 2004, pp [14] M. Kazimierczuk and J. Jozwik, Resonant dc/dc converter with class-e inverter and class-e rectifier, IEEE Transactions on Industrial Electronics,, vol. 6, no. 4, pp , [15] IXYS Corporation, IXZR08N120 Datasheet, April [16] J. M. Rivas, Y. Han, O. Leitermann, A. Sagneri, and D. J. Perreault, A high-frequency resonant inverter topology with low voltage stress, 2007 IEEE Power Electronics Specialists Conference (PESC 2007), pp , June [17] B. J. Baliga, Power Semiconductor Devices. PWS Publishing Company, [18] J. Glaser and A. Witulski, Output plane analysis of load-sharing in multiple-module converter systems, IEEE Transactions on Power Electronics, vol. 9, no. 1, pp. 4 50, [19] K. Matocha, J. Tucker, S. Arthur, M. Schutten, J. Nasadoski, J. Glaser, and L. Stevanovic, Low output capacitance 1500V 4H-SiC MOSFETs with 8 mw-cm2 specific on-resistance, in Proceedings of 6th Annual European Conference on Silicon Carbide and Related Materials (ECSCRM 2006), /09/$ IEEE 1128