Dynamic Duty Cycle and Frequency Controller

Transcription

1 1 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA FPGA-based Dynamic Duty Cycle and Frequency Controller for a Class-E 2 DC-DC Converter May 21st, 2018 Sanghyeon Park and Juan Rivas-Davila spark15@stanford.edu SUPER Lab, Stanford University, USA

2 2 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Basic structure of ac-dc converters 60Hz, 110V Rectifier Unregulated DC DC-DC Converter Regulated DC galvanic isolation

3 3 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA The scope of this work 60Hz, 110V Rectifier Unregulated DC DC-DC Converter Regulated DC galvanic isolation

4 Class-E 2 dc-dc converter : It consists of a class-e inverter (left) and a class-e rectifier (right). 4 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Class-E Inverter Linv Class-E Rectifier Ls Cs Lrect Iout Vin Q Cinv D Crect a Vout [1] N. O. Sokal and A. D. Sokal, "Class E-A new class of high-efficiency tuned single-ended switching power amplifiers," IEEE Journal of Solid-State Circuits, vol. 10, no. 3, pp , Jun [2] R. Zulinski and J. Steadman, "Class E Power Amplifiers and Frequency Multipliers with finite DC-Feed Inductance," IEEE Transactions on Circuits and Systems, vol. 34, no. 9, pp , September [3] M. K. Kazimierczuk and J. Jozwik, "Resonant DC/DC converter with class-e inverter and class-e rectifier," IEEE Transactions on Industrial Electronics, vol. 36, no. 4, pp , Nov 1989.

5 5 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Class-E 2 dc-dc converter : Class-E topology achieves zero-voltage and zero-dv/dt switching. On Off On Off Class-E Inverter Vin Iin Linv Q Cinv Vin = 80 V sinusoidal current Is Class-E Rectifier Vout = 12 V sinusoidal current Is D a Crect Lrect Vout Iout

6 Class-E 2 dc-dc converter : The major downside is the circuit s sensitivity to input and output voltages. Lossy switching 6 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Class-E Inverter Vin Linv Q Vin = 80 V sinusoidal current Is Class-E Rectifier Vout = 12 V sinusoidal current Is D a Crect Lrect Vout 20 V Iin Cinv Iout

7 Class-E 2 dc-dc converter : The major downside is the circuit s sensitivity to input and output voltages. Lossy switching 7 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Class-E Inverter Vin Iin Linv Q Cinv Vin = 80 V sinusoidal current Is 160 V Class-E Rectifier Vout = 12 V sinusoidal current Is D a Crect Lrect Vout Iout

8 8 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Previous works : Resistance compression network Y. Han, O. Leitermann, D. A. Jackson, J. M. Rivas and D. J. Perreault, "Resistance Compression Networks for Radio- Frequency Power Conversion," IEEE Transactions on Power Electronics, vol. 22, no. 1, pp , Jan

9 9 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Previous works : Consistant zero-crossing timing L. Roslaniec, A. S. Jurkov, A. A. Bastami and D. J. Perreault, "Design of Single-Switch Inverters for Variable Resistance/Load Modulation Operation," IEEE Transactions on Power Electronics, vol. 30, no. 6, pp , June 2015.

10 Proposed method : Dynamic duty cycle and frequency S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 10 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

11 Class-E 2 dc-dc converter implementation for testing 11 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA dc blocking cap Linv Lm Lrect Vin Vout Cinv Crect is equivalent to k' Class-E Inverter Class-E Rectifier Lp' Ls We implement this structure. nvin Cinv /n 2 Class-E Inverter Crect Vout Class-E Rectifier S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.

12 Class-E 2 dc-dc converter implementation for testing 12 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Lp Ls Vin Crect Cin gate driving signal gate buffer Q D Cout Vout Cinv S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.

13 Class-E 2 dc-dc converter implementation for testing 13 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA 675/48 Litz wire GaN transistor (GS66502B) Si diode (MBR5H100MFS) S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.

14 Class-E 2 dc-dc converter implementation for testing 14 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Lp = 2000 nh Ls = 499 nh k = 0.26 Crect = 6 nf Cinv = 3 nf S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.

15 Experimental setup for testing dynamic duty cycle and frequency control 15 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA signal generator 6V gate signal power supply Vin power supply oscilloscope electronic load dc-dc converter thermal camera S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.

16 Measured waveforms of the voltage across the inverter transistor : It maintains zero-voltage and zero-dv/dt switching for Vin = V. S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 16 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

17 Measured waveforms of the voltage across the rectifier diode : It maintains zero-voltage and zero-dv/dt switching for Vin = V. S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 17 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

18 The d-f modulation strategy calls for a dedicated controller design. Inverter transistor duty cycle experimental theoretical S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 18 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

19 The d-f modulation strategy calls for a dedicated controller design. Inverter transistor duty cycle Switching experimental frequency theoretical experimental theoretical S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 19 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

20 The d-f modulation strategy calls for a dedicated controller design. Inverter transistor duty cycle Switching experimental frequency experimental We need a controller that changes the duty cycle and frequency of the gate driving signal, depending on the in/out voltages. S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output Voltage Ranges," IEEE Trans. Power Electronics, in press. 20 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA

21 The d-f modulation strategy calls for a dedicated controller design. 21 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Load variation

22 The d-f modulation strategy calls for a dedicated controller design. 22 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA On-off control for output voltage regulation under the load variation off off on on on off Load variation

23 The d-f modulation strategy calls for a dedicated controller design. 23 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA On-off control for output voltage regulation under the load variation off off on on on off Vin = 80 V 200 V Vout = 5 V 20 V Load variation

24 24 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA The d-f modulation strategy calls for a dedicated controller design. d-f modulation to minimize the switching loss under input / output voltage variations On-off control for output voltage regulation under the load variation gate driving signal Vin = 80 V 200 V off off on on on Vout = 5 V 20 V Load variation off

25 The controller prototype using Mojo v3 FPGA 25 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Mojo v3 FPGA development board - Xilinx Spartan 6 FPGA - ADC with 8 input channels - Clock speed up to 300 MHz - 84 digital input/output pins

26 The controller prototype using Mojo v3 FPGA 26 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA User-selectable output voltage Gate driving signal - on-off controlled - d-f modulated Mojo v3 FPGA development board - Xilinx Spartan 6 FPGA - ADC with 8 input channels - Clock speed up to 300 MHz - 84 digital input/output pins Vout to ADC input Vin to ADC input

27 27 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Design details of the FPGA-based controller lookup_table Vin,Vout LUT sw_period duty_cycle

28 28 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Design details of the FPGA-based controller lookup_table Vin,Vout LUT pwm sw_period counter duty_cycle sw_period duty_cycle gate_drv_sig

29 29 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Design details of the FPGA-based controller lookup_table Vin,Vout LUT pwm sw_period counter duty_cycle sw_period duty_cycle on_off_ctrl Vout < Vout,target? gate_drv_sig gate_drv_sig on-off gate driving signal

30 Schematic of the controller and peripheral circuits 30 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA V k D + Vin Cin Q Lp Cinv Ls Crect 5-20V Cout + Vout gate driving signal V FPGA controller Vout selection bits unity-gain isolation amplifier V

31 Controller implementation 31 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA ADC input ports (under the controller board) Vin gate driving signal extra Cout Vout,target selection switch FPGA board isolation amplifier Vout controller board

32 Experimental setup for testing the controller aux power supplies Vin power supply oscilloscope thermal camera electronic load dc-dc converter May 21, 2018 IPEC-Niigata / 48 controller Sanghyeon Park, SUPER Lab, Stanford University, USA

33 Experimental setup for testing the controller 33 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Class-E 2 dc-dc converter controller

34 34 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage Vin = 120 V, Rload = 10 Ω Vout from 5 V to 9 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div

35 35 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage Vin = 120 V, Rload = 10 Ω Vout from 9 V to 12 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div

36 36 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage Vin = 120 V, Rload = 20 Ω Vout from 12 V to 20 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div

37 37 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage : closer look Vin = 120 V, Vout = 5 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div d = 0.10, f = 2.07 MHz horizontal timescale 200 ns/div

38 38 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage : closer look Vin = 120 V, Vout = 9 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div d = 0.12, f = 2.06 MHz horizontal timescale 200 ns/div

39 39 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage : closer look Vin = 120 V, Vout = 12 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div d = 0.14, f = 2.04 MHz horizontal timescale 200 ns/div

40 40 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the output voltage : closer look Vin = 120 V, Vout = 20 V voltage across inv. transistor 100 V/div voltage across rect. diode 20 V/div output voltage 5 V/div gate driving signal 5 V/div d = 0.16, f = 1.94 MHz horizontal timescale 200 ns/div

41 41 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Step change in the load resistance from 7 Ω to 30 Ω Vin = 120 V, Vout = 12 V voltage across inv. transistor 100 V/div voltage across rect. diode 50 V/div output voltage 5 V/div gate driving signal 5 V/div

42 Efficiency at different output powers 42 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Vin = 80 V Vin = 120 V

43 Efficiency at different output powers 43 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Vin = 80 V Vin = 120 V Synchronous rectification and a low-μ magnetic core achieve % efficiency (80 V-to-20 V conversion). S. Park and J. Rivas, "Isolated Resonant DC-DC Converters with a Loosely Coupled Transformer, " in Control and Modeli ng for Power Electroni cs (COMPEL), Jul

44 Efficiency at different output powers 44 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Vin = 160 V Vin = 200 V

45 Comparison with and without dynamic duty cycle and frequency : Efficiency drops when duty cycle and frequency are fixed instead of being dynamically changed (Rload = 20 Ω) 45 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Vin = V, Vout = 12 V Vin = 120 V, Vout = 5-20 V

46 46 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Comparison with and without dynamic duty cycle and frequency Vin = 120 V, Vout = 12 V, Rload = 20 Ω Normal operation rectifier diode : 31 C When d and f are mistuned to Vout of 5 V rectifier diode : 31 C Reference picture rectifier diode inverter transistor : 29 C inverter transistor : 35 C efficiency = 77 % efficiency = 74 % inverter transistor

47 47 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Comparison with and without dynamic duty cycle and frequency Vin = 120 V, Vout = 12 V, Rload = 20 Ω Lossy switching voltage across inv. transistor 100 V/div voltage across rect. diode 50 V/div output voltage 5 V/div gate driving signal, 5 V/div, mistuned to Vout of 5 V d = 0.10, f = 2.07 MHz horizontal timescale 200 ns/div

48 48 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USA Summary Class-E 2 dc-dc converter loses its zero-voltage and zero-dv/dt switching when the input and output voltage changes. We found that we can solve the problem by changing the gate driving signal s duty cycle and frequency. We developed a controller that reads the input / output voltages and drives the transistor with appropriate duty cycle and frequency. The controller regulates the output voltage by on-off control scheme.