FREQUENCY DIVISION MULTIPLE ACCESS RECEIVER FOR WIRELESS INTERCONNECTION ON PRINTED CIRCUIT BOARDS

Transcription

1 FREQUENCY DIVISION MULTIPLE ACCESS RECEIVER FOR WIRELESS INTERCONNECTION ON PRINTED CIRCUIT BOARDS By MINSOON HWANG A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA

2 2011 Minsoon Hwang 2

3 To my wife, son, daughter and parents 3

4 ACKNOWLEDGMENTS I want to express my deep gratitude and appreciation to my advisor, Professor Kenneth K. O, for his patient, constant encouragement and devotion. He guided me through the transition from a student to an electrical engineer. Under his supervision, I had opportunities to work in microelectronics, which eventually became a joy for me. Also much appreciation goes to Professor William Eisenstadt, Huikai Xie and Professor Namho Kim for their helpful suggestions to my research. I would like to thank them for their interests in this work and serving on my Ph.D. supervisory committee Much appreciation goes to TOYOTA Motor Corporation for funding this work and Dr. Janshen Lin and Dr. Rizwan Bashillulah to help me with measurement equipment. I also would like to thank the SiMICS members Yu Su, Yanping Ding, Eunyoung Seok, Swaminathan Sankaran, Kwangchun Jung, Chikuang Yu, Haifeng Xu, Jau-Jr Lin, Ning Zhang, Hisnta Wu, Chuying Mao, Dongha shim, Tie Sun, Hsinta Wu, Dongha Shim, Tie Sun, Wuttichai Lerdsitomboon, Ruonan Han, Dr. Choongyul cha, and Kyungsun Seol. It was quite fortunate to have worked with my colleagues. The discussions with them and their advice were immensely helpful for completing this work. Finally, I deeply thank to my wife, son, daughter and parents for their love and support through the lengthy Ph.D. program. 4

5 TABLE OF CONTENTS page ACKNOWLEDGMENTS... 4 LIST OF TABLES... 7 LIST OF FIGURES... 8 LIST OF ABBREVIATIONS ABSTRACT CHAPTER 1 INTRODUCTION Hybrid Circuit Board Using Photo Couplers How to Improve Hybrid Engine Controller Board Organization of the Dissertation SYSTEM OVERVIEW Hybrid Engine Controller Communication System FDMA Channel Link Analysis FDMA Receiver Architecture RF TO IF CONVERSION OF FDMA RECEIVER On-Chip Antenna and Duplexer Overview of On-Chip Antenna Duplexer Broadband Low Noise Amplifier Band Pass Filter Broadband RF Amplifier Broadband Down Conversion Mixer INTERMEDIATE FREQUENCY TO BASEBAND CONVERSION IF-to Baseband Conversion System Intermediate Frequency Amplifier IF to BB Down Conversion Mixer Baseband Architecture Measurement Results SYNTHESES OF MULTIPLE INTERMEDIATE FREQUENCIES Background of Frequency Generation

6 5.2 Frequency Generation and Duty Correction Phase Generation Measurement of Test Structure Summary FDMA RECEIVER CHARACTERIZATION Test Structure Measurements of FDMA Receiver Chain RF Front-End Measurements RF-to-Baseband Converter measurements Time Shared FDMA Receiver SUMMARY AND SUGGESTED FUTURE WORKS Summary Suggested Future Work LIST OF REFERENCES BIOGRAPHICAL SKETCH

7 LIST OF TABLES Table page 2-1 Frequency plan for Channels of CDMA and FDMA link ( unit : GHz) Link margin analysis for the FDMA channel link Specification of the on-chip duplexer [28] Bandwidth versus n [42] Performance of LNAs over 20 GHz Intermediate frequency and frequency divider ratio Phases difference generated by IF generator according to frequencies Frequency and phase selection Summary of IF generator measurement

8 LIST OF FIGURES Figure page 1-1 Hybrid cars selling in North America [1] [7] Hybrid engine controller board Two approaches to replace photo-couplers Communication system architecture of the hybrid engine controller board Block diagram of transceiver for the controller section with an FDMA transmitter and a CDMA receiver Block diagram of transceiver architecture for the Deadtime controller with a CDMA transmitter and an FDMA receiver The Proposed architecture of FDMA receiver Frequency plan for down conversion scheme of FDMA receiver On-chip antenna A) Die photo of an on-chip antenna fabricated using UMC 130nm CMOS technology B) Cross section of an on-chip antenna mm zigzag antenna radiation pattern at 24 GHz [22] Antenna pair gain versus distance in the lobby of new engineering Building at 24 GHz Measurement points chosen on the PCB [28] Large scale fading channel measurement results Schematic of the single-ended on-chip duplexer [29] Die photo of the single-ended on-chip duplexer Schematics of broadband LNA Schematic of 5-stages gain distributed broadband differential LNA Simple diagram and equivalent circuit of common source (CS) LNA A) Simple CS LNA schematic B) Equivalent circuit of CS LNA Noise model of CS LNA Schematic of differential common source (CS) amplifier with source degeneration inductor

9 3-14 Simulation results of differential common source (CS) LNA. Overall gain and gain of each stage versus frequency The S-parameter and noise figure simulation results of differential common source (CS) LNA Measurement setup for 5 stage gain distributed differential LNA Characterization set up for Balun plus GSSG probe using a network analyzer.[46] Measurement setup for single ended mode Simulated S parameters and Noise Figure in single ended mode and differential mode A) S11 B) S21 C) S22 D) Noise Figure Measured S-parameters in single ended mode Deembeded S 21 and noise figure of LNA A) S 21 B) noise figure Linearity measurement result of LNA A) IP 1dB B) IIP Die photo of common source (CS) LNA Frequency plan of RF to IF conversion Schematic of 3 rd order Chevyshev band pass filter (BPF) S-parameter simulation results versus frequency of 3 rd order Chevyshev band pass filter (BPF) Simulated phase versus frequency of 3 rd order Chevyshev band pass filter (BPF) with ideal LC components and LC components including parasitics Die photograph of 3 rd order Chevyshev band pass filter (BPF) Schematic of a 3-stages gain distributed cascode RF amplifier (RFA) S parameter measurement results of a 3-stages gain distributed cascode RFA and a bandpass filter in single ended mode Measured S 21 in single ended mode and deembeded one in differential mode of a bandpass filter and a RFA Measured noise Figure in single ended mode and deembeded one in differential mode of a bandpass filter and a RFA Linearity measurement results of bandpass filter (BPF) and RFA combination A) I P1dB B) IIP

10 3-35 Single-balanced mixer A) schematic B) functional representation for the large switching signals Double balanced Gilbert cell mixer Frequency translation of white noise in transconductor stage Time varying transconductance of the switching pair and the PSD of generated thermal noise [52] Schematic of double balanced Gilbert cell mixer with source degeneration inductors Voltage gain versus intermediate frequency (IF) as function of load resistance Voltage gain and power gain versus input power Noise figure versus intermediate frequency (IF) as function of load resistance Die photograph and layout of broadband double balanced Gilbert cell mixer A) Die photograph B) Layout Block diagram for IF to baseband conversion Schematic of broadband IF amplifier with resistive feedback Schematic of single stage of resistive feedback inverter and equivalent circuit Layout of a differential IF amplifier with resistive feedback Frequency plan of IF to BB conversion Zero IF down conversion scheme using simple homodyne architecture Square wave with 50% duty cycle Power spectral density (PSD) of square wave with 50 % duty cycle Schematic of double balanced Gilbert cell mixer Layout of double balanced Gilbert cell mixer Block diagram of baseband section of the FDAM receiver Schematic of the third order low pass filter Layout of the third order low pass filter

11 4-15 Schematic of 3-stage baseband amplifier Layout of the baseband amplifier Schematic of comparator and SR latch Layout of comparator and SR latch Measurement setup and test structure of the mixer and baseband amplifier integrated with an FDMA receiver Input measurement scheme of IF to BB converter test structure Measurement setup and PCB board of IF to BB converter test structure Measurement results of IF to baseband conversion stage Measurement results of LPF and baseband amplifier A) Frequency response at baseband B) Gain of the LPF and BB amplifier Simplified frequency generation scheme Generation of 2.8 GHz using a mixer and a high pass filter (HPF) Schematic of current mode logic (CML) static divide-by-2 based on a D flipflop [70] A) Block diagram of divide-by-2 circuit B) Schematic Block diagram and waveforms of a divide-by Duty cycle correction scheme for the divide-by-2.5 and waveform to generate 2.4 GHz output Block diagram and waveforms of a divide-by-1.5 circuit Duty correction scheme for the divide-by-1.5 and waveforms Block diagram and waveforms of a divide-by-3 circuit using three dual edge triggered flip-flops (DEDFFs) Waveforms of a divide- by-2 circuit Waveforms of a divide-by Waveforms of a divide-by Measurement scheme and Die photograph of IF generator A) Measurement scheme and layout B) Die photograph Printed Circuit Board (PCB) of IF generator testing

12 5-15 Measurement setup for IF generator testing Output spectra of IF generator A) 400 MHz B) 800 MHz C) 1.2 GHz D) 1.5 GHz E) 2.0 GHz F) 2.4 GHz G) 3.0 GHz Measured duty cycle ratio of output waveforms of IF generator in the Oscilloscope Agilent infiniium 86100B Measured output waveforms of 400 MHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 800 MHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 1.2 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 1.5 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 2.0 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 2.4 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured output waveforms of 3.0 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH Measured Phase Noise of each channel and input reference signal Test structure of FDMA receiver Test scheme and measurement setup of FDMA receiver Die photo of transceiver at Deadtime controller Measurement scheme for RF Front-End of FDMA receiver Measurement results of Duplexer for Antenna and FDMA receiver ports [72] Gain of RF-Front-End of FDMA receiver Measurement setup of IF to BB Down conversion Measured output power of IF-to-BB Mixer and Baseband amplifier (BBA) with -50 dbm RF input power for each channels Gain of LNA to Baseband amplifier of FDMA receiver

13 6-10 Measurement setup for ASK modulated data of FDMA receiver Spectrum of ASK modulated PRBS data Output waveforms of IF-to BB Mixer and ones of Inverted input data with 50 Mbps data rate A) Pattern B) PRBS data Output waveforms of FDMA receiver and ones of Inverted input data with 50 Mbps data rate A) B) Noise Figure measurement result of FDMA receiver Linearity measurement result of FDMA receiver A) IP 1dB B) IIP Block diagram of time shared FDMA receiver architecture Channel selection scheme of time shared FDMA receiver Block diagram of 1-to-7 serial to parallel converter Test plan with two PCB board for the time shared FDMA receiver Test structure of time shared FDMA receiver for three channels Waveforms of test structure of time shared FDMA receiver for two channels Output and selector waveforms of test structure of time shared FDMA receiver for two channels A) IF-to BB Mixer output B) Buffer output

14 LIST OF ABBREVIATIONS BB BPF C CDMA CMOS CS FDMA HPF GSSG IF IIP 3 IP1 db L LC LPF LNA NF PCB Q R RC RF RFA SR Latch Baseband Band Pass Filter Capacitor Code Division Multiple Access Complementary Metal Oxide Semiconductor Common source Frequency Division Multiple Access High Pass Filter Ground-Signal-Signal-Ground Intermediate Frequency Input Third Order Intermodulation Intercept Point 1dB Input Compression Point Inductor Inductor-Capacitor Inductor-Capacitor Low Pass Filter Noise Figure Printed Circuit Board Quality Factor Resistor Resistor-Capacitor Radio Frequency Radio Frequency Amplifier Set-Reset Latch 14

15 RX TX Receiver Transmitter 15

16 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy FREQUENCY DIVISION MULTIPLE ACCESS RECEIVER FOR WIRELESS INTERCONNECTION ON PRINTED CIRCUIT BOARDS By Minsoon Hwang August 2011 Chair: Kenneth K. O Major: Electrical and Computer Engineering The return voltage levels of high voltage motor drive sections and a low voltage digital control section in an engine controller board of a Hybrid Electric Vehicles (HEV) can differ by several hundreds of volts. Presently, the board utilizes numerous photocouplers that can support ~1 Mbps data rate. Use of wireless inter-chip data communication utilizing single chip radio integrating on-chip antennas to isolate return paths is proposed. In particular, for communication from high voltage section to the low voltage section, FDMA is selected to support seven data channels. An FMDA receiver that can support seven 400-MHz channels form 24.2 to 27.2 GHz is implemented in the UMC 130 nm logic CMOS process. There are two major parts in the FDMA receiver: receiver and local oscillator generation blocks. A five stage gain distributed LNA, a BPF and three stage distributed RFA have been demonstrated. The LNA has 19-dB gain and 5.7-dB noise figure at 30 GHz consuming 49.5-mW power. The BPF and RFA combination has 5.2-dB gain and db noise figure at 30 GHz. The IF LO generator has been demonstrated. It utilizes only dividers composed of DFF and buffers, and does not require a mixer or a filter. Dividers are shared and the 16

17 total numbers of dividers in is only nine. To reduce the even harmonic effect, every LO outputs have 50% duty cycle and their deviation is less that ±5% in single ended measurements and ±1% in differential measurements. Each LO signal has two selectable phases with difference greater than 60 o. The phase offsets from the targets are less than 8%. A full FDMA receiver test structure has been demonstrated for seven channels. The channels were characterized one at a time using a multiplexer that selects the IF LO frequency. The gain of receiver from LNA to Baseband amplifier is 40 db and noise figure is 8.7 db at 27 GHz at mW power consumption. Time shared FDMA receiver operation has been demonstrated up to data rate of 10 Mbps. Two channels are time shared using selection signal. It multiplexes two LO signals with different frequencies. 17

18 CHAPTER 1 INTRODUCTION 1.1 Hybrid Circuit Board Using Photo Couplers Recently Hybrid electric Vehicles (HEV s) have become popular item in the automobile industry with the increasing gasoline price and the enactment of regulations for carbon dioxide emissions in some countries. Because HEV s have ~ 50% higher gasoline mileage comparing with the same size vehicles with a gasoline only engine, HEV s can reduce the amount of carbon dioxide emission. HEV s have been called environment-friendly or eco-friendly cars. Many automobile makers have been developing hybrid electric vehicles shown in Figure 1.1. Figure 1-1. Hybrid cars selling in North America [1] - [7] One of drawbacks of the HEV s is high price. Lowering manufacturing cost has been the main issue to make them widely accepted and utilized. There are so many parts in an automobile. One of them is the hybrid engine controller board which checks the statues and controls the operation of engine. 18

19 Figure 1-2. Hybrid engine controller board A hybrid engine controller board is shown in Figure1.2. This has photo-couplers to communicate between the high voltage motor drive and low voltage control sections. This research focuses on lowering the cost and improving the performance of hybrid engine controller board by finding a new cheaper and better way to communicate between sections. This proposed research investigates an approach using complementary metal oxide semiconductor (CMOS) technology that reduces the number of components for inter-chip communication and cost. 1.2 How to Improve Hybrid Engine Controller Board The reason to use photo-couplers in the hybrid engine controller board shown in Figure 1-2 is due to the potential difference in the signal return paths. This board is 19

20 divided into two sections. One is the motor driver section that operates in high voltage. The potential difference between the return paths can be as high as 300V. The other is control section that operates at lows between 3 to 12 V. Photo-couplers, however, have normally low transmission data rate of ~ 1 Mbits/sec. and costs ~ $1. For higher data rate, they can cost up to many dollars. 1.2 V V TX RX 0 V Single chip 300 V A TX Wireless RX PLL RX TX PLL Motor Controller Deadtime controller B Figure 1-3. Two approaches to replace photo-couplers A) Inductive coupling with transformer in a single chip B) Wireless interconnection with on-chip antenna Two approaches to replace photo couplers in the board have proposed [8]. The left diagram in Figure 1-3 is an isolator that uses inductive coupling with a transformer. The right one is a transceiver with on- chip antennas. The first approach was investigated by Hsinta Wu using UMC 0.13 µm standard CMOS technology. The 20

21 isolator could support 160 Mbits/sec. data rate at 70 V. The result was not sufficient to support the 300-V difference due to the break down voltage limitation. For the second approach, the feasibility of using on-chip antennas for wireless communications have been studied [9]-[12] and integrated with other circuit blocks. Communication using onchip antenna is possible at 5 GHz and higher [13] [14]. There are 26 photo couplers in the hybrid engine controller board. The focus of this proposed research is to optimize transceivers with an on-chip antenna that can be used for communication from the high voltage section to low voltage section. Figure 1-4. Communication system architecture of the hybrid engine controller board The communication system architecture of the hybrid engine board is shown in Figure 1-4 [15]. This block diagram describe a half of the full system. There are 13 channels. This system consists of a Deadtime controller in the control section and 6 drivers and a temperature sensor in the motor section. Two different multiple access methods are adapted for this system. The uplink uses frequency division multiple access (FDMA), while the downlink uses code division multiple access (CDMA). The 21

22 proposed research focuses on the receiver part of FDMA link and seeks that works with the transmitter demonstrated by Hsinta Wu [15]. 1.3 Organization of the Dissertation First, the system and FDMA link will be discussed and the FDMA receiver architecture are proposed in Chapter 2. In Chapter 3, radio frequency (RF) to intermediate frequency (IF) conversion scheme are presented. Components compromising the RF-font-end such as on-chip antenna, duplexer, broadband low noise amplifier (LNA), band pass filter, RF amplifier, and broadband double balanced down conversion mixer are discussed. In Chapter 4, IF to baseband conversion stage is introduced, and IF amplifier and IF to baseband mixer are discussed. In Chapter 5, the synthesis of local oscillator signals at multiple intermediate frequencies is discussed. Generating seven different frequencies with two phases using simple and small circuits such as dividers composed of D flip-flops is discussed. In Chapter 6, the baseband architecture including components such as 3 rd order low pass filter (LPF), baseband amplifier, comparator and latch is discussed. In Chapter 7, measurement results of FDMA receiver are presented. A time shared architecture for the FDMA receiver are discussed and preliminary operation is demonstrated in Chapter 9. Lastly in Chapter 10, the dissertation is summarized and future works are suggested 22

23 CHAPTER 2 SYSTEM OVERVIEW 2.1 Hybrid Engine Controller Communication System In the wireless interconnection system, there are two links, CDMA for down link, FDAM for uplink [16]. Channelization is needed for the communication system to support multiple channels. First looking at the requirement of CMDA link, the data rate of each channel is 50 Mbps. The Walsh code is widely used for CDMA system. It has N orthogonal codes per N bits (N is 1, 2, 4, 8,, 2 N ). Because there are six channels in the CDMA link, 8 Walsh codes are required and chip rate is 400 Mcps (Mega chips per second) or 8 times the data rate. A square wave has ~ 80% of the signal energy within the first 3 harmonics. To capture these, the baseband bandwidth for CDMA links was set to three times the chip rate, The RF bandwidth of CDMA link is 2.4 GHz which is twice the bandwidth at baseband for an AM system [17]. The CDMA down link for six channels are allocated at 16.8 GHz with a single carrier and data are spread from 15.6 to 18 GHz as shown in Table 2-1. The FDMA link, on the other hand, has seven channels with 50 Mbps data rate for each. A channel of FDAM link occupies 300 MHz bandwidth. The seven channels are allocated at 24.4, 24.8, 25.2, 25.5, 26.0, 26.4, and 30.0 GHz. To support the multiple access schemes, an FDMA receiver and a CDMA transmitter are needed for the Deadtime controller in the control section. In the motor section, an FDMA transmitter and a CDMA receiver are needed. A block diagram of transceiver for the motor section is shown in Figure 2-1[18]. This is composed of an FDMA transmitter, a CDMA receiver, PLL and clock data recovery (CDR) for LO frequency generation and data recovery, and a 3-bit analog to digital converter. 23

24 Table 2-1. Frequency plan for Channels of CDMA and FDMA link ( unit : GHz) TX Channel Freq. Band RX Channel Freq. Band Chip Motor Controller , C1 M , C2 M , C3 M , C4 M , C5 M , C6 M M7 Deadtime Controller , C , C , C , C D , C , C Figure 2-1. Block diagram of transceiver for the controller section with an FDMA transmitter and a CDMA receiver 24

25 The proposed architecture of other transceiver for the Deadtime controller side is shown in Figure 2-2. There are two sections; a CDMA transmitter and an FDMA receiver. The Deadtime controller sends signals to six CDMA receivers in Figure 1-4 through a duplexer and an on-chip antenna sharing with the FDMA receiver. The latter has wider bandwidth than its counterpart transmitter because of the guard bands. Each components of the FDMA receiver must support 3 GHz bandwidth. Figure 2-2. Block diagram of transceiver architecture for the Deadtime controller with a CDMA transmitter and an FDMA receiver 2.2 FDMA Channel Link Analysis The FDMA link in the hybrid engine controller board must support data rate of 50 Mbps/channel, latency less than 2 µs and a range of up to 15 cm. The board size is 15 cm x 25 cm. The link margin analysis of FDMA channel is shown in Table 2-2. The maximum distance between chips is 15 cm and E b /N o is 14.5 db for Amplitude shift 25

26 keying (ASK) modulation to achieve 1X10-13 BER [19]. The sensitivity of this link is dbm when the noise figure of a receiver is assumed 8 db. Assuming that an on-chip antenna on a 100-μm thick substrate has a -7 db of antenna gain, the received power is -57 dbm when the output power level of a transmitter is 3 dbm and propagation loss is 46 db at the highest possible frequency of 32 GHz for the proposed system. The link margin of FDMA channel, therefore, is 17.3 db. Table 2-2. Link margin analysis for the FDMA channel link FDMA link Range (R) TX Power Propagation 32 GHz (λ/4πr) 2 Antenna Gain (0.25λ = 3.2 mm) Received power Thermal Noise [kt ( o K)] Bandwidth (50 MHz) E b /N o for BER of 1x10-13 for ASK RX noise figure Sensitivity Link margin 15 cm 3 dbm 46dB - 7 db -57 dbm dbm/hz 77 db 14.5 db 8 db dbm 17.3 db 2.3 FDMA Receiver Architecture From the link margin analysis and system requirements for the hybrid engine controller board, the architecture and design targets of FDMA receiver are specified in this chapter. Considering the composition and frequency plan of Deadtime controller, a duplexer is needed to isolate FDMA signals at 24.2 to 27.2 GHz from the CDMA ones at 15.6 to 18GHz. Another key to replace the photo couplers is an on-chip antenna integrated with other circuitries There are seven channels from 24.2 through 27.2 GHz. Seven receivers are required to down-convert seven different channels at the same 26

27 time. This scheme, however, need more space and power. Simplification is needed to lower cost. For instant, the RF front-end components such as a low noise amplifier (LNA), a band pass filter (BPF), an RF to IF down-conversion mixer, and IF amplifier (IFA) can be shared. The proposed architecture of FDMA receiver is shown in Figure 2-3. This can be divided into two parts. One is part which converts RF signals coming through an on-chip antenna to baseband signals. Figure 2-3. The Proposed architecture of FDMA receiver The other is a signal generation block with a phase locked loop (PLL) to generate the necessary local oscillator frequencies for the RF to IF down conversion mixer and an IF local oscillator (LO) frequency generator for IF to baseband down conversion mixers. The RF and IF components in the proposed architecture, an LNA, a BPF, a mixer, and an IF amplifier, have broad bandwidth to support the FDMA channels with 3 GHz bandwidth. The number of IF to baseband converters is seven. In the IF stage, the signal of seven channels are allocated at 0.4, 0.8, 1.2, 1.5, 2.0, 2.4, and 3.0 GHz. This means each channel needs different LO frequency for data recovery at the baseband. 27

28 Figure 2-4 shows how each channel is converted down to baseband. First, RF signal is translated to IF using the 24 GHz signal from the PLL. IF signals, then, are converted to baseband using matched IF frequency LO signal. The baseband signals of seven channels are filtered by a low pass filter, amplified, and converted to digital signals by a comparator. For this system, a problem is simultaneously generating the seven different LO signals. A goal of this proposed research is simplifying the architectures. This will be explained in greater detail in Chapter 5. Figure 2-4. Frequency plan for down conversion scheme of FDMA receiver 28

29 CHAPTER 3 RF TO IF CONVERSION OF FDMA RECEIVER 3.1 On-Chip Antenna and Duplexer There are three components shared by a CDMA transmitter and an FDMA receiver in the RF-Front-End of Deadtime controller: an on-chip antenna, a duplexer, a phase locked loop (PLL). As discussed, the important goal in this research is lowering cost. To achieve this reducing external components and increasing efficiency using more on-chip ones and combining common blocks are critical. Most wireless products use external antennas. These are pretty big and occupy a large area in a printed circuit board (PCB) especially when the ground plane area is included. An alternative solution that can lower is an on-chip antenna fabricated in an integrated circuit using metal lines. The study of on-chip antennas spans for over twenty years [20] - [25] and have shown to be possible at frequencies as low as 5.8 GHz [26] Overview of On-Chip Antenna On-chip antennas have been fabricated in a the silicon substrate used in standard CMOS technology. A die photo of dipole fabricated using a copper layer in UMC 130 nm CMOS technology is shown in Figure 3-1. This dipole antenna is 3-mm long and has a zigzag shape which can have higher gain than simple dipoles [27]. The copper layer has 1.5-µm thickness and 30 µm widths, and there is an oxide layer with 3-µm thickness between the metal layer and substrate. Figure 3-1. On-chip antenna A) Die photo of an on-chip antenna fabricated using UMC 130nm CMOS technology B) Cross section of an on-chip antenna. A 29

30 Antenna Oxide (3 µm) Silicon Substrate (670 µm) A Figure 3-1. Continued Figure mm zigzag antenna radiation pattern at 24 GHz [22]. 30

31 Figure 3-3. Antenna pair gain versus distance in the lobby of new engineering Building at 24 GHz. 3-mm on-chip zigzag dipole antennas fabricated on a 20 Ω cm substrate with a 3-µm oxide layer are used for these measurements at 50-cm height from the ground [22]. The substrate thicknesses were 50, 100, and 670 µm.[22] The measured data are shown in Figures 3-2 and 3-3. The former is an antenna pair gain versus distance plot in the air with 3-mm long on-chip zigzag dipole antennas with the substrate thicknesses of 50, 100, 670 µm. The latter is a radiation pattern. Antenna pair gain is improved by thinning the substrate thickness by about 10 db at 50 µm. The radiation pattern is consistent to that of a short dipole [22]. The environment of hybrid engine controller board is different from that of air because there are many obstacles between chips. Some of them have pretty large 31

32 height up to 2.5 cm. The antenna pair gain and radiation pattern will be changed in the PCB boards because of these components. Some points selected to measure antenna pair gain on the PCB board are shown in Figure 3-4. Figure 3-4. Measurement points chosen on the PCB. Photo courtesy of Hainta Wu [28] Antenna pair gain is defined as G a = S ( 1 S11 ) ( 1 S22 ) λ = G tg r 4πR 2 (3-1) Where G t, G r : the transmitting and receiving antenna gain λ is the wavelength in free space R is the distance between the antenna pair The measurement results are shown in Figure 3-5.The substrate thickness is 670 µm. Each point represents the antenna pair gain between two points whose range is

33 to 25 cm. The solid curve is the ideal one in free space based on Equation 3-1 at 24 GHz, assuming G t and G r are 0 db. The maximum distance between a receiver and transmitters is about 15 cm if the receiver of FDMA link is located on the center of board. The sensitivity of FDMA receiver from table 2-2 is dbm. The antenna pair gain requirement is over -71 db with 6 db margin in real environment. Some are not sufficient to meet the requirement. There are two ways to improve the antenna gain. One is to decrease thickness of substrate and the other is to use a metal cover. The measurements for the two cases are shown in Figures 3-5 [28]. Ga (db) _3 1_3 1_3 1_3 4_5 1_2 1_2 4_5 1_2 5_6 5_6 4_7 4_7 6_7 4_7 5_6 6_7 6_7 6_7 w/ cover w/o cover theoretical value in the free space 12_14 11_13 12_14 11_13 11_15 11_15 11_13 11_13 12_14 12_14 11_15 11_15 f = 24 GHz, λ = 12.5 mm Pr λ 1 = GtGr 2 P 4πR R Distance (cm) Figure 3-5. Large scale fading channel measurement results. (11-15 means TX is placed at sampling point 11 and RX is placed at sampling point 15.) Theoretical value is calculated based on Friis formula and using the measured on-chip dipole antenna gains of -12 db [28]. t 2 8_9 8_9 8_9 8_9 8_9 8_10 8_10 8_10 8_10 8_10 At all measurement points, up to 15 cm separation, the antenna pair gain is higher than -68 db. The implementation using an on-chip antenna should be possible based on 33

34 these. An on-chip antenna is integrated with an FDMA receiver chain and a CDMA transmitter in the UMC 130 nm logic CMOS technology Duplexer Another block sharing a CDMA transmitter in the RF-Front-End is a duplexer. SAW filters are used at frequency less than 3 GHz. But In this case, the operating frequency is over 15 GHz. For the transceiver in the Deadtime controller, the duplexer is composed of two third order band stop filters (BSF) as shown in Figure 3-6. There are three ports: an antenna, a CDMA transmitter, and a FDMA receiver. Antenna Duplexer TX BSF BSF RX Figure 3-6. On-chip duplexer using two band stop filters [29]. The operating frequency bands of CDMA link and FDMA link are 15.6 to 18 GHz and 24.2 to 27 GHz. Base on these frequency allocations, the left BSF in Figure 3-6 has a pass band from 15.6 to 18 GHz, and the right BSF has one at 24.2 to 27 GHz. Looking at the specifications for each port of duplexer, insertion loss (IL) is below 3 db in the CDMA band, 15.6 through18 GHz, and in the FDMA band, 24.2 through to 27.2 GHz. Return loss (RL) is below 10 db at each port in their respective pass bands. 34

35 Isolation between TX port and RX port is better than 30 db. These target requirements are summarized in Table 3-1. Table 3-1. Specification of the on-chip duplexer [29] Performance target TX band (PA port) RX band (LNA port) Antenna port PA and LNA Insertion loss Return loss Insertion loss Return loss Return loss Isolation (Rejection) Below 3 db for 15.6 ~ 18 GHz Below 10 db for 15.6 ~ 18 GHz Below 3 db for 24.2 ~ 27 GHz Below 10 db for 24.2 ~ 27 GHz Below 10 db for 15.6 ~ 18 GHz and 24.2 ~ 27 GHz Below 30 db for 15.6 ~ 18 GHz and 24.2 ~ 27 GHz Antenna TX side RX side L a1 L a2 L b1 L b2 PA LNA C a1 C a2 C b1 C b2 L a3 L b3 C a3 C b3 Figure 3-7. Schematic of the single-ended on-chip duplexer [29]. The schematic of single ended on-chip duplexer with two Chevyshev band stop filters (BPFs) using three resonators with inductors and capacitors are shown in Figure 3-7. The band stop filter is used of a low pass filter (LFP) and a high pass filter (HPF). 35

36 For the transmitter side in Figure 3-2, L a1, L a2, and C a3 form a low pass filter (LPF) and C a1, C a2, and L a3 form a high pass filter (HPF). A die photo of the single-ended on-chip duplexer fabricated with an on-chop dipole antenna and a FDMA receiver is shown in Figure 3-8. Figure 3-8. Die photo of the single-ended on-chip duplexer. 3.2 Broadband Low Noise Amplifier The first amplifying stage in the FDMA receiver is a low noise amplifier (LNA) which needs high gain and wide bandwidth to lower noise figure and to cover the 3 GHz bandwidth. Some studies have proposed for broadband LNAs [30]-[35]. A common way is to cascade a few stages of LNA resonated at different frequencies. Another is to use low quality factor (Q-factor) matching networks for input and output. Other is to use a doubly-terminated LC ladder and a three section Chevyshev band pass filter for input 36

37 matching, or shunt RC feedback. Some examples for achieving broad bandwidth are shown in Figure 3-9. Figure 3-9. Schematics of broadband LNA. A) Broadband LNA with low Q matching network [34]. B) LNA with a doubly terminated LC ladder [31]. C) LNA using three section Chevyshev band pass filter [32]. D) An LNA with shunt RC feedback [35]. The architectures in Figures 3-9 (B), (C), and (D) are usually used at frequencies below 10GHz. Even though they have broad bandwidths of 3 to 10 GHz, their noise figure is degraded at the higher end of band. For case (A) in Figure 3-9, the LNA has about 10 db of gain and less than 5 GHz bandwidth around 20 GHz. This gain is modest due to low Q-factor matching networks. The gains of most circuits in the literature do not exceed 15 db of gain near 20 GHz [36] [41]. An easy way to achieve 37

38 higher gain is to cascade more stages. But this reduces bandwidth. To see this, consider a block with unit DC gain and single pole response. The transfer function is defined as 1 H ( s) = τ s + 1 (3-1) If n stages of such blocks are cascaded, the transfer function can be written as 1 H ( s) = τs + 1 n. (3-2) Setting, 1 H ( j ) = = τs + 1 n 1 ω (3-3) The 3-dB bandwidth is n ω 3dB = 2 1 (3-4) τ As n goes to infinity, the overall bandwidth tends to zero. The equation 3-4 can be approximately written using a series expansion of 1/2 1/n [42] ω n 3dB 2 1 τ τ 1 ln 2 n = (3-5) τ n From equation 3-5, the bandwidth decreases as square root of 1/n. Table 3-2 summarizes the bandwidth as function of n. For example, to implement an amplifier with 24 db gain and 5 GHz bandwidth three amplifiers which have 8-dB gain and 10-GHz bandwidth or four stages amplifiers which have 6-dB gain and 12-GHz bandwidth 38

39 should be cascaded according to Table 3-2. It is challenging to achieve over 10-GHz bandwidth near 20GHz. Table 3-2. Bandwidth versus n [42] Actual n bandwidth(normalized) Approximate bandwidth(normalized) Error % For more gain and wider bandwidth, a cascade of low noise amplifiers with varying resonant frequencies is another candidate. A 5-stage gain distributed broadband differential LNA is proposed and shown in Figure It is composed of five cascode common-source (CS) amplifiers with an inductive load and a source degeneration inductor. Each amplifier is designed to have several db gain and about 3-GHz bandwidth. The loads of each stage are resonated at f c GHz or f c - 2.5GHz, and input and output are matched to 50-Ω at f c. 39

40 Figure Schematic of 5-stages gain distributed broadband differential LNA. Figure Simple diagram and equivalent circuit of common source (CS) LNA. A) Simple CS LNA schematic B) Equivalent circuit of CS LNA. Looking at the first stage of 5-stage gain distributed broadband differential LNA, it is composed of an inductor for matching to 50-Ω and a CS LNA. A simplified CS LNA topology is shown in Figure The input impedance of CS LNA is Z s(l L ) 1 g L m in = g + s + + s sc gs C (3-6) gs The effective transconductance of the CS LNA is defined as G m g m1 ωt = g m1q = = ω C (R ω L ) ωt L, (3 7) 0 gs s + T s s ω0 R s(1+ ) R s 40

41 where Q-factor of input network 1 g =, ω = (3 8) m1 Qin T 2ω0C gsrs Cgs If the input is matched to R s, G m g m1 ωt = g m1q = = ω C (R ω L ) ωt L (3 9) 0 gs s + T s s ω0 R s(1+ ) R s The effective transconductance can be written again as G m = 1 2R s ω ω T 0 (3 10) The voltage gain of CS LNA is defined as jg m Z Vout(ω) 1 Av = = Vin(ω) 2 + j( load ω ω g 0 ω0 ( Qgs ) ω ω0 )Qgs ω 1 1 where ω 0 = and Qgs = ( L + L ) C ω C R s gs 0 gs s (3-11) If input is matched to R s and R s = Z Load, A = G v m Z Load 1 = 2R s ω ω T 0 Z Load (3-12) The overall gain of CS LNA can be varied between 3.5 to 8 db because ω T /ω 0 is in the range between 3 to 5 [43]. A noise model of CS LNA is shown in Figure There are three noise sources. One is for the gate inducted noise (i g ), another is channel thermal noise (i d ), and the other is the source noise (v n ). The output noise current is 41

42 i n1 β(z g + Z s ) Z g + Z s + 1 sc gs = ig + id (3-13) 1/sC + Z + (β + 1)Z βz + Z + Z + 1 sc gs g s s g s gs where β = ω T /jω The noise factor is defined as [43] 2 ( 1+ Q ) Qgs γ 2 c γδ 5 + δ gs /5 ω0 F 1 = 1+ + (3-14) Qind Qgs ωt Z g v n i g C gs i β i i d i 1 = i n1 + i n2 Z s Figure Noise model of CS LNA. A cascode topology shown in Figure 3-13 is commonly used to improve the stability, and increases isolation between input and output. Even though the noise contribution of upper transistor M 2 is often neglected at low frequencies for long channel devices with high output resistance, it cannot be ignored around 20 GHz due to the effects of drain-to-body capacitance. The noise factor for a cascode CS LNA is F 2 δ / 5 + γcr 2 c Cr γδ 5 W2 = F1 = 4 2 (3-15) β W 1 β 2 Qgs 1 Where β 1 and β 2 are the current gains and W 1 and W 2 are widths of M 1 and M 2. Increasing the width of M 2 makes β 2 low and increases noise factor. Decreasing the 42

43 width of M 2 lowers the drain voltage of M 1 and bias current which can bias M 1 in the linear region [43]. The optimal value of M 2 is selected as the same as that of M 1 [44], [45]. c L d1 - OUT + L d2 C out1 C out2 C b1 + IN - C in1 C b2 C in2 c L s1 c L s2 L c Figure Schematic of differential common source (CS) amplifier with source degeneration inductor. Figure 3-13 shows a stage of CS amplifier for the 5-stages gain distributed broadband differential LNA. To increase common mode rejection ratio L c resonated with the parasitic capacitances of L s1 and L s2 is added. Source degeneration inductors are added to the input transistors. Inductors used in the load and common node are shielded using a polysilicon patterned ground shield to reduce loss. 43

44 Figure Simulation results of differential common source (CS) LNA. Overall gain and gain of each stage versus frequency Figure The S-parameter and noise figure simulation results of differential common source (CS) LNA. 44

45 Figures 3-14 and 3-15 show the simulation results of the broadband LNA. The overall gain is 25 db at 30 GHz. It is over tuned in simulations to compensate the expected down tuning in the actual silicon. It has 5.5 GHz bandwidth and about 4-dB noise figure in simulations. Agilent E8361A PNA Balun LNA Balun 50Ω 50Ω Figure Measurement setup for 5 stage gain distributed differential LNA. Figure Characterization set up for Balun plus GSSG probe using a network analyzer.[46]. 45

46 A pair of Baluns (Krytar s 180 Hybrid coupler) was used to convert single ended to differential signal at the input, and to combine power of positive and negative nodes of output in the measurement setup shown in Figure To characterize the Balun and GSSG probe, the reflection coefficients (Γ in ) are measured using Open, Short, Load calibration structures. It is assumed that each port of Balun is matched to 50 Ω and balanced between two 3dB ports. The operation frequency range of the Balun which is 6 to 26.5 GHz, however, limited the characterization of Balun because the phases of two 3 db ports are not balanced and matched to 50 Ω above 27 GHz. It is difficult to characterize and get S-parameters of Balun and LNA. The balun complicates the measurement S-parameters of LNA. It is much easier to measure LNA without Balun. An alternative measurement setup is shown in Figure Agilent E8361A PNA LNA 50Ω 50Ω Figure Measurement setup for single ended mode. It is challenging to make differential measurements using a two port Network Analyzer without using Baluns. That means that it is challenging to measure differential 46

47 components such as differential LNA using measurement setup in Figure Even though the measurement results are different from differential measurements, the LNA was simulated in single ended and differential modes and characterized utilizing the simulation result. 6 db 3GHz A B 3 db C D Figure Simulated S parameters and Noise Figure in single ended mode and differential mode A) S11 B) S21 C) S22 D) Noise Figure The simulation results of single ended and differential mode are shown in Figure In Figure 3-19 (A) S 11 in single ended mode, the circuit is tuned at about 3 GHz higher than in differential mode. The node which is connected with L c in Figure 3-13 is not AC Ground any more in the single ended mode. The input impedance of common 47

48 source amplifier is described by Equation 3-6. There is no term related with L c. which must be included in the single ended mode. While S 22 s of LNA in two modes are the same. S 21 is 6 db higher and Noise Figure is 3 db lower in differential mode than these in single ended mode. Figure Measured S-parameters in single ended mode. 3.3GHz A B Figure Deembeded S 21 and noise figure of LNA A) S 21 B) noise figure 48

49 A B Figure Linearity measurement result of LNA A) IP 1dB B) IIP 3 Measurement results of LNA in single ended mode are shown in Figure 3-20 and Intering the differential performance form single ended measurement, gain and noise figure of LNA are achieved about 19 db and 5.7 db at 30.5 GHz with 3.3 GHz 49

50 bandwidth. Input 1 db compression point (IP 1dB ) is -30 dbm and input third order intercept point (IIP 3 ) is -18 dbm. The linearity measurement results are shown in Figure Table 3-3. Performance of LNAs over 20 GHz Process Type f c (GHz) Gain (db) NF (db) BW (GHz) Supply Voltage (V) Power (mw) [36] [37] [38] [39] [40] [41] 0.13-μm SOI CMOS 0.18-μm CMOS 0.18-μm CMOS 0.18-μm CMOS 0.13-μm CMOS 0.13-μm CMOS Differential Single NA Single Single Differential Single This Work* 0.13-μm CMOS Differential These are compared to the performance of LNA s operating over 20 GHz in Table 3-3. Figure 3-23 shows a die photo of 5 stage gain distributed lose noise amplifier (LNA). The die size is 980 µm by 430 µm. 50

51 Figure Die photo of common source (CS) LNA 3.4 Band Pass Filter To select the signal in the desired band and to reject image during RF to IF conversion, a band pass filter (BPF) is need before a mixer. The frequency plan of RF to IF conversion in the FDMA receiver is shown in Figure Images are located at 20.8 to 23.8 GHz when RF band is 24.2 through 27.2 GHz and local oscillator (LO) frequency is 24-GHz. If there is no BPF, RF signal and Image are translated together to the IF band. For the FDMA receiver, a 3 rd order Chevyshev band pass filter (BPF) shown in Figure 3-25 is chosen. It is composed of a pair of three resonators. Figure Frequency plan of RF to IF conversion 51

52 L 1 C 1 C 3 L 3 L 2 C 2 L 2 C 2 L 1 C 1 C 3 L 3 Figure Schematic of 3 rd order Chevyshev band pass filter (BPF) The simulation results of BPF are given in Figures 3-26 and The insertion loss (IL) is 3 db and bandwidth is 6 GHz. The BPF is over tuned at 30 GHz like the LNA. The S-parameter simulation results are shown in Figure 3-25 and phase versus frequency plots are shown in Figure 3-27 for the ideal case (Ideal) using ideal LC components and a more realistic case (Sim.) using LC components including parasitics. Figure S-parameter simulation results versus frequency of 3 rd order Chevyshev band pass filter (BPF) A) S 21 and S 11 versus frequency. B) S 11 versus frequency 52

53 Figure Simulated phase versus frequency of 3 rd order Chevyshev band pass filter (BPF) with ideal LC components and LC components including parasitics Figure Die photograph of 3 rd order Chevyshev band pass filter (BPF) 53

54 3.4 Broadband RF Amplifier A second broadband amplifier is added between the BPF and mixer. A three stages gain distributed cascode broadband RF amplifier uses the same topology as the 5-stage LNA. Each stage is tuned at f c GHz, f c, and f c +2.5-GHz as shown in Figure 3-29, and input and out are tuned at 30 GHz in simulation to compensate the expected down tuning in silicon like that was down for the design of the low noise amplifier and the bandpass filter. The measurement setup and deembeding techniques are the same as LNA. The measurement results are shown in Figures 3-30 through Figure Schematic of a 3-stages gain distributed cascode RF amplifier (RFA) Figure S parameter measurement results of a 3-stages gain distributed cascode RFA and a bandpass filter in single ended mode 54

55 Figure Measured S 21 in single ended mode and deembeded one in differential mode of a bandpass filter and a RFA A Figure Measured noise Figure in single ended mode and deembeded one in differential mode of a bandpass filter and a RFA 55

56 A Figure Linearity measurement results of bandpass filter (BPF) and RFA combination A) I P1dB B) IIP 3 B The deembeded gain of bandpass filter and RF amplifier combination is 5.2 db with 3.2 GHz bandwidth at 30 GHz in differential mode. The expected gain of RFA is about 9 db based on simulations with bandpass filter loss of 4 db. The noise figure of two components is 11.4 db in differential mode. I P1dB is -16 dbm and IIP 3 using two tone 56

57 at 30 and GHz is -6 dbm. The die photo of 3 stage gain distributed amplifier is shown in Figure Figure Die photo of a 3-stages gain distributed cascode RFA 3.5 Broadband Down Conversion Mixer A mixer translates frequency in a wireless system. The carrier frequency of received signal is translated using multiplication with a local oscillator (LO). For LO signals, square wave is generally used instead of sine wave because the former renders mathematically 2 db higher conversion gain [47]. A mixer can be classified as a passive and an active mixer. An active mixer is used for the FDMA receiver. A simple single balanced active CMOS mixer and the functional representation are shown in Figure It is composed of three parts. One is a transconductance stage (M1) to 57

58 convert voltage to current, another is a switching stage (M2 and M3), and the other is a load (two R L s). Figure Single-balanced mixer. A) schematic B) functional representation for the large switching signals When RF input is V B + v RF, where V B is the dc bias voltage and v RF is the small signal RF input voltage, the output current through the left load resistor in Figure 3-35 (A) is defined as [48] I 1 = F( VLO(t),V B vrf ) (3-16) 2 o1 + Assuming that v RF is small, Equation 3-16 can be approximately rewritten using a Taylor series as I o1 F( V = LO (t),v B I B(t) g + 2 F( VLO(t),V ) + V m1 (t)v 2 RF. B B ) 1 v 2 RF (3-17) Similarly, the output current of other side is I o1 I B(t) 2 g (t)v 2 m1 RF (3-18) Therefore, total output current is 58

59 I o = I I 2 g (t)v (3-19) o1 o m1 RF Including LO input signal, if the products from the high order harmonics of LO signals are ignored, the output voltage is approximately [49] V (t) out = g m1 ARL cos(ωrf ωlo )t + cos(ωrf ωlo )t π 2 2 (3-20) Filtering the High frequency term, V (t) out 4 1 = g m1 ARL cos(ωrf ωlo )t (3-21) π 2 Conversion gain is A v = g m 2 1 RL (3-22) π For a single balanced mixer, the switching pair acts like as differential amplifier during portions of operation, and square wave LO signal appear in the spectrum. To remove the undesired output LO components, a double balanced mixer in Figure 3-36 is used [50]. Figure Double balanced Gilbert cell mixer 59

60 g m1 and g m2 are the transconductance of M R1 and M R2. The output current through M R1 and M R2 from Equation 3-19 are, =, = (t)v. (3-19) Io gm1 gm1(t)vrf Io, gm2 gm2 In the case of 50% duty cycle, where TLO is a period of square wave g RF TLO = gm 1(t ) (3-20) 2 m2 + The overall current is I = I ) = o o, gm1 Io, gm2 = ( gm1(t) gm2(t) vrf geff (t)vrf. (3-21) The output voltage of mixer is V out R 2 R 2 L L = ( Io, gm1 Io, gm2) = geff(t)vrf. (3-22) Conversion gain of double balanced mixer can be written as A v R 2 g (t) L = eff. (3-23) The real square wave, however, is not perfect. It has finite slope in the rise and fall transitions. When the transition time is t and g m0 is the magnitude of g m1 and g m2, conversion gain can be approximately rewritten as [51] A v 2 sin( π π π f f LO t) t LO R 2 L g mo. (3-24) The noise generation in the mixers is complicated since the operating point of device is changed periodically with time. Noise comes from the transconductor stage, switching stage, and load [50]. Looking at the noise from the transconductor stage, the 60

61 power spectrum density (PSD) of the drain thermal noise of MOS transistor in saturation region is 2 i f = 4kTγ g m, (3 25) where g m is transconductance, k is the Boltzmann s constant, T is absolute temperature, and γ is 2/3 for long channel devices, and can be higher for short channel devices. For the square wave in LO signal case, the thermal noises of drive stage (M 1 in Figure 3-35, M R1 and M R2 in Figure 3-36) in the odd harmonic frequencies of LO signal are down converted to IF because a square wave is composed of odd harmonics of the fundamental. These noises are not correlated. The noise from f LO ± f IF, from 3f LO ± f IF, and rest of higher order harmonics are 81%, 9% and 10% respectively (Figure 3-37) [52]. Figure Frequency translation of white noise in transconductor stage For a single balanced mixer, PSD is S 0 2 n1 ( f ) α 4kT( Rs + rg 1 + ) gm 1 gm 1 γ = (3 26) For a double balanced mixer when g mr1 = g mr2 and r g1 =r g2, PSD is 61

62 S 2γ 0 2 nr12 ( f ) α 4kT( Rs + 2rgR 1 + ) gmr 1 gmr 1 = (3 27) The second noise source is the thermal noise generated in the switching pair. If transistors M 2 and M 3 in Figure 3-35 are assumed to be in saturation region during ON, the output current determined by tail current and M 1 and M 2 does not contribute noise. If LO is sufficiently high, this noise is smaller than that of drive stage. If both M 2 and M 3 are ON, they cause noise. The instantaneous noise PSD at output port (I o1 ) is 0 g m2gm3 S = n2( f ) 4kTγ. (3 27) gm2 + gm3 Because the noise at one port is twice of I o1, the corresponding output noise PSD is S 0 n23 g ( f ) = 16kTγ gm m2 m3 g where G( t) = 2 gm 2 g + g m3 = 8kTγgG( t), m2 2 g + g m3 m3. (3 28) [52] G(t) is the small signal transconductance. As the amplitude of LO increases, the interval time when both M 2 with M 3 are on decreases and the noise decreases (Figure 3-35). Time averaging the PSD at output, S 0 n23 1 T ( f ) = 8kTγ T 0 LO I B where G = 2 πv LO o G( t) dt = 8kTγgG,. (3-29) The PSD of noise at the output is proportional to the bias current and inversely proportional to the zero crossing slope of LO signal. 62

63 Figure Time varying transconductance of the switching pair and the PSD of generated thermal noise [52] The third noise source is the LO port. Even though it is very complicated because the LO is a periodically time varying and the noise at the output contains cyclostationary components. Simplifying the LO port as the time invariant stationary voltage noise source, output noise is y ( t) G( t) n ( t) nlo = LO, (3-30) where G(t) is the time varying transconductance of the switching pair (M 2 and M 3 in Figure 3-35) and n LO (t) is noise at LO port. For a single balanced mixer, PSD of noise from LO port is S 0 nlo ( f ) = 4kTγ where G ( R + 2r ) 2 LO 1 = T LO g 2 T LO 0 G 2 G( t) 2. (3-31) dt R LO is the equivalent noise resistance at LO port. The external noise at LO port, however, is rejected in a double balanced Gilbert cell mixer. The PSD for this is 63

64 S 0 nlo ( f ) G 2 = 4kTγ (4rg 2 ). (3-32) Including the three noise sources and that generated by loads, single side band (SSB) noise factor (F) [52] is 2 ( γ + r g ) g α + 2γ G + ( R + 2r ) G + 1 g1 m1 m1 1 F α SB, SSB = 2 2 c c g 2 m1 R s LO g 2 1 R L (3-33) For a double balanced mixer, noise factor is 2 2 ( γ + r g ) g α + 4γ G + 4r G + MR1 g, MR1 m, MR1 m1, MR1 α FDB, SSB = c c g m1, MR1 R s 1 g, ML1 1 R L (3-34)[52] Figure Schematic of double balanced Gilbert cell mixer with source degeneration inductors 64

65 The schematic of double balanced Gilbert cell mixer with source degeneration inductors for the FDMA receiver is shown in Figure The basic architecture shown in Figure 3-36 is augmented to improve the performance. Like in the LNA, source degeneration inductors (L S1 and L S2 ) are added to improve linearity, L S3 is added to improve common mode rejection resonating the parasitic components at the common mode node. L D1 is added for noise rejection from the LO port by resonating the parasitic components at the drain nodes of M R1 and M R2. Even though the inductor loads are usually used for GHz IF, resistive loads are used to increase bandwidth. The simulation results of mixer are in Figures 3-40, 3-41 and Figure Voltage gain versus intermediate frequency (IF) as function of load resistance 65

66 Figure Voltage gain and power gain versus input power Figure Noise figure versus intermediate frequency (IF) as function of load resistance Voltage conversion gain is -4.5 db, 3-dB bandwidth is 4.5 GHz, and noise figure is 12.8 db at If of 1.5 GHz with -6 dbm Local Oscillator (LO) power. In Figure 3-41 power gain is greater than the voltage gain. The conversion voltage gain of mixers is 66

67 normally higher than power gain. This, however, depends on the input and load impedances. The relationship between power gain and voltage gain is P vout Re{ } Re{ } Pout Z L 2 Z L = = VGAIN P (3 35) in vin Re{ } Re{ } Z Z GAIN = in If the input and load impedance are the same, power gain is the same as voltage gain. If Re{1/Z L } is higher than Re{1/Z in }, then the power gain is higher than the voltage gain. Figure 3-43 shows a die photograph and layout of the mixer. in A Figure Die photograph and layout of broadband double balanced Gilbert cell mixer A) Die photograph B) Layout B 67

68 CHAPTER 4 INTERMEDIATE FREQUENCY TO BASEBAND CONVERSION 4.1 IF-to Baseband Conversion System The second down conversion stage that frequency translates from intermediate frequency (IF) to baseband (BB) is shown in Figure 4-1. The stage is composed of three parts. One is a broadband IF amplifier with over 3-GHz bandwidth. Another is seven mixers that convert IF signals to baseband signals with seven different intermediate frequencies. The other is an intermediate frequency generator using the 24 GHz signal from a phase locked loop (PLL). This can simultaneously generate seven different signals with frequencies at 0.4, 0.8, 1.2, 1.5, 2.0, 2.4, and 3.0 GHz. According to the original frequency plan, there were two other IF frequencies at 1.6 GHz instead of 1.5 GHz and 2.8 GHz instead of 3.0 GHz. These allocations are changed to simplify the structure of IF generator. This is allocated since there is a great deal of flexibility for frequency allocation in a self contained system enclosed by a conductive case. CH1 400 MHz IF IFAMP CH2 PLL 24GHz 800 MHz.... CH6 Frequency Generator 400MHz 800MHz. 3GHz 2.4 GHz CH7 3 GHz Figure 4-1. Block diagram for IF to baseband conversion 68

69 The bandwidth of received signal in the FDMA link is 3 GHz from 200 MHz to 3.2 GHz. This is an extremely wide IF range. Amplifiers with an inductive load are usually used several gigahertz. The bandwidth of those is too narrow to cover the 3-GHz range. For the FDMA receiver, an amplifier with resistive feedback is used at IF. It can cover a wider band and is simple. The down conversion mixer needs also broad bandwidth to cover whole the entire band. A double balanced mixer using a Gilbert cell and resistor load is used to decrease second harmonic effect and to increase the bandwidth. The seven mixers have the same structure and size. It is not easy to simultaneously generate the LO signals at multiple frequencies. Frequency synthesizers in a communication system with multiple channels like ultra wideband (UWB) system multiply or divide using mixers to generate LO signals at a wide range of frequencies. This requires more space and filters. Alternate way is to use only buffers and D Flipflops. This can be compact because it does not need any inductors and capacitors which occupy large space. Each block in IF to Baseband conversion and baseband circuit are explained in this chapter Intermediate Frequency Amplifier There are many reports for a wide band amplifier used in broad band systems like UWB [53] - [58]. A simple amplifier architecture for several-ghz systems is an inverter with resistive feedback [59], [60] between input and output. Schematic of the proposed two stage IF amplifier is shown in Figure 4-2. Both NMOS and PMOS transistors form the amplifier. The DC bias at input and output is set by a feedback resistor. A separate bias circuit is not needed. A capacitor is used for DC blocking between the amplification stages. The bandwidth of inverter with resistive feedback is determined by the RC time constants at the input and output nodes [60]. 69

70 Figure 4-2. Schematic of broadband IF amplifier with resistive feedback A schematic of single stage resistive feedback amplifier and its equivalent circuit are shown in Figure 4-3. Figure 4-3. Schematic of single stage of resistive feedback inverter and equivalent circuit A) Schematic of inverter amplifier with resistive feedback B) Equivalent circuit of the amplifier 70

71 The loop gain is defined as T 1 1 = gm ( Z1 + Z 2) //( // ron // rop ), (4-1) scds Z1 + Z 2 Z where g m = g mn + g mp; and g mn and g mp are the transconductances of NMOS and PMOS transistors. C ds = C dsn + C dsp ; where C dsn and C dsp are the drain-source capacitance of NMOS and PMOS transistors. Z 1 = 1/s(C gsn + C gsp ); C gsn and C gsp are the gate to source capacitance of NMOS and PMOS transistors. Z 2 = R f /(1+ R f s(c gdn + C gdp ); C gdn and C gdp are the gate-to-drain capacitance of NMOS and PMOS transistors. Open loop gain is A Z = Z 2 (4-2) and the closed loop gain is 1 T A 1+1/ T = (4-3) If Z 1 is greater than Z 2 and the gate-to-source capacitance and gate-to-drain capacitances are neglected, the transfer function of single stage inverter with resistive inverters is V V out in = ( sc ds g + r m 1 1 on + rop ). (4-4) If the source resistance is R S, the noise figure (NF) of the amplifier is [61] 71

72 NF R f 2 1+ ( + ) + ( ) g R 3 g R R R + m s s R s 2 s 2 m s (4-5) f f T 3 R f And the input impedance is Z in R f + Z 1 + A v L (4-6) Where Z sc // r // r L =. ds on op If the source resistance is small, the gain of resistive inverter becomes V out A v = gm ( Rs + R f Vin ) =. (4-7) In simulations, the two stage resistive feedback inverter has 18 db gain at 1.6 GHz, 3.3 db noise figure, and 3.3 GHz 3-dB bandwidth. The layout is shown in Figure 4-4 and its size is 220 µm by 250 µm. This is fabricated in the UMC 130nm CMOS technology. Figure 4-4. Layout of a differential IF amplifier with resistive feedback 72

73 4.1.2 IF to BB Down Conversion Mixer There are signals at seven different FDMA channels. They should operate at the same time. The total bandwidth of them is 3 GHz. To support the wide bandwidth from 200 MHz through 3.2 GHz at the input, a Gilbert cell mixer with resistive loads is used. To reduce the effect of even order harmonics, a double balanced structure is used. It is straight forward to use differential topology because the FDMA receiver is fully differential. IFA IF : 0.4, 0.8, 1.2, 1.5, 2.0, 2.4, 3.0GHz CH1 CH2 CH3 IF : GHz 0 CH4 CH5 CH6 CH GHz Figure 4-5. Frequency plan of IF to BB conversion The mixer in Figure 4-7 is a simple heterodyne down conversion mixer. To look at the frequency conversion scheme, input signal is define as RF input = A cosω t (4-8) RF RF 73

74 and if LO is set as LO = cos( ω RF t + θ ), then (4-9) baseband out is BB ouyput = ( A 1 = 2 RF cosω t)cos( ω t + θ ) [ A cosθ + [ A cos(2ω t + θ )]] RF RF RF RF RF (4-10) Filtering the high frequency term with a low pass filter, and amplifying the signal with gain of 2, the output is BB = cosθ. (4-11) ouyput A RF Figure 4-6. Zero IF down conversion scheme using simple homodyne architecture Another possible solution for this is to use Hartley architecture shown in Figure 4-7. It needs two mixers, two 90-degree phase rotators and a combiner to recover signal and to reject image. Equations from 4-11 to 4-13 show how RF signal is converted to baseband and recovered. 74

75 XA1(t) LPF XA2(t) RFin cosωrft π/2 cosωrft+θ Σ BBout LPF IF π/2 XB1(t) XB2(t) Figure 4-7. Zero IF down conversion scheme using Hartley architecture X X X X A1 A2 B1 B2 BB ( t) = A RF 1 = 2 1 ( t) = A 2 ( t) = A 1 = 2 1 ( t) = A 2 out cosω t cos( ω t + θ ) [ A cosθ + A cos(2ω t + θ )] RF RF RF RF cosθ RF RF RF cosω t sin( ω t + θ ) [ A sinθ + A sin(2ω t + θ )] RF RF RF cosθ cosθ RF ( t) = X A2 ( t) + X B2 ( t) = = A RF RF 1 2 A RF RF 1 cosθ + A 2 RF cosθ (4-11) (4-12) (4-13) We need seven mixers. The Hartley is more complicated and requires more area. A simpler architecture is preferred in multiple channel systems. The simpler one is selected for the FDMA receiver. There is, however, a problem in these architectures. If θ = 90º there is no signal in baseband because cos(90º) is zero. This well known nulling 75

76 problem for AM systems should be fixed to recover the signals at baseband. The simplest way is to use LO signals which have phase significantly away from 90 degrees. This can be accomplished by generation of two LO phases and selecting the one that results higher baseband output. There are a few ways to generate the phases [62]-[64]. A RC low pass filter or gm-c is usually used to generate the phases. Some use digital like delay cells with D flip-flops. This needs reference signal with 50% duty cycle and a specific divider ratio like 2, 4, 8, 16, etc. In the IF LO generator used in this research, it is challenging to make two signals with phase difference of the 90 degrees at every output frequencies especially without significantly increasing the chip area. Instead, The IF generator outputs two signals with phase differences between 60 and 90 degrees. How to generate the two signals will be discussed in next chapter. Another requirement is the duty cycle of IF LO signals. They must have 50% duty cycle. Such a signal has only DC and odd harmonics of the signal at fundamental frequency. Square wave with 50% duty cycle and a period (T 0 ) is shown in Figure 4-8., Figure 4-8. Square wave with 50% duty cycle Using the complex exponential Fourier series, a physical waveform can be represented over the interval a < t < a +T0 [65] 76

77 n = n = jnω0 W ( t) = c n e t (4 14) Where the complex Fourier coefficients c n is c n 1 T a+ T0 jnω0t = W ( t) e dt a (4 15) 0 and ω 0 = 2πf 0 = 2π/T 0. For the square wave in Figure 4-5, the complex Fourier coefficients are = 1 T0 / 2 jnω0 = A j ( e 2πn 1) t jnπ c n Ae dt T 0, (4 16) 0 where A is the amplitude of square wave. Using l Hospital s rule, c n A, 2 = j 0, A n, n = 0 n = odd π (4 17) n = even From equation 4-17, there is no even harmonics in the square wave. The complex Fourier coefficients can be represented using sync function in frequency domain as c n A e 2 jnπ 2 sin( nπ / 2) nπ / 2 = (4 18) The power spectrum density (PSD) of square wave with 50% duty cycle is shown in Figure

78 78 Figure 4-9. Power spectral density (PSD) of square wave with 50 % duty cycle If the duty cycle is not 50 %, however, the complex Fourier coefficients are changed and some of them are not zero when n is even. For example, when the duration of HIGH is T0/2 + t, the complex Fourier coefficients are 1) ( / 0 0 = = + π π ω π jn T t n j t jn t T n e e n A j dt Ae T c (4 19) Comparing equation 4-19 with 4-16, there is a new term with t. = + = + = + = even n e n A j odd n e n A j n T t A c T t n j T t n j n ), 1 ( 2 ), (1 2 0 ), 2 ( π π π π (4 20) When t = (1/8)T 0, C 0 = (5/8)A, C 1 = [(1- j)/2π]a, and C 2 = [(-1+ j)/4π]a. The second harmonic has a finite value. This causes a mixer to have an even order

79 harmonic problem and degrade the linearity of a mixer. So IF generator should make all the outputs to have 50% duty cycle. Some frequencies whose divider ratio at the end is 2 N when N is an integer, 50% duty cycle is obtained by the divider. For other outputs, duty correction circuits are required. An intermediate frequency generator composed of divider chains and duty correction circuits will be discussed in the next chapter. LO+ LO+ RF+ LO- RF- Figure Schematic of double balanced Gilbert cell mixer Figure 4-10 shows the schematic of a double balanced Gilbert cell mixer integrated in the FDMA receiver. The mixer has two load resistors. These are formed using poly resistors with a silicide block that has higher sheet resistance and lower temperature coefficient. In the double balanced structure, the mismatch of load and MOSFETs cause even harmonic problems that degrades linearity. To reduce the mismatch in the load several resistors are connected with parallel instead of one and 79

80 dummy resistors are added on both sides of resistors to decrease the variations. The layout is drawn to keep symmetry. Even though the FDMA receiver needs seven, only one is fabricated for the test purpose. In the test structure, each IF LO signal from IF generator is selected by a 3- bits decoder. The layout of a mixer fabricated in the UMC 130-nm CMOS technology is shown in Figure4-11. The size of mixer cell is 42 µm by 52 µm. Figure Layout of double balanced Gilbert cell mixer 4.2 Baseband Architecture There are three parts in the baseband section for each channel of the FDMA receiver as shown in Figure 4-12: a low pass filter, a baseband amplifier, and a comparator. Since there are seven channels in the FDMA receiver, seven baseband 80

81 links are needed. The architecture and specification of components in the baseband is the same for all channels. Figure Block diagram of baseband section of the FDAM receiver The first stage is a low pass filter (LPF). When the IF mixer frequency translates, one agian there are signals at f c -f IF and f c +f IF. The filter is used to reject the high frequency term and to select the low frequency one. The proposed LPF structure is shown in Figure The low pass filter is composed of a source follwer and an RC filter. Figure Schematic of the third order low pass filter The third order low pass filter has 270-MHz bandwidth and 3 db of loss in simulation. The layout of LPF integrated in the FDMA receiver is shown in Figure The layout size is 84 µm by 65 µm in the UMC 130 nm logic CMOS technology. 81

82 Figure Layout of the third order low pass filter Figure Schematic of 3-stage baseband amplifier. A baseband amplifier is composed of three stages of basic cells shown in Figure A basic cell is a differential amplifier with common mode feedback using a resistor (R 2 ). The output dc bias is set by R 2 and the gain of a basic cell is set by R 1 and R 2. 82

83 Gain of each stage is R 2 /R 1 and set to 5 db. The total voltage gain of amplifier is 15 db. The bandwidth is 250-MHz which is sufficient to cover the 150 MHz of signal bandwidth. The layout of baseband amplifier is shown in Figure 4-16 and its size is 150 µm by 32 µm. Figure Layout of the baseband amplifier Figure Schematic of comparator and SR latch 83

84 The last stage of receiver is a one-bit comparator composed of two single to differential amplifiers with wide bandwidth and an SR latch that is composed of two NOR gates to convert sinusoidal signal to square wave. The comparator determines the high and low levels of incoming signals. The schematic of amplifier and block diagram of comparators and SR latch are shown in Figure The layout is shown in Figure The comparator size is 47 µm by 74 µm. Figure Layout of comparator and SR latch 4.3 Measurement Results The measurement scheme, setup, chip, a Printed Circuit Board (PCB), and a bonding diagram for the mixer are shown in the Figure Looking at the measurement setup, the two inputs, IF and LO signals are injected from signal 84

85 generators using a GSSG probe and a Balun. The Input signal is a single tone which has 10 to 50 MHz higher frequency than the frequency of IF LO signal. The outputs of mixer are connected to an external operational amplifier (AD8138, Analog Device) with 6 db gain and a voltage divider to drive a spectrum analyzer with 50-Ω input impedance. Figure Measurement setup and test structure of the mixer and baseband amplifier integrated with an FDMA receiver A) Measurement setup B) Die photo of test structure C) Test PCB board D) Block diagram of test structure E) Zoomed in photo of bonding area Figure Input measurement scheme of IF to BB converter test structure 85

86 Figure Measurement setup and PCB board of IF to BB converter test structure Figure Measurement results of IF to baseband conversion stage A) Gain and frequency response of each channel at baseband B) Gain versus intermediate frequency The output of mixer and baseband amplifier are connected to an external operational amplifier (OPA) with high input impedance for converting differential signal to single ended for testing. In Figure 4-22, the two plots show the gain and frequency response of each channel versus baseband frequency (A) and gain of each channel 86

87 versus intermediate frequency (IF) (B) for the IF to baseband conversion stage. The IF amplifier and mixer have 10 MHz of bandwidth. This is currently limited by an external amplifier. The gain of the IF amplifier and mixer combination channels 1 to 7 have 23.6, 27.5, 27.6, 25.6, 23.3, 23.1, and 21.5 db. Figure Measurement results of LPF and baseband amplifier A) Frequency response at baseband B) Gain of the LPF and BB amplifier The measured characteristics of low pass filter (LPF) and baseband amplifier (BBA) are shown in Figure As mentioned, the baseband amplifier has 250 MHz bandwidth and 15 db of gain, and the low pass filter has 250-MHz bandwidth and 3-dB loss in simulation. In Figure 4-23, measured gain is 5 db, bandwidth is about 40 MHz and power consumption is 1.5 mw. The gain is degraded by 7.5 db in the measurements. Since the load resistance of baseband amplifier is 18kΩ while input resistance of external operational amplifier used for measurements is 5kΩ. This reduces gain to 1/3 of simulation or by 7 db. If this loss is de-embedded, gain of the low pass filter and a baseband amplifier combination is about 12 db. The bandwidth is still small. This appears to be caused from the parasitic capacitance of line and pad for connecting 87

88 the external load. To fix this problem, the external amplifier AD8138 was replaced with an AD 8131ed for the subsequent effort. 88

89 CHAPTER 5 SYNTHESES OF MULTIPLE INTERMEDIATE FREQUENCIES 5.1 Background of Frequency Generation As discussed, a key challenge is generating LO signals at multiple frequencies for channel selection. It is not practical to use multiple voltage controlled oscillators (VCO s) to synthesize because they occupy a large area and consume much power. Approaches to synthesize multiple frequencies for ultra wideband systems have been suggested [66]-[68]. These normally have complicated architecture and cannot simultaneously output signals at multiple frequencies. To make the system compact, the proposed multiple LO generator uses only transistors except for the 12 GHz and 24 GHz buffers. This frequency generator frequency divides the 24 GHz signal from s phase locked loop (PLL) and simultaneously generates seven frequencies using static frequency dividers [69] [70]. The generated frequencies and divide ratios for each channel are listed in Table 5-1. Table 5-1. Intermediate frequency and frequency divider ratio Signal Frequency Generation LO Ref 24 GHz LC-VCO + PLL IF GHz LO R /2/2/2.5/2/3 IF GHz LO R /2/2/2.5/3 IF GHz LO R /2/2/2.5/2 IF GHz LO R /2/2/2/3 IF GHz LO R /2/2/3 IF GHz LO R /2/2/2.5 IF GHz LO R /2/2/2 89

90 Potentially, a lot of dividers are needed. Simplification is required to decrease size, and power consumption. This can be achieved by sharing dividers. Such simplification is shown in Figure 5-1. Figure 5-1. Simplified frequency generation scheme Based on Table 5-1, potentially twenty six dividers are need. If dividers are shared, the number of dividers can be reduced to nine. In the original frequency plan, 2.8 GHz and 1.6 GHz are used for channel 3 and channel GHz is replaced with 3.0 GHz because generation of 2.8 GHz is not easy using only dividers. It requires a mixer and a filter as shown in Figure GHz is replaced with 1.5 GHz because generation of 1.6 GHz requires a divide-by-1.5 circuit. It is difficult to make the output to have 50 % duty cycle. To generate 1.5 GHz, the 3.0 GHz output needs to be simply frequency divided by two. 90

91 Figure 5-2. Generation of 2.8 GHz using a mixer and a high pass filter (HPF) 5.2 Frequency Generation and Duty Correction Looking at Table 5-1 and Figure 5-1, seven divide-by-2, a divide-by-3, a divideby-2.5 are needed to support the seven necessary output frequencies. The divide-by-2 circuit using a D flip-flop (DFF) is straight forward. There are two latches in the DFF forming the master and slave. The input of DFF is connected to the inverted output and the input signal is fed to the clock port (Figure 5-3 (A)). The schematic of current mode logic (CML) static divide-by-2 based on a D-type flip-flop (DFF) is shown in Figure 5-3 (B). It can operate over a wide frequency range (> 20 GHz) and has moderate power consumption comparing to the dynamic one [70]. 91

92 A B Figure 5-3. Schematic of current mode logic (CML) static divide-by-2 based on a D flipflop [70] A) Block diagram of divide-by-2 circuit. B) Schematic The second divider is the divide-by-2.5 circuit. Its divide ratio is fractional. In the case that a divide ratio is x.5, where x is an integer, the divider architecture is similar to the one with divide ratio of 2x+1. The only difference is the use of dual edge triggered flip-flops for a fractional divider instead of using single edge (either rising or falling edge) triggered flip flops. A divide-by-2.5 circuit was implemented with three dual edge triggered flip flops and a NAND gate as shown in Figure 5-4. A duty correction circuit to change the duty ratio to 1:1, however, is required to reduce the even order harmonic output. Without it, the duty ratio of outputs is 3:2 or 2:3. 92

93 OUT(3:2) D1 D Q Q1 D Q2 Q D Q Q3 Q Q Q CLK CLK D1 Q1 Q2 Q3 Figure 5-4. Block diagram and waveforms of a divide-by-2.5 1/2.4GHz (416.7ps) 1/24GHz (41.7ps) 12 GHz 6 GHz (/2) 2.4 GHz (Q1) 2.4 GHz (Q1_d) OUT 3 : 2 1 : GHz D Q Q1 D Q Q1_d Q Q OUT 12 GHz 12 GHz Figure 5-5. Duty cycle correction scheme for the divide-by-2.5 and waveform to generate 2.4 GHz output 93

94 The duty correction circuit for the 2.4 GHz output is composed of two dual edge triggered flip-flops (DEDFFs) and an AND gate. Q1 and Q1_d delayed by 41.7-ps which is a half period of 12-GHz through a DEDFF in Figure 5-5. The product of two 2.4 GHz waveforms can make output with a 1:1 duty cycle using an AND gate. D Q D Q OUT Q Q CLK 1:1 Input Duty Ratio IN OUT 1 : 2 3:2 Input Duty Ratio IN OUT 3(37.5%) : 5(62.5%) 2(28.6%) : 5(71.4%) Figure 5-6. Block diagram and waveforms of a divide-by-1.5 circuit A divide-by-1.5, which is another fractional divider, is made of two dual edge triggered D flip flops and a NOR gate shown in Figure 5-6. This has a duty cycle problem like the divide-by-2.5 circuit. The duty cycle ratio of output is 1:2 when the input duty cycle ratio is 1:1. The output duty cycle is 3:5 and 2:5 when the input duty cycle is 3:2. The duty correction circuit uses the 1:1 input duty cycle case. The duty correction circuit for the 1.6 GHz LO signal is shown in Figure 5-7. The Q1_d which is a delayed 94

95 signal of Q1 by a quarter of an input clock signal period ( ps) is needed. None of the outputs of dividers have such phase. The delay is generated using a combination of analog delayers. Because of this, the circuit is susceptible to variations. Figure 5-7. Duty correction scheme for the divide-by-1.5 and waveforms A divide-by-3 circuit using D flip-flops generally provides output with 3:2 or 2:3 duty cycle ratio. For 800-MHz and 2.0 GHz LO signal generation, a divide-by-3 and duty correction circuits are need. An approach to implement these is shown in Figure 5-8. This circuit is composed of two D flip-flops (DFF), one latch, one AND gate, and a multiplexer. Two DFFs (FF0 and FF1) and an AND gate (G0) are for divide-by-3 in the upper side and a latch and a multiplexer in the lower part are for duty correction. Looking at waveforms Q1 and Q2 which are delayed by a half cycle of reference clock (CK) using a latch (LT0) either, generates the CLK3 with a 1:1 duty cycle ratio in conjunction with a multiplexer that chooses either in Q1 and Q2. 95

96 Figure 5-8. Block diagram and waveforms of a divide-by-3 [71] Another solution uses three dual edge triggered flip-flops (DEFFs) as shown in Figure 5-9. It does not need any additional components for duty correction. Even though a DEFF is bigger than a single edge triggered flip-flop, it has the advantage to provide a 1:1 duty cycle ratio. Because it uses both rising and falling edges, it can divide with a fractional ratio with only three DEFFs. For 0.4, 1.2, 1.5, and 3.0 GHz outputs, they do 96

97 not need duty correction circuit because the last divide stage that generates the signals has a divide ratio of 2, which makes the output duty cycle ratio 1:1. CLK Q1 Q2 Q3 OUT D Q D Q D Q Q Q Q CLK Q1 Q2 Q3 OUT Figure 5-9. Block diagram and waveforms of a divide-by-3 circuit using three dual edge triggered flip-flops (DEDFFs) 5.3 Phase Generation The other requirement of LO generation is providing two output phases with an offset larger than 60. The phases which IF generator supports are listed in Table 5-2. As mentioned in the previous chapter, 90-degree phase offset is desired, but in some case, it is not straightforward to generate them. This depends on the duty cycle of input and divide ratio. If the input duty cycle is 50% for divide-by-2 circuit, there is no problem generating signals with the 90 degree phase offset. For the other cases when the divide ratio is 2.5 or 3, this is not straightforward. 97

98 Table 5-2. Phases difference generated by IF generator according to frequencies Signal phase 3.0G G G G G G G 90 T 4 3T 4 CLK Q1 Q2 Figure Waveforms of a divide- by-2 circuit Starting with divide-by-2 circuit, both Q1 and Q2 in Figure 5-10 are the frequency divide-by-2 waveforms of input (CLK). Q1 is divided at the rising edge, while Q2 is done at the falling edge. The time difference is T/4 which is 90 degrees in phase. One of them is selected by a multiplexer. For the second case, 2.4-GHz output generates two signals with zero and 72 degree phase. In Figure 5-4, there are three dual edged triggered flip-flops (DEDFFs) in the divide-by-2.5 output. They delay each output of the previous stage by a half of period of input. For example, Q2 is delayed signal of Q1 by a DEDFF in Figure

99 The delay time is 1/5 period of output with frequency that is two and half divide by the frequency, which corresponds to 72 degrees. T 5 4T 5 CLK D1 Q1 Q2 Q3 Figure Waveforms of a divide-by-2.5 T 6 5T 6 CLK Q1 Q2 Q3 OUT Figure Waveforms of a divide-by-3 The last case for 800 MHz and 3.0 GHz which use divide-by-3 circuit is shown in Figure Q2, Q3 and OUT in Figure 5-12 are the outputs of three DEDFFs. Comparing Q3 with OUT, the latter is delayed by a half period of input (CLK). It is 1/6 period of output, or the phase difference between Q3 and OUT is 60 degrees. 99

100 5.4 Measurement of Test Structure The test structure for IF generator is fabricated in the UMC130nm CMOS technology. It generates seven frequencies (0.4, 0.8, 1.2, 1.5, 2.0, 2.4, and 3.0 GHz) using 12 GHz input. The test structure also includes an output buffer and a multiplexer to select the output channel for IF generation circuit and another output buffer and 100 MHz generation circuit including divide-by-60 circuits for trigger an oscilloscope for Phase offset measurements. The function for frequency selection and phase selection scheme is summarized in Table 5-3. Table 5-3. Frequency and phase selection Channel FS2 FS1 FS0 HL 0.4GHz /1 (90 ) 0.8GHz /1 (60 ) 1.2GHz /1 (90 ) 1.5GHz /1 (90 ) 2.0GHz /1 (60 ) 2.4GHz /1 (72 ) 3.0GHz /1 (90 ) The layout size of test structure for IF generation is 783 by 720 µm 2. The layout, die photo, printed circuit board (PCB) and measurement setup are shown in Figures 5-13 through The input at 12 GHz from a signal generator and the output frequency was measured with a spectrum analyzer. The duty cycle was measured with an oscilloscope. The phase offset between two selectable signals of each channel was measured using 100MHz triggering signal. 100

101 A B Figure Measurement scheme and Die photograph of IF generator A) Measurement scheme and layout B) Die photograph 101

102 Figure Printed Circuit Board (PCB) of IF generator testing Figure Measurement setup for IF generator testing Signals with seven different frequencies from 400 MHz to 3 GHz were generated by the IF LO generation circuit. One of them can be chosen using a 3-bit selector in the test structure. The measured output spectra of each channel are shown in Figure

103 A B C Figure Output spectra of IF generator A) 400 MHz B) 800 MHz C) 1.2 GHz D) 1.5 GHz E) 2.0 GHz F) 2.4 GHz G) 3.0 GHz D 103

104 E F G Figure Continued 104

105 A B C D E F Figure Measured duty cycle ratio of output waveforms of IF generator in the Oscilloscope Agilent infiniium 86100B A) 400 MHz single ended B) 400 MHz differential. C) 800 MHz single ended D) 800 MHz differential E) 1.2 GHz single ended F) 1.2 GHz differential G) 1.5 GHz single ended H) 1.5 GHz differential I) 2.0 GHz single ended J) 2.0 GHz differential K) 2.4 GHz single ended L) 2.4 GHz differential M) 3.0 GHz single ended N) 3.0 GHz differential 105

106 G H I J K L M N Figure Continued 106

107 The duty cycle and phase offset between two selectable signals of each channel are measured using an oscilloscope (Agilent infiniium DCA 86100B). The output waveforms are shown in Figure The duty cycle of the each channel is 49.4 % (400MHz), 48.5 % (800MHz), 46.4 % (1.2GHz ), 54.4 % (1.5GHz), 53.9 %(2.0GHz), 54.9 % (2.4GHz), 48.2 % ( 3.0 GHz) for single ended measurements and 49.5 % (400MHz), 49.6 % (800MHz), 49.2 % (1.2 GHz), 50.1 % (1.5GHz), 49.3 %(2.0GHz), 50.2 % (2.4GHz), 50.4 % (3.0 GHz) for differential measurements. The deviation is less than ±5 % in the single ended case, while that is less than 0.5 % for differential case. A B Figure Measured output waveforms of 400 MHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH A 100-MHz signal was used as a trigger signal and as the reference to measure phase offset between two selectable signals of each channel. The 400 MHz waveform in Figure 5-18 (A) lags the triggering signal by 835 ps when the selector signal for phase, HL_SEL is LOW, when HL_SEL is HIGH, the waveform in Figure 5-18 (B) lags triggering signal by ns. The time difference of two 400MHz signals in Figures 5-18 (A) and (B) is 630 ps, which is 25.2 % of a period of 400 MHz which is 2500 ps. The corresponding phase offset of 400MHz output is 90.7 more slightly. 107

108 630 ps offset = 360 = ps Phase (5 1) Using the same way the phase offsets of other channel can be calculated from waveforms. The phase offset of 800 MHz output is 59.9 from Equation 5-2 and Figure ( ) ps offset = 360 = ps Phase (5 2) A B Figure Measured output waveforms of 800 MHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH The phase offset of 1.2 GHz output is 93.3 from Equation 5-3 and Figure ( ) ps offset = 360 = ps Phase (5 3) A B Figure Measured output waveforms of 1.2 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH. 108

109 The phase offset of 1.5 GHz output is 90.7 from Equation 5-4 and Figure ( ) ps offset = 360 = ps Phase (5 4) A B Figure Measured output waveforms of 1.5 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH The phase offset of 2.0 GHz output is 64.8 from Equation 5-5 and Figure ( ) ps offset = 360 = ps Phase (5 5) A B Figure Measured output waveforms of 2.0 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH The phase offset of 2.4 GHz output is 72.6 from Equation 5-6 and Figure

110 (157 73) ps offset = 360 = ps Phase (5 6) A B Figure Measured output waveforms of 2.4 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH The phase offset of 3.0 GHz output is 83.2 from Equation 5-7 and Figure ( ) ps offset = 360 = ps Phase (5 7) A B Figure Measured output waveforms of 3.0 GHz and 100 MHz trigger signal A) HL_SEL = LOW B) HL_SEL = HIGH The measured phase offset are close to the target for the output except the ones at 2 and 3 GHz whose error is about 8 %. 110

111 A B C D E F G H Figure Measured Phase Noise of each channel and input reference signal A) 400 MHz B) 800 MHz C) 1.2 GHz D) 1.5 GHz E) 2.0 GHz F) 2.4 GHz G) 3.0 GHz H) 12 GHz input reference 111

112 The phase noise of outputs was measured using Agilent E4448A Spectrum Analyzer. The phase noise 12 GHz input is dbc/hz of at 1MHz offset. The measurement results are shown in Figure 5-25 and summarized in Table 5-4. The power consumption of IF generation block is 90 mw, but including the power consumption of a 24-GHz buffer from the PLL, the total is 106 mw. Summary Table 5-4. Summary of IF generator measurement Channel Duty cycle ratio (%) Single Ended Differential Phase Offset (Target) Phase 1MHz (dbc/hz) 0.4 GHz (90 ) GHz (60 ) GHz (90 ) GHz (90 ) GHz (60 ) GHz (72 ) GHz (90 ) In this chapter, an intermediate frequency LO generator circuit that simultaneously generates multiple signals with different frequencies is proposed and the measurement results are presented. The circuit generates seven outputs at frequencies; 0.4, 0.8, 1.2, 1.5, 2.0, 2.4, and 3.0 GHz. Each output has two selectable phases. The output frequencies were checked from 0.4 to 3 GHz with an oscilloscope and a spectrum 112

113 analyzer. The output duty cycle variation is less than ± 5% in single ended measurements and ± 1% in differential measurements. The phase offset of two selectable signal of each channel was measured using a 100-MHz triggering signal. The deviation of offset for target is less than 8 %. Phase Noise of each channel was measured with a 12-GHz input signal. 113

114 CHAPTER 6 FDMA RECEIVER CHARACTERIZATION 6.1 Test Structure The full architecture of FDMA receiver in the controller section of the hybrid engine controller board was shown in Figure 2-2. There are seven mixers and seven baseband chains for the seven channels. This increases the chip size. The fabricated test structure of receiver is shown in Figure 6-1. Figure 6-1. Test structure of FDMA receiver Only one baseband chain is included. It is a simpler way to test a channel even though it is not possible to support multiple channels at one time. To select an appropriate channel during the IF to baseband conversion, an 8-to-1 multiplexer is used to select the necessary Local Oscillator (LO) signal. Another buffer is added to drive the mixer. As described in chapter 5, the IF generator synthesizes signals at seven different frequencies (0.4, 0.8, 1.2, 1.5, 2.0, 2.4, and 3.0GHz) with two selectable phases. Only one IF to baseband conversion and a baseband chain composed of an IF amplifier, a 114

115 mixer, a LPF, a baseband amplifier, and a comparator are taped out as part do the FDMA receiver test structure. The test scheme and measurement setup are illustrated in Figure 6-2. The output of mixer and baseband amplifier are connected to an external operational amplifier (OPA) with high input impedance for converting differential signal to single ended one for measurements. A Figure 6-2. Test scheme and measurement setup of FDMA receiver A) Test scheme and PCB B) Measurement setup (C) Chip (D) PCB (E) Power and spectrum analyzer setup 115

116 Figure 6-3. Die photo of transceiver at Deadtime controller 116

117 6.2.1 RF Front-End Measurements 6.2 Measurements of FDMA Receiver Chain 50Ω FDMA Receiver RF input Balun Duplexer LNA BPF RFA Signal Generator Spectrum Analyzer RF output Balun 50Ω Figure 6-4. Measurement scheme for RF Front-End of FDMA receiver The blockdiagram shown in Figure 6-4 is the measurement setup for the first three components: Low Noise amplifier (LNA), Band Pass Filter (BPF) and RF amplifier (RFA). There is separated test structure for this. Instead, this is measured in the receiver chain. The RF amplifier is connected to a Pad and the RF-to IF down conversion mixer. This means measurement results are different from them in the receiver chain. In simulation, the power gain is degraded by 3 db when the output of RF amplifier is connected to a 50 Ω load. The loss of cable, probe and Duplexer should be considered to estimate the gain of RF-front-end of FDMA receiver. The measurement results of Duplexer which was measured by Hsinta Wu [72] are shown in Figure 6-5. Based on them, the gain is calculated and the plot is shown in Figure 6-6.The maximum gain is 22 db at 30 GHz. While the passband of FDMA receiver is 24.2 through 27.2 GHz. The expected frequency down tuning is not observed. The lowest frequency band of seven channels 117

118 in FDMA receiver has about -20 db of gain and the highest one of them has 5 db of gain. Figure 6-5. Measurement results of Duplexer for Antenna and FDMA receiver ports [72] Figure 6-6. Gain of RF-Front-End of FDMA receiver 118

119 6.2.2 RF-to-Baseband Converter measurements IFGEN FDMA Receiver Signal Generator MHz PLL MUX GHz 50Ω 24 GHz BUF RF input Balun LNA BPF RFA IFA LPF BBA Comparator BUF Signal Generator AD KΩ AD KΩ Ω 750Ω AMP 50Ω Spectrum Analyzer Ω 750Ω AMP 50Ω Spectrum Analyzer 1.5KΩ 1.5KΩ Figure 6-7. Measurement setup of IF to BB Down conversion The measurement setup for IF-to-Baseband down converter is shown in Figure 6-7. The outputs of IF-to-BB mixer and baseband amplifier can be measured in this setup. To transfer RF signal to baseband, a phase locked loop (PLL) provides the 24 GHz LO signal to RF-to-IF down conversion Mixer and IF generation circuit which synthesizes seven LO signals from 400 MHz to 3 GHz for IF-to BB Mixer. Even though the IF generator can simultaneously synthesize seven different LO frequencies, as discussed only one of them is used to convert IF signal to baseband to select one channel. The frequency of RF signals for each channel is 10 MHz higher than the center frequency of each channel. This means that the RF signal of every channels converted down to 10 MHz at the baseband. The outputs of IF-to-BB Mixer and baseband amplifier (BBA) for seven channels when the RF input power is -50 dbm are shown in Figure 6-8. To increase the bandwidth of external operational amplifier, AD 8131, is 119

120 replaced with AD8138. The input Impedance of AD8131 is too small comparing to the output impedance of IF-to-BB mixer and baseband amplifier. In simulations, the gain of IF-to-BB Mixer decrease by 12 db and one for BBA drops by 27 db. The gain plot of LNA to baseband amplifier after deembeding the effect of external operational amplifiers is shown in Figure 6-7. The highest gain of 40 db from LNA to Baseband amplifier is observed at RF input frequency of 30 GHz. The lowest one of 13 db is measured at RF frequency of 24.4 GHz. Mistuning the RF-front-end causes the gains to vary with channel. A B C D Figure 6-8. Measured output power of IF-to-BB Mixer and Baseband amplifier (BBA) with -50 dbm RF input power for each channels A) Mixer output with GHz input B) BBA output with GHz input C) Mixer output with GHz input D) BBA output with GHz input E) Mixer output with GHz input F) BBA output with GHz input G) Mixer output with GHz input H) BBA output with GHz input I) Mixer output with GHz input J) BBA output with GHz input K) Mixer output with GHz input L) BBA output with GHz input M) Mixer output with GHz input N) BBA output with GHz input 120

121 E F G H I J K L Figure 6-8. Continued M N 121

122 Figure 6-9. Gain of LNA to Baseband amplifier of FDMA receiver BERT 50 Mbps Data Signal Generator 4 GHz Signal Generator Signal Generator 23 GHz MHz IFGEN FDMA Receiver GHz 50Ω RF input 24 GHz PLL MUX BUF Balun LNA BPF RFA IFA LPF BBA Comparator BUF AD KΩ Ω 750Ω AMP 50Ω AMP Oscilloscope Oscilloscope 1.5KΩ Figure Measurement setup for ASK modulated data of FDMA receiver 122

123 Agilent N4906A Serial Bit Error Tester (BERT) is used to generate PRBS or specific data patterns for ASK modulation. Data from BERT is used to modulate a 4- GHz carrier. The modulated signal was upconverted to 27 GHz using an external mixer and a 23-GHz signal source. The spectrum of modulated signal with PRBS data at 27 GHz is shown in Figure As explained a previous chapter, one of seven frequencies synthesized by IF generator can be chosen using an 8-to-1 multiplexer. The LO signal at 3 GHz is selected for the data at 27 GHz. The modulated RF input signal is down-converted to baseband and output waveforms are checked using a oscilloscope( Agilent 54831D). Another external amplifier is used in this measurement setup because the output of mixer needed amplification for use with oscilloscope. Figure Spectrum of ASK modulated PRBS data 123

124 A B Figure Output waveforms of IF-to BB Mixer and ones of Inverted input data with 50 Mbps data rate A) Pattern B) PRBS data The output waveforms of IF-to-BB Mixer are show in Figure Comparing to the inverted input data pattern, the output data patterns are the same as the input in specific and PRBS patterns. Finally the output of FDMA receiver is converted to Digital signal by a comparator and an SR latch. Inverter buffers drive load. The output waveforms of FDMA receiver converted to digital data are shown in Figure The waveforms are compared with inverted input data pattern, and they are the same. A B Figure Output waveforms of FDMA receiver and ones of Inverted input data with 50 Mbps data rate A) B)

125 Figure Noise Figure measurement result of FDMA receiver Figure Linearity measurement result of FDMA receiver A) IP 1dB B) IIP 3 A 125

126 Figure Continued B Noise Figure and Linearity measurement results are shown in Figures 6-14 and Noise Figure of 27 GHz channel is 8.7 db. For RF frequency below ~ 26 GHz, the noise figure exceeds 10 db. ) IP 1dB 29 dbm and IIP 3 is -20dBm with 27.01and GHz. The total power consumption of FDMA receiver is mw including that for the PLL. FDMA test structure works for a single channel even though the total gain of each channel is not sufficient comparing to the target due to the frequency mistuning in the RF-front-end. Redesign of RF-front-end Is needed for proper operation. 6.2 Time Shared FDMA Receiver The FDMA receiver needs seven IF-to-Baseband conversion stages to support seven channels. This will significantly increase the chip area. To make the receiver compact, alternate architecture is proposed. More specifically, the time shared FDMA receiver shown in Figure 6-16 is proposed. 126

127 Figure Block diagram of time shared FDMA receiver architecture A time shared FDMA receiver architecture which requires a single IF to baseband converter and a baseband chain is shown To the FDMA receiver test structure in Figure 6-1, two more blocks are added as shown Figure One is a 3-bit counter to provide selector signals to the 8-to-1 multiplexer and the other is a Parallelizer which converts the incoming serial data to parallel data. Figure Channel selection scheme of time shared FDMA receiver 127

128 An 8-to-1 multiplexer (MUX) selects an LO signal with required intermediate frequency, and provides it to the mixer according to the selector signal from the counter. Since the counter provides periodic 3 bit selector signal to the 8-to-I MUX, each channel is converted at t1 to t7 slots in a period as shown in Figure The baseband signal is converted to parallel data using a 1-to-7 serial to parallel converter shown in Figure Since the data of seven channels are allocated in series, parallelized data at each are that for each channel. To enable to this, the mixer and baseband section should have sufficient time to settle to support the input data rate (50Mbps). Another test board shown in Figure 6-19 including the counter and 1-to 7 serial to parallel converter in Figure 6-18 is built. This is used in conjunction with PCB board shown in Figure 6-2. Data DFF DFF CH1 DFF DFF CH2 DFF DFF CH3 3-bit Counter CLK1X DFF DFF CH4 CLK7X DFF Signal Gnenerator DFF DFF CH5 DFF CH6 DFF DFF CH7 Figure Block diagram of 1-to-7 serial to parallel converter 128

129 FDMARX Data Parallelizer 3-bit Selector CLK1X 3-bit Counter CLK7X Signal Gnenerator FDMARX test PCB Serializer Figure Test plan with two PCB board for the time shared FDMA receiver Signal Generator f LO1 Data1 Power Combiner Signal Generator f LO2 Data2 Digital Pattern Generator 3-bit Selector Signal Generator 24 GHz Signal Generator f LO3 Data3 Signal Generator MHz IFGEN FDMA Receiver GHz 50Ω RF input 24 GHz PLL MUX BUF Balun LNA BPF RFA IFA LPF BBA Comparator BUF AD KΩ Ω 750Ω AMP 50Ω AMP Oscilloscope Oscilloscope 1.5KΩ Figure Test structure of time shared FDMA receiver for three channels 129

130 The test scheme of time shared FDMA receiver for three channels is shown in Figure It is a little different from the initially proposed measurement setup in which a 3-bit counter is used to produce 3-bit selector signals for a 8-to-1 multiplexer (MUX). A digital pattern generator replaced with 3-bit counter for selector and the serialized data can be checked in an oscilloscope. For this setup, however, five signal generators are needed. Due to the number of available signal generators, the measurements have been done for only two channels. A BERT which has two data port, DATA and DATAB, was used for data pattern generation instead of a digital pattern generator and one bit selector signal was used. Figure Waveforms of test structure of time shared FDMA receiver for two channels To check the waveform easily in an oscilloscope, simple data patterns shown in Figure 6-21 are used. From a pair of input data pattern, CH1 and CH2, one of them is chosen alternatively by SEL signal. The data rate of selector is twice as fast as one of data. When SEL is LOW the data from Channel 1 is selected, while the data from Channel 2 is chosen when SEL is HIGH. For measurements, a pair of 26 GHz and 27 GHz channels and a pair of 25.5 GHz and 26 GHz channels were selected. 130

131 A B Figure Output and selector waveforms of test structure of time shared FDMA receiver for two channels A) IF-to BB Mixer output B) Buffer output Data rate of input pattern for Channel 1 and Channel 2 is 10 Mbps and the selector signal rate is 20 Mbps. The output waveforms of IF-to-BB mixer and buffer measured using an oscilloscope are shown in Figure Comparing to the waveforms in Figure 6-21, the measured output pattern is the same as expected, illustrating that the time shared FDMA receiver properly works. This architecture, however, can work up to 10 MHz selection rate currently instead of 350 MHz selection rate needed for the system. The time shared FDMA receiver should be measured using seven channels. 131