Mixed Signal LSI. Practical design method of CMOS analog circuits. Kanazawa University Microelectronics Research Lab.

Transcription

1 Mixed Signal LSI Practical design method of CMOS analog circuits Kanazawa University Microelectronics Research Lab. Akio Kitagawa

2 0. Introduction 2

3 Growing information technology toward a real world and an daily life Keywords: Wireless, Energy Harvesting, Sensor integration. An analog mixed signal (AMS) LSI is fundamental to advanced electronic systems. Regional Information Disaster prevention Maintenance of infrastructure Cultivation Conventional cyberspace Intelligent transport systems Distribution system Nursing-care Environment conservation Home safety and automation Health care The Internet of Everything Medical services 3

4 Stages of mixed signal circuit design Function 1 Analog Transfer function Verilog-A Digital Block diagram Verilog-D Circuit Analog circuit (Amplifier and RLC) Logic circuit (Logic gate) Circuit Element 2 Analog circuit (Transistor circuit) Digital circuit (Transistor circuit) The hierarchical learning makes easy to understand the analog circuit design. Let us learn 1 first, then learn 2. 4

5 Books of reference For students who wants to learn the practical CMOS analog circuit design Note 1 R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation, 3rd Edition, ISBN , Wiley-IEEE Press (2010) R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, 2nd Edition, ISBN , Wiley-IEEE Press (2009) Course wares Note 1: These books does not cover the RF (Radio-frequency circuits). Book of reference on RF circuits: - RF Microelectronics, B. Razavi, ISBN , Prentice Hall (1998) - High-linearity CMOS RF Front-end Circuits, Yongwang Ding, ISBN , Springer (2004) 5

6 Requirement to mixed-signal circuit designer Broad knowledge and much experience are required. There are many circuit parameters with trade-off relations each other. All optimization procedure must be solved under the constraint peculiar to the application assumed. The constraint of the circuit design depends on the architecture of whole system. An mixed-signal circuit designer must learn a digital circuit design before an analog circuit, a system architecture and a systematic design methodology too. 6

7 History of analog mixed signal LSI development Bipolaar PMOS NMOS CMOS(Analog Mixed Signal) 741 OPA (1996) SPICE (1973) Bipolar OPA Analog Functions Bipolar ICs MOS Analog SCF MODEM Over Sampling ISDN MODEM Mobile Phone Base band Read Ch. LSI CMOS RF Micro electro mechanical systems, Bio-sensor, Energy harvesting Millimeter-wave CMOS technology permitted the development of the analog/digital integrated systems

8 Example of single chip UHF transceiver (RF signal generation) PLL DSM (Frequency control) (Impedance matching) LNA Mixer (Frequency conversion) Amp., ADC (Analog-to- Digital conversion) Regulator (Power supply) Other functions in Logic Image rejection Decimator Channel filter Demodulator 8

9 Analog/Digital functions in the transceiver LSI Name of circuit block Function Analog/Digital Remarks AAF (Anti-Aliasing Filter) Band-limitation Analog feasible only in analog SF (Smoothing Filter) from Discrete time to Continuous time Analog feasible only in analog LNA (Low Noise Amp.) Impedance matching Analog feasible only in analog Mixer Down-conversion, Up-conversion Analog for RF signal Power supply circuits (e.g. Regulator, Reference Voltage) ADC (Analog-to-Digital Converter) DAC (Digital-to-Analog Converter) Voltage regulation, DC-DC conversion, Voltage/Current reference Analog-to-Digital conversion Digital-to-Analog conversion Digital Analog Analog + Digital Analog + Digital PLL (Phase Locked Loop) RF Frequency Synthesize Analog or Digital DSM (Delta-Sigma Modulator) Frequency control of PLL Digital Memory(Sens-Amplifier, Memory Cell, DLL) Read out from memory cell Processor(DSP, MCU) Software signal processing, system control Digital Analog + Digital for IF signal Filter Hardware signal processing Analog for RF signal Digital for baseband 9

10 Strategy of analog/digital partitioning Digital implementation The digital implementation is given priority over the analog implementation, if the function can be implemented with a digital circuit. The digital circuit can make use of a merit of the scaling. The specification of digital circuit can be changed easily. Analog implementation There are some functions which can not be implemented in the digital circuit. High frequency High sensitivity Continuous time processing Ultra low power Sensor integration System performance is influenced by the insertion point of the analogto-digital converter (ADC) and digital-to-analog converter (DAC). The accuracy of analog circuits can enhanced by digital compensation technique. 10

11 Wave forms in mixed signal circuits Continuous time Discrete time Continuous value Continuous time analog circuit Discrete time analog circuit Discrete value Time domain analog circuit (Pulse width, Delay time) Binary b 3 b 2 b 1 b 0 DSM Digital circuit DSM: Delta-Sigma Modulation 11

12 Overview of analog design flow Block diagram of system architecture Specification sheet for analog block PHS RFU GPS RFU ETC RFU PHS IFU User Mode IFU GPS IFU ETC IFU DAC ADC ADC Wave Form GEN Quad Damed CLK GEN GPS Correrator DBP I/F DSP I/F GPS I/F PHS I/F 項目 条件 規格値設計値単位 Min. Typ. Max. Min. Typ. Max. 電源電圧 V 消費電流 2.2 ma 利得 15 db 周波数 雑音指数 (NF) 2 db 1dBコンフ レッションレヘ ル 0 dbm インタセフ トホ イント (IIP3) 9.6 db 入力インヒ ータ ンス 50 Ω 出力インヒ ータ ンス 500 Ω 端子間アイソレーション (OUT IN) 20 db ETC Demed ETC I/F Circuit scjematic with behavior models Transfer function or Signal flow Circuit schematic with Transistors Layout artwork Marge to digital blocks vdd M14 5/2 M15 5/2 M8 5/2 M5 5/2 Vbias M6 5/2 M9 5/2 3.5kΩ Vout- 0.5pF M3 M / /2 0.5pF Vin+ M1 M2 Vin- Vout+ 8.56/2 8.56/2 M16 8/2 M10 8/2 M7 8/2 M11 8/2 Vcm M17 5/2 M18 5/2 gnd M12 5/2 M13 5/2 12

13 Choice of Process technology CMOS (MOSFET) Current driving ability is rather low. High speed (SOI-CMOS is better for very high speed circuits) In the case of integration with large scale digital circuits, there is not the choice else. Bipolar Current driving ability is high (good characteristic for power amplifiers) SiGe HBT (Hetero Bipolar Transistor) can perform in high frequency. HEMT (High Electron Mobility Transistor) Very low noise (good characteristic for low noise amplifiers) Very high speed 13

14 Application Spectrum prediction at 2011 Transistors LNA: Si CMOS~ SiGe NPN~ InP HEMT PA: Si CMOS < SiGe NPN~ GaN HEMT Submillimeter wave InP HEMT/HBT 800MHz 2GHz 5GHz 10GHz 28GHz 77GHz RF-Mixed Signal LSI (SiP or SoC) Millimeter-wave GSM CDMA ISM( 海外 ) DTTV PDC GPS SAT Radio DCS PCS DECT CDMA WLAN b/g/n HomeRF Bluetooth SAT TV WLAN a/n SAT TV WLAN UWB LMDS (Local Multipoint Distribution Service) WLAN AUTO RADER LNA: Low Noise Amplifier PA: Power amplifier 2005 ITRS, and 2011 ITRS Wireless Ch.7 14

15 Structure of MOSFET and Bipolar Tr. MOSFET Bipolar Tr. source gate drain base emitter collector contact L W eff t OX SiO 2 n-si n-si p-si n-si substrate p-si n-si W B L eff W E : Emitter Width Transition frequency f T depends on L eff. Transition frequency f T depends on W B. NOTE: The peak transition frequency of bipolar transistor also depends on the base width W B and the base resistance (small W E is better). 15

16 Peak Transition frequency (GHz) Trends of operating frequency range 350nm Cellular 250nm High Speed Bipolar 130nm 90nm 65nm CDMA 180nm WLAN a CMOS 45nm Bipolar 32nm 22nm CMOS Amp., Mixer (20dB) CMOS ADC, Small Digital 16nm 11nm Peak Transition Frequency: The frequency for the current gain h 21 = 1 (0dB) of the transistor Year ITRS

17 Performance of ADC architecture 10G Technology front is limited by GBP of amplifier, switching speed of CMOSswitch, and process variation of capacitance. Sampling Frequency (Hz) 1G 100M 10M 1M 100k 10k 1k HDD Digital IF Flash ADC DVD Digital TV VDSL Digital Camera LAN ADSL Pipeline ADC SAR ADC Motor Servo Celluar Phone GSM, PDC Resolution (bit) Σ-Δ ADC CD/MD 17

18 Advantages and disadvantages of technology scaling Performance (Log) Gain Dynamic 1 Integration 2 L 1 GBP 1 L L 1, Supply voltage Range (for constant I DS ) 1 L Signal Swing Noise Mismatch 2 L 1/(Design Rule) (Log) Scaling 18

19 Figure of merit (FOM) of analog circuits Before ITRS2004 edition: FOM was defined for each category of circuits. LNA: Low noise amplifier VCO: Voltage controlled oscillator PA: Power amplifier ADC: Analog-to-Digital converter SerDes(SERializer/DESerializer) P : Power consumption IIP3: Third Order Input Intercept Point NF : Noise figure L: Spurious power PAE: Power efficiency FOM LNA FOM VCO FOM FOM FOM PA G IIP3 f ( NF 1) P 2 f0 1 f L{ f } P P ADC SerDes out G p PAE ENOB0 ( 2 R B ) P R P f f S 2 MuxDeMux ENOB 0 : Effective number of bits f S : Sampling frequency R B : Data Rate R MuxDeMux : Bit count of parallel data 19

20 Quiz Which circuit is better in a sensitivity and a signal-to-noise ratio? 20

21 Speed = Accuracy = Gain? Effective Number of Bits for Oversampling ADC SNR max OSR [ db] 6.02 N fs 2 f log[ M 2 M ] (20 M 1 Sampling frequency f S Maximum frequency of signal f o 10)log OSR Equivalent gain for LSB = 1(bit) 6.02(dB) Why is the increment of 1bit equivalent with the amplification of 6dB (2 times)? 21

22 Suggested answer Maximum number of N-bit binary code = 2 N -1 Dynamic range of N-bit binary code system = (2 N -1)/1 Maximum number of (N+1)-bit binary code = 2*2 N -1 Dynamic range of (N+1)-bit binary code system = (2*2 N -1)/1 Then, the amplitude of signal that is equivalent for the differential dynamic range between (N+1)-bit and N bit system is comparable to (2*2 N -1)/ (2 N -1) [dB] Note that this calculation is made on a condition of M = 0 (no noise shaping) and OSR = 1 (no oversampling). More precise analysis is shown in next slide. 22

23 Effect of noise shaping and oversampling SNR for quantization noise and ENOB of oversampling conversion M SNRmax[ db] 6.02 N log[ ] (20 M 10) logosr 2 M 1 ENOB[ bit] [(20 M 10) logosr 20 log( M : Order of noise shaping transfer function OSR: Oversampling ratio M 2 M )] 1 Example Speed Accuracy Gain M = 0, OSR = 128, then ENOB = 4.5[bit], ΔSNR max = 27[dB] M = 1, OSR = 128, then ENOB = 10.6[bit], ΔSNR max = 64[dB] 23