Single Supply Dual 16-Bit Audio DAC AD1866

Transcription

1 a FEATUES Dual Serial Input, Voltage Output DACs Single + Volt Supply 0.00% THD+N ow Power 0 mw db Channel Separation Operates at Oversampling -Pin Plastic DIP or SOIC Package APPICATIONS Multimedia Workstations PC Audio Add-In Boards Portable CD and DAT Players Automotive CD and DAT Players Noise Cancellation FUNCTIONA BOCK DIAGAM V D CK D Single Supply Dual -Bit Audio DAC AD -BIT DAC -BIT SEIA EGISTE -BIT SEIA EGISTE AD V EF V EF N N -BIT 0 DAC PODUCT DESCIPTION The AD is a complete dual -bit DAC offering excellent performance while requiring a single + V power supply. It is fabricated on Analog Devices ABCMOS wafer fabrication process. The monolithic chip includes CMOS logic elements, bipolar and MOS linear elements and laser trimmed, thinfilm resistor elements. Careful design and layout techniques have resulted in low distortion, low noise, high channel separation and low power dissipation. The DACs on the AD chip employ a partially segmented architecture. The first three MSBs of each DAC are segmented into elements. The SBs are produced using standard - techniques. The segments and - resistors are laser trimmed to provide extremely low total harmonic distortion. The AD requires no deglitcher or trimming circuitry. Each DAC is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate, producing ± V signals at load currents up to ± ma. The buffered output signal range is. V to. V. The. V reference voltages eliminate the need for false ground networks. A versatile digital interface allows the AD to be directly connected to all digital filter chips. Fast CMOS logic elements allow for an input clock rate of up to MHz. This allows for operation at,,, or the sampling frequency (where F S =. khz) for each channel. The digital input pins of the AD are TT and + V CMOS compatible. The AD operates on + V power supplies. The digital supply, V, can be separated from the analog supply,, for reduced digital feedthrough. Separate analog and digital ground pins are also provided. In systems employing a single + volt power supply, V and should be connected together. In battery operated systems, operation will continue even with reduced supply voltage. Typically, the AD dissipates 0 mw. The AD is packaged in either a -pin plastic DIP or a -pin plastic SOIC package. Operation is guaranteed over the temperature range of C to + C and over the voltage supply range of. V to. V. PODUCT HIGHIGHTS. Single supply + V.. 0 mw power dissipation.. THD+N is 0.00% (typical).. Signal-to-Noise atio is db (typical).. db channel separation (typical).. Compatible with all digital filter chips.. -pin DIP and -pin SOIC packages.. No deglitcher required.. No external adjustments required. EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 0, Norwood, MA 00-0, U.S.A. Tel: /-00 Fax: /-0

2 AD* PODUCT PAGE QUICK INKS ast Content Update: 0//0 COMPAABE PATS View a parametric search of comparable parts. DOCUMENTATION Application Notes AN-: The Alexander Current-Feedback Audio Power Amplifier Data Sheet AD: Single Supply Dual -Bit Audio DAC Data Sheet DESIGN ESOUCES AD Material Declaration PCN-PDN Information Quality And eliability Symbols and Footprints DISCUSSIONS View all AD EngineerZone Discussions. SAMPE AND BUY Visit the product page to see pricing options. TECHNICA SUPPOT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 AD SPECIFICATIONS (T A = + C and + V supplies unless otherwise noted) Min Typ Max Unit ESOUTION Bits DIGITA INPUTS V IH. V V I 0. V I IH, V IH = V.0 µa I I, V I = 0.0 µa Maximum Clock Input Frequency. MHz ACCUACY Gain Error ± % of FS Gain Matching ± % of FS Midscale Error ±0 mv Midscale Error Matching ±0 mv Gain inearity Error ± db DIFT (0 C to +0 C) Gain Drift ±00 ppm/ C Midscale Drift 0 µv/ C TOTA HAMONIC DISTOTION + NOISE 0 db, 0. Hz ADN % AD % 0 db, 0. Hz ADN 0.0 % AD 0.0 % 0 db, 0. Hz ADN.0 % AD.0 % CHANNE SEPAATION ( khz, 0 db) 0 db SIGNA-TO-NOISE ATIO (With A-Weight Filter) db D-ANGE (With A-Weight Filter) 0 db Voltage Output Pins (, ) Output ange (±%) ± V Output Impedance 0. Ω oad Current ± ma Bias Voltage Pins (, ) Output ange +. V Output Impedance 0 Ω POWE SUPPY Specification, V and.. V Operation, V and.. V +I, V and = V 0 ma POWE DISSIPATION 0 0 mw TEMPEATUE ANGE Operation C Storage 0 00 C Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical EV. 0

4 THD+N db PS db CHANNE SEPAATION db THD+N db THD+N db GAIN INEAITY EO db Typical Performance AD dB 0 C 0 C C 0 0 0dB 0 C 0 0dB C FEQUENCY Hz INPUT AMPITUDE db 0 0 Figure. THD+N vs. Frequency Figure. Gain inearity Error vs. Input Amplitude 0 0 0dB dB 0 0dB FEQUENCY Hz Figure. Channel Separation vs. Frequency TEMPEATUE C 0 Figure. THD+N vs. Temperature 0 0 0dB dB 0 0 0dB SUPPY VOTAGE Figure. THD+N vs. Supply Voltage FEQUENCY Hz Figure. Power Supply ejection atio vs. Frequency (Supply Modulation Amplitude at 00 mv p-p) EV. 0

5 AD ABSOUTE MAXIMUM ATINGS* V to V to V to V to V to ±0. V Digital Inputs to V to V Soldering (0 sec) C *Stresses greater than those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WANING! ESD SENSITIVE DEVICE PIN CONFIGUATION PIN DESIGNATIONS V D CK D -BIT DAC -BIT SEIA EGISTE -BIT SEIA EGISTE AD V EF V EF 0 -BIT DAC N N Pin Mnemonic Description V Digital Supply (+ V) eft Channel atch Enable Pin D eft Channel Data Input Pin CK Clock Input Pin D ight Channel Data Input Pin ight Channel atch Enable Pin Digital Common Pin ight Channel Bias Pin Analog Supply (+ V) 0 ight Channel Output Pin N ight Channel Noise eduction Pin Analog Common Pin N eft Channel Noise eduction Pin eft Channel Output Pin Analog Supply (+ V) eft Channel Bias Pin ODEING GUIDE Temperature Package Package Model ange Description Option ADN C to + C Plastic DIP N- AD C to + C SOIC - AD-EE C to + C SOIC - EV. 0

6 Definition of Specifications AD TOTA HAMONIC DISTOTION + NOISE Total harmonic distortion plus noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the amplitudes of the harmonics and noise to the amplitude of the fundamental input frequency. It is usually expressed in percent (%) or decibels (db). D-ANGE DISTOTION (EIAJ SPECIFICATION) D-ange distortion is the ratio of the amplitude of the signal at an amplitude of 0 db to the amplitude of the distortion plus noise. In this case, an A-weight filter is used. The value specified for D-range performance is the ratio measured plus 0 db. SIGNA-TO-NOISE ATIO The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale output is present to the amplitude of the output with no signal present. It is expressed in decibels (db) and measured using an A-weight filter. FUNCTIONA DESCIPTION The AD is a complete, monolithic dual -bit digital audio DAC which runs off a single + volt supply. As shown in the block diagram, each channel contains a voltage reference, a -bit serial-to-parallel input register, a -bit input latch, a -bit DAC, and an output amplifier. The voltage reference section provides a reference voltage and a false ground voltage for each channel. The low noise bandgap circuits produce reference voltages that are unaffected by changes in temperature, time, and power supply. The input registers are fabricated with CMOS logic gates. These gates allow high switching speeds and low power consumption, contributing to the fast digital timing, the low glitch and low power dissipation of the AD. V -BIT DAC AD GAIN INEAITY Gain linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. It is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a lower level. A perfect D/A converter exhibits no difference between the ideal and actual amplitudes. Gain linearity is expressed in decibels (db). MIDSCAE EO Midscale error, or bipolar zero error, is the deviation of the actual analog output from a voltage at the bias pin when the twos complement input code representing midscale is loaded in the DAC. Midscale error is expressed in mv. D CK D -BIT SEIA EGISTE -BIT SEIA EGISTE V EF V EF 0 -BIT DAC N N AD Functional Block Diagram The -bit DAC uses a combination of segmentation and - architecture to achieve good integral and differential linearity. The resistors which form the ladder structure are fabricated with silicon-chromium thin film. aser trimming of these resistors further reduces linearity error, resulting in low output distortion. The output amplifier uses both MOS and bipolar devices and incorporates an NPN class A output stage. It is designed to produce high slew rate, low noise, low distortion, and optimal frequency response. EV. 0

7 AD Analog Circuit Considerations GOUNDING ECOMMENDATIONS The AD has two ground pins, designated as (Pin ) and (Pin ). The analog ground,, serves as the high quality reference ground for analog signals and as a return path for the supply current from the analog portion of the device. The system analog common should be located as close as possible to Pin to minimize any voltage drop which may develop between these two points, although the internal circuit is designed to minimize signal dependence of the analog return current. The digital ground,, returns ground current from the digital logic portion of the device. This pin should be connected to the digital common node in the system. As shown in Figure, the analog and digital grounds should be joined at one point in a system. When these two grounds are connected such as at the power supply ground, care should be taken to minimize the voltage difference between the and pins in order to ensure the specified performance. V D CK D AD N N 0.µF +.µf + POWE SUPPY POWE SUPPIES AND DECOUPING The AD has three power supply input pins. (Pins and ) provide the supply voltages which operate the analog portion of the device including the -bit DACs, the voltage references, and the output amplifiers. The supplies are designed to operate from a + V supply. These pins should be decoupled to the analog ground using a 0. µf capacitor. Good engineering practice suggests that the bypass capacitor be placed as close as possible to the package pins. This minimizes the inherent inductive effects of printed circuit board traces. V (Pin ) operates the digital portions of the chip including the input shift registers and the input latching circuitry. V is also designed to operate from a + V supply. This pin should be bypassed to digital common using a 0. µf capacitor, again placed as close as possible to the package pins. Figure illustrates the correct connection of the digital and analog supply bypass capacitors. An important feature of the AD audio DAC is its ability to operate at diminished power supply voltages. This feature is very important in portable battery operated systems. As the batteries discharge, the supply voltage drops. Unlike any other audio DAC, the AD can continue to function at supply voltages as low as. V. Because of its unique design, the power requirements of the AD diminish as the battery voltage drops, further extending the operating time of the system. (CAPACITO VAUES AE 0. µf UNESS OTHEWISE INDICATED) Figure. ecommended Circuit Schematic NOISE EDUCTION CAPACITOS The AD has two noise reduction pins, designated as N (Pin ) and N (Pin ). In order to meet specifications, it is required that external noise reduction capacitors be connected from these pins to to reduce the output noise contributed by the voltage reference circuitry. As shown in Figure, each of these pins should be bypassed to with a. µf or larger capacitor. The connections between the capacitors, package pins and should be as short as possible to achieve the lowest noise. USING AND The AD has two bias voltage reference pins, designated as (Pin ) and (Pin ). Each of these pins supplies a dc reference voltage equal to the center of the output voltage swing. These bias voltages replace false ground networks previously required in single supply audio systems. At the same time, they allow dc coupled systems, improving audio performance. EV. 0

8 Analog Circuit Considerations AD + V +V AD V D CK N +V FASE GOUND (.V) D +V + V N 0 Figure b. Circuitry Using Voltage Biases Figure a. Schematic Using False Ground Figure a illustrates the traditional approach used to generate false ground voltages in single supply audio systems. This circuit requires additional power and circuit board space. The AD eliminates the need for false ground circuitry. and generate the required bias voltages previously generated by the false ground. As shown in Figure b, and may be used as the reference point in each output channel. This permits a dc coupled output signal path. This eliminates ac coupling capacitors and improves low frequency performance. It should be noted that these bias outputs have relatively high output impedance and will not drive output currents larger than 00 µa without degrading the specified performance. DISTOTION PEFOMANCE AND TESTING The THD+N figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. Therefore, the THD+N specification provides a direct measure to classify and choose an audio DAC for a desired level of performance. Figure illustrates the typical THD+N versus frequency performance of the AD. It is evident that the THD+N performance of the AD remains stable at all three amplitude levels through a wide range of frequencies. A load impedance of at least kω is recommended for best THD+N performance. Analog Devices tests all ADs on the basis of THD+N performance. During the distortion test, a high speed digital pattern generator transmits digital data to each channel of the device under test. Sixteen-bit data is latched into the DAC at. khz ( F S ). The test input code is a digitally encoded 0. Hz sine wave with 0 db, 0 db, and 0 db amplitudes. A 0 point FFT calculates total harmonic distortion + noise, signal-to-noise ratio, and D-range. No deglitchers or external adjustments are used. EV. 0

9 AD Digital Circuit Considerations CK D M S B S B D M S B S B Figure. AD Control Signals INPUT DATA The digital input port of the AD employs five signals: Data eft (D), Data ight (D), atch eft (), atch ight (), and Clock (CK). D and D are the serial inputs for the left and right DACs, respectively. Input data bits are clocked into the input register on the rising edge of CK. The falling edges of and cause the last bits which were clocked into the serial registers to be shifted into the DACs, thereby updating the respective DAC outputs. For systems using only a single latch signal, and may be connected together. For systems using only one DATA signal, D and D may be connected together. Data is transmitted to the AD in a bit stream composed of -bit words with a serial, twos complement, MSB first format. eft and right channels share the Clock (CK) signal. Figure illustrates the general signal requirements for data transfer for the AD. TIMING Figure 0 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished properly. The input pins of the AD are both TT and + V CMOS compatible. D/D CK / >0ns >0ns >0ns >ns >0ns >0ns >0ns >0ns >ns >0ns Figure 0. AD Input Signal Timing The maximum clock rate of the AD is specified to be at least. MHz. This clock rate allows data transfer rates of,,, and F S (where F S equals. khz). The applications section of this data sheet contains additional guidelines for using the AD. EV. 0

10 Applications of the AD APPICATIONS OF THE AD The AD is a high performance audio DAC specifically designed for portable and automotive digital audio applications. These market segments have technical requirements fundamentally different than those found in the high-end or home use market segment. Portable equipment must rely on components which require low amounts of power to offer reasonable playback times. Also, battery voltage tends to diminish as the end of the discharge cycle is approached. The AD s ability to operate from a single + V supply makes it a good choice for battery operated gear. And, as the battery voltage drops, the power dissipation of the AD drops. This extends the usable battery life. Finally, as the battery supply voltage drops, the bias voltages and signal swings also drop, preventing signal clipping and abrupt degradation of distortion. Figure illustrates how the THD+N performance of the AD remains constant through a wide supply voltage range. Automotive equipment relies on components which are able to consistently perform over a wide range of temperatures. In addition, due to the limited space available in automotive applications, small size is essential. The AD has guaranteed operation between C and + C, and the -pin DIP or -pin SOIC package is particularly attractive where overall size is important. Since the AD provides dc bias voltages, the entire signal chain can be dc coupled. This eliminates ac coupling capacitors from the signal path, improving low frequency performance and lowering system cost and size. In summary, the AD is an excellent choice for multimedia, battery operated portable or automotive digital audio systems. In the following sections, some examples of high performance audio applications featuring the AD are described. AD with the Sony CXD0P Digital Filter Figure illustrates a -bit CD player design incorporating an AD DAC, a Sony CXD0P digital filter, and -pole antialias filters. This high performance, single supply design operates at F S and is suitable for portable and automotive applications. In this design, the CXD0P filter transmits left and right channel digital data to the AD. The left and right latch signals, and, are both provided by the word clock signal (CKO) of the digital filter. The digital data is converted to low distortion output voltages by the output amplifiers on the AD. Also, no deglitching circuitry or external adjustments are required. Bypass capacitors, noise reduction capacitors and the antialias filter details are omitted for clarity. ADDITIONA APPICATIONS In addition to CD player designs, the AD is suited for similar applications such as DAT, portable musical instruments, laptop and notebook personal computers, and PC audio I/O boards. The circuit techniques illustrated here are directly applicable in those applications. Figures,,, and show connection diagrams for the AD and several popular digital filter chips from NPC and Yamaha. Each application operates at F S operation. Please refer to the appropriate sections of this data sheet for additional information. +V POWE SUPPY CXD0P TEST SOT CKO DATA DATA AD V D CK N.kΩ 000 pf.kω 0 pf.kω NJM pf EFT CHANNE IGHT CHANNE.kΩ V DD S D.kΩ BCKO N S 0.kΩ CK 000 pf ATCH 0 Figure. AD with Sony CXD0P Digital Filter EV. 0

11 AD +V POWE SUPPY SM BCKO WCKO DO DO V DD AD V D CK N OW- FITE EFT CHANNE 0 S S 0 D N 0 OW- FITE IGHT CHANNE OW OW0 COB Figure. AD with NPC SM Digital Filter +V POWE SUPPY SMAP V DD AD V BCKO WDCO D CK N OW FITE EFT CHANNE DO D DO 0 N 0 OW FITE IGHT CHANNE S OMOD Figure. AD with NPC SMAP Digital Filter 0 EV. 0

12 Applications AD +V POWE SUPPY YM AD V V DD / ST S D CK N OW- FITE EFT CHANNE BCO D WCO DO 0 N 0 OW- FITE IGHT CHANNE V DD DO V B Figure. AD with Yamaha YM Digital Filter +V POWE SUPPY DI N V AD SM0A/B BCKO BCKO O D CK N OW- FITE EFT CHANNE S VDD VD D D OW0 WCKO O DO DO DO D G 0 N 0 OW- FITE IGHT CHANNE Figure. AD with NPC SM0C Digital Filter EV. 0

13 AD OUTINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N) Package Plastic SOIC () Package 0. (.) MAX 0. (.) 0.0 (0.) 0. (.) 0. (.) MAX 0. (.0) 0. (0.) C0 0 / 0. (.) 0.0 (0.) 0.0 (0.) 0. (.) 0. (.) MIN 0.0 (0.) 0. (.) 0.0 (0.) 0.00 (0.) 0. (0.0) 0.0 (.) EF 0.0 (0.) 0.0 (.) 0.0 (0.) 0.0 (.0) PINTED IN U.S.A. EV. 0