Non-Volatile Memory Characterization and Measurement Techniques

Transcription

1 Non-Volatile Memory Characterization and Measurement Techniques Alex Pronin Keithley Instruments, Inc

2 Why do more characterization? NVM: Floating gate Flash memory Very successful; lead to explosion in consumer market (tables, smart phones) There is concern that standard Flash is hitting the wall and cannot sustain Moore s law of storage expansion Response: Switch to 3D Flash technologies New materials and new technologies In test and measurement there is increased demand for characterization Need for fast voltage and current transient measurements Integration of DC and pulse measurement Simplicity of use 2

3 Outline Review types of NVM NVM test requirements and overview Common NVM test parameters Capabilities of Keithley s Model 4225-PMU Ultra-fast I-V Module for NVM characterization Examples of test projects and characterization Flash Memory PRAM/PCM FeRAM Measurements optimization 3

4 NVM types FG Flash, CTF/SONOS charge trapping Flash, 3D Flash PCM/PCRAM Phase change memory Resistive: ReRam/RRAM, CBRAM MRAM Magnetoresistive, STT-MRAM: spin transfer torque MRAM FeRAM Ferro electric RAM CNT RAM carbon-nanotube RAM 4

5 Ideal Memory attributes Low cost and high density with scalability road map Fast read/write (similar to or faster than existing DRAM speeds) High endurance (to address DRAM or SSD applications) Long retention Low power and voltage requirements Compatible with existing logic circuits and semiconductor processes 5

6 New NVM test requirement Traditional requirements Accurate DC measurements (SMU source measurement units) for Vt, Set/Reset Resistance, etc. High fidelity pulses Optimized integration of DC and pulse instruments Transient characterization capability for new NVM technologies 6 Provides fundamental data on intrinsic material properties Initial implementations: Use load resistors and capacitors in combination with digitizing scopes; one-off, customized system, which requires high maintenance Limited accuracy, difficult calibration Development of new pulse measure instrumentation Pulse generation functionality combined with measure Simultaneous measurement of high speed voltage and pulses Integration with DC and ease of use

7 NVM test parameters Pulse amplitude Pulse amplitude fidelity (ringing, overshoot, and undershoot ) Ability to output multi-pulse waveforms Pulse timing (rise, fall time, and pulse width ) Dynamic, simultaneous ultra-fast current and voltage measurement Remote pulse amplifier (to decrease parasitic effects of interconnects) Current compliance or current control Switching and integration between pulse and DC instruments Channel synchronization 7

8 Models 4225-PMU and 4225-RPM The Model 4225-PMU Ultra-Fast I-V Module is a single-slot instrument card for the Model SCS Two channels of voltage pulse sourcing with integrated, simultaneous real-time current and voltage measure for each channel Each channel can independently source ±10V or ±40V into high impedance, 80V amplitude in differential mode Two A/D converters per channel that sample the voltage and current simultaneously, with 200M Sample rate Timing features from 20ns to 40s, automatically synchronized to within ±2ns across channels Arbitrary segment waveform (Segment ARB ) capability for multi-level or multi-pulse waveforms 8

9 Multi-level waveforms with Segment ARB capability Flash memory program and erase waveform 2 pulses, 3 levels Multi-level pulse waveform 4 pulses, 3 levels Created by 16 linear voltage segments (grey numbers) and 4 measurements (red boxes) 9

10 Model 4225-RPM (Remote Pulse Unit) The Model 4225-RPM Remote Amplifier/Switch is an optional addition to the Model 4225-PMU Located near the device-under-test Allows for low current pulse measurement ranges (from 10mA to 100nA) Decreases parasitic effects of interconnects Provides switching for Source measurement units (SMUs) CVU signals Pulses from PMU No re-cabling to change instruments 10

11 Connection setups for NVM testing 2-terminal test device 4-terminal test device 11

12 Flash testing Program and erase conditions for Fowler-Nordheim tunneling Test hardware One Model 4225-PMU with two Model 4225-RPMs Two SMUs 12

13 Connection to four-terminal floating-gate Flash device 13

14 Flash data: program and erase Vt Program Erase 14

15 Flash program pulse Simultaneous gate voltage (blue) and gate current (red) measurement Program Voltage and Current Waveforms Gate Voltage (V) FN current parasitic current Gate Current (A) Time (s) 15

16 Flash endurance 16

17 What is PRAM? 17 PCRAM Phase Change RAM Based on chalcogenide alloys Amorphous phase after RESET High resistivity > 1MOhm Melting of material Fast cooling (RESET) Fall time for PRAM materials is about 30ns or even faster Crystalline phase after SET operation Low resistivity <~1kOhm Lower energy state Raising temperature above crystallization temperature Re-crystallization by slower cooling (SET) Re-crystallization rates dropped from hundreds of ns to 30ns

18 PRAM material testing R-load technique Connection diagram for PRAM tests 18

19 PRAM I-V characterization Blue line: voltage pulse vs. time Red line: current response vs. time Rise time: 10µs, can be as short as 20ns Note: switching for high resistive state to low resistive state at 0.7 V I-V curve measured by the PMU with RPMs. This test uses the same data shown to the left. 19

20 Definition of PRAM R-I curve Diagram explains the R-I curve measurement sources from the RESET-measure-SET-measure waveform. The amplitude of SET curve is swept, while measuring RESET resistance (red M), SET current (green M), and SET resistance (blue M) 20

21 PRAM RI curve, data Voltage (blue) and current (red) waveform RESET pulse puts DUT into a high resistance state SET pulse sets the low resistance state The second and last pulse measures the resistance of the RESET/SET state R-I curve shows the variation of the SET resistance as the SET pulse amplitude is swept 21

22 PRAM endurance SET resistance is plotted as a function of total number of cycles SET resistance increases as applied stresses increases 22

23 Ferro-electric memory Ferro-electric memory is based on polarization switch due in the presence of critical electrical field It is NOT ferro-magnetic memory Read-write processes are destructive intrinsically and require refreshing Characterization tests Hysteresis curve of polarization (charge) vs. field PUND (positive-up-negative-down) test References: 23

24 FeRam test setups Traditional: Sawyer-Tower circuit C0 (load cap) >> C Vin ~ V Vo << Vin, measures charge/polarization Requires ability to measure small voltage 24 Measurement with Pulse Measure Unit Measures current and charge directly No need for load cap Does not require measurement of small voltages

25 FeRAM hysteresis waveform measurement Voltage Current 25 Voltage Up/Down/Up sweep waveform (blue line on the left graph) Measure response current from low side of FeRam cap (red line) Integrate current to charge and plot charge vs. voltage to get Hysteresis curve (black curve on the right graph)

26 FeRAM PUND (positive-up-negative-down) test 26 Procedure: Force PUND pulse sequence using Segment ARB functionality of PMU/RPM (blue curve) Measure response current (red line) Integrate current to obtain (area under curve) P, Pa U, Ua N, Na D, Da Psq, and Qsw Advantage: low noise measurement

27 FeRAM endurance Test Psw (P-U) Qsw (1/2(P-U+N-D)) Total endurance is about 1e8 cycles Test time is in minutes 27

28 ReRAM and CBRAM testing Diagram for one of the multi-pulse tests included in the NVM library In many cases, ReRAM and CBRAM testing is done with SMU (DC sweep) DC current compliance is used But SMU compliance circuitry is not instantaneous! It takes hundreds of microseconds to milliseconds We provide Segment Waveform, dynamic Voltage sweep to characterize I-V curve for any sweep test DC test time is always >0.1ms Pulse test time with PMUs can be as short as 40ns 28

29 Capacitive charging effects during pulse transitions 29

30 Avoiding capacitive charging effects High Low dv/dt 0 Measuring the current on the LOW side of the DUT, away from the applied pulse, is the key to avoiding the charging effect The side of the device connected to Channel 2 has a dv/dt that is essentially 0 This approach is sometimes called pulsing on the high side and measuring the current on the low side There is no capacitive charging current seen during the pulse transitions. Only the current flowing through the resistor DUT is seen. No charging effects, just current flowing through the test device 30

31 NVM Testing with the Model 4200-SCS Hardware minimum requirements Model 4200-SCS with KTEI V8.2 or higher Two SMUs, either medium power (Model 4200-SMU) or high power (Model 4210-SMU). One Model 4225-PMU with two Model 4225-RPMs Compiler to modify the NVM test modules Software components KTEI V8.2 with standard suite of characterization tools NVM library and NVM project, with example test setups and data for PRAM, FLASH NAND, and FeRAM For additional information, see application note #3141 Non-volatile Memory Pulse I-V Characterization Techniques at 31

32 Summary Most of the NVM technologies have similar electrical characterization requirements Multi-level pulse waveforms Simultaneous current and voltage sampling during the test Wide range of voltage sourcing and current measurements The Model 4200-SCS with Models 4225-PMU and 4225-RPM simplifies complex NVM test requirements Hardware that does not require load resistors or load capacitors Integrated, simultaneous fast current and voltage transient measurements Segment ARB capability for multi-level, multi-pulse waveform creation Included project contains sample tests and data for multiple NVM technologies 32

33 Contact Keithley for further information Worldwide Headquarters Within the USA: KEITHLEY Outside the USA: Additional offices: Europe: Germany: (+49) Great Britain: (+44) Asia: China: (+86) Japan: (+81) Korea: (+82) Taiwan: (+886)