8-, 10-,12-BitVideoSpeed DEVICES CurrentandVoltageOut,D/A Converters OBSOLETE

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1 P'" W JG 7 {() F 7 ANALOG 8-, 10-,12-BitVideoSpeed DEVCES CurrentandVoltageOut,D/A Converters FEA TURES Current Settling Times to 15ns :t1.5v Compliance Voltage Settling Times to 100ns (MDH) Monotonicity Guaranteed Over Temperature High Output Currents - 15mA -30 C to +85 C Operating Range ndustry Standard Pin Outs 20V, p.p Out (MDH) TTl or ECl logic APPLCATONS CRT Vector Displays Digitial Waveform Generation Automatic Test Equipment TV Picture Reconstruction,. GENERAL DESCRPTON This broad family of digital-to-analog converters represents the "state of the art" in modular, high speed, voltage and current output devices. The family consists of a total of 11 devices in 4 series (MDS, MDSE, MDSL and MDH) that allow the user to make engineering trade-offs between resolution, speed, output and logic type. The first 3 are high compliance current output units which make possible linear output swings greater than :t1.5v. The voltage output MDH series contain a fast settling hybrid operational amplifier which provides:t 10V output at :t5oma. To simplify selection these major specifications are summarized in Table 1. FULLSCALE FULL SCALE NPUT MODEL BTS SETTLNG TME LOGC MDS (Fastest Settling High Current Out) 15mA 15ns to 0.4% FS TTL MDS-020 to 15mA 20n5 to 0.1% FS TTL MDS mA 40n5 to 0.025% FS TTL (MDS with ECL Logic) MDS-O815E 8 15mA 15ns to 0.4% FS ECL MDS-020E 10 15mA 20n5 to 0.1% FS ECL (Low Current MDS) MDSL SmA 25n5toO.l% TTL MDSL SmA 25n5toO.l% TTL MDSL SmA SOns to 0.025% TTL MDH (Voltage Out MDSL) 10V /50mA 150n5 to 0.4% TTL MDH-l00l 10,tOV/50mA 200n5 to 0,1 % TTL MDH tov /50mA 500n5 to 0.025% TTL Table 1. achieve ultra-high speed operation. n fact, it is the fastest 12- bit D/A available, settling to 0.025% in 40ns. Hybrid construction eliminates the thermal lag problem inherent in 12-bit D/A's constructed with discrete components. This in turn means that the accuracy is maintained over the total frequency range of operation, yielding superior results for frequency domain applications. The MDS-1240 is particularly well suited for CRT display applications because of its unsurpassed speed and drive capabilities. The high output current (SmA) allows the use of low impedance loads so that settling times remain short - even with higher output voltage levels. The ability to drive load capacitance is at least 3 times that of other 12-bit D/A's thus providing capability to drive a terminated transmission line directly. The MDS-815 and MDS-020 provide similar performance at 8 and 10 bits, while the MDS-E units provide it with ECL logic. MDSL-082S, MDSL-035 and MDSL-12S0 also utilize this reliable hybrid construction. The use of laser trimmed resistor networks within the D/A's not only eliminates thermal time lag errors but provide the linearity tempco of 2ppmtC; guaranteeing monotonic operation over the extended temperature range of -30 C to +8SoC. The power dissipation of the MDSL series is one-half that of competitive D/A's, but a full SmA output current is maintained. This allows driving transmission lines or other low impedance loads directly. (continued on page 1955) SPEED WTH PRECSON Analog Devices' model MDS-1240 is the first D/A converter available with highly reliable, internal hybrid construction to Page 1 of 8 D/A S 1915 ',:-",~,,"",,'C,:C ';'" -:", ~",;:",,":_'.,-: :-" "".':_-"_:'.~,':,,-:.:.c'-,

2 ',',:' <,:'"",..:,~.~,,':".,':<""",-,;",.,::,,:,::;,.:,.',,',:,,':;:":'.-:.',;,:' ",:"',',", SPECFCATONS C unlessotherwisespecified) CURRENT CURRENT MDS MDS-E (ECL) MODEL UNTS RESOLUTON Bits (Weight) la ACCURACY nitial (Adjust to 0) :!:%FS Linearity (ntegral) max :!:li2... '. Monotonicity Guaranteed Over OperatingTemp Range Zero Offset (Adjust to 0) SnA max '... TEMPERATURECOEFFCENTS Linearity ppm/c Gain ppm/c Offset (ipolar) ppm/c 15 STABLTY WTH TME :!:%/yrmax DATA NPUTS Logic Comparability TTL " ECL ECL Logic Voltage Levels BitOnLogic"" V +2 to +5.0 ' Bit Off Logic"0" V 0 to +0.4 ' LogicCurrent (Each Bit) BitOnLogic"" JlA ';;;50. Bit Off Logic"0" ma -8-5max ma N/A. -10max Coding.. All Units Binary(BN) for Unipolar, Offset Binary(OBN) for Bipolar.. Current Range Unipolar ma Oto+15 '. Oto-15 0 to -15 Bipolar ma :!:7.5. mpedance (See Figure 3) n :!: 1%.. Load Resistance for VOUT (See Figure 5) Oro+lV n Compliance (MDH VOUT) V +1.5,-2 '. -1.5, , +2 :!:V n 4.32k ' 750. NTERNALREFERENCEVOLTAGEOUT V N/A :!:5% '. SETTLNG TME2 Current ns to %. S to to to 0.1 ' 40 to Unipolar Voltage (RL = 300n 10pF) ns to % Bipolar Voltage (RL =2325n 0pF) ns to % POWER REQUREMENTS Range V :!:11to :tl6 ' :!:14.5 to :!:16.5. Current at Nominal +V ma max Current at Nominal-V ma max S POWER SUPPLY REJECTON RATO %/V 0.04 '.. +15V "la/v V (Bipolar) %/V V (Unipolar) %/V -0.2 TEMPERATURE RANGE Operating c -20 to +75 ' -30 to +85 ' Storage c -55 to +85 ' -55 to +125 ' CASE '. Diallyl Phthalate per ML-M-14 Type SDG-F PRCE (1-4) $ ls to 0.10.Specifications NOTES, same as MDS~81S. 1 ppmt' C for current output, Op amp is SOllY / C. (See tables in Figures and 17, for overall TC in various configurations.) 'For Full Scale Step D/A S Page 2 of 8 '0 to +5V Out '0 to +10V Out See Figures 15 and 16 for test circuits. 'tsv Out f Specifications subject to change without notice,

3 CURRENT VOLTAGE OUT MDSL MDH Depends on VOUT lomv 10mV 10mV See Note to +5 0 to +5 0 to +5 :t50 max :t50 max :t50 max :t2.5 :t2.5 :t2.5 :t50 max :t50 max :t50 max 600:tl% 600:t1% 600:t 1% 0.1 max 0.1 max 0.1 max... :t10 :t10 :t N/A N/A N/A 2.325k 2.325k 2.325k N/A N/A N/A -6.2 :t5% -6.2 :t5% -6.2 :t5%, -6.2 :t5% -6.2 :t5% -6.2 :t5% 25 to to to ( to to to to to to to to to to to to to to toto toto l30tao to to to to :t12to:t15 :t12to:t15 :tl2 to :ts :t14.5 to :t16.5 :t145 to :t16.5 :t14.5 to :t to to to to to to to to to to to to Page 3 of 8 D/A S 1935 ~--..~- -~ ---

4 MDS-o815, 0815E, 1020, 1020E OUTLNE DMENSONS Dimensions shown L'1inches and (rom). 1- t1 ' BOTTOMVEW 2.3 (58.01 MO""" MOS-'O2O MOS-CO'" MOS-'...' A _ 0.43 "o.") + mil 23 ;58.01 Wil -, r-.' 12.54GRO DOT ON TOP NDCATES POSTON OF PN,. MATNG SOCKET PN DESGNATONS MDS-o81 5E, 1020E PN FUNCTON PN FUNCTON 1 BT 1 () 9 BT 9 2 BT 2 10 BT 10 3 BT V 4 BT BT5 13 COMMON 6 BT BT 7 15 COMMON 8 BT V MD5-1240, MDSL-O825, 1035, 1250 OUTLNE DMENSONS Dimensions shown in inches and (mm)..l MOS.'2.. MOSL<l )---j MOSL.'035 MOSL."" --L G ) :t" 321. DOT ON TOP NDCATES FOSTON OF PN,. MATNG SOCKET MSA-l PN DESGNATONS MD5-0815, MDS ' 110.2) a++++1 L." (OA).L :. 16 _J(50.8) T OOTTOMVEW-11-0.'1254'GR0 PN FUNCTON PN FUNCTON 1 BT 1( 9 BT9 2 BT 2 10 BT 10 3 BT V 4 BT BT5 13 COMMON 6 BT BT7 15 COMMON 8 BT V MDH-o870, 1001, 1202 OUTLNE DMENSONS Dimensions shown in inches and (mm). r 2.0"".8)---1i 0.'.L MOH.(J870MOH.'OO'. MOH ' ) ~ Lo.25(..., 3> ' '.L,. MATNG SOCKET MSA-1 PN DESGNATONS MDS-1240, MDSL-O825, 1035, 1250 PN DESGNATONS MDH-o870, 1001, (254) GRD OOT ON TOP NDCATES POSTON OF PN,..-OOTTOMVEW (50..' PN FUNCTON PN FUNCTON 3 BT 1 NPUT ( 15 BT 11 NPUT 4 BT 2 NPUT 16 BT 12 NPUT 5 BT 3 NPUT 17 REFERENCE NPUT 6 BT 4 NPUT 18 REFERENCE 7 BT 5 NPUT 28 ANALOG 10 BT 6 NPUT BT 7 NPUT BT 8 NPUT 31-15V POWER NPUT 13 BT 9 NPUT V POWER NPUT 14 BT 10 NPUT 7 j DGTAL NPUTS 1",581 BT 1 BT2 BT3 BT4 BTS BT6 BT7 BTS BT9 BT 10 (lsb C 12 COMMON COMMON PN FUNCTON PN FUNCTON 3 BT 1 NPUT () 17 REFERENCE fput 4 BT 2 NPUT 18 REFERENCE 5 BT 3 NPUT 22 ANALOG 6 BT 4 NPUT 24 +NPUT 7 BT 5 NPUT 25 -NPUT 10 BT 6 NPUT 26 FXED GAN 11 BT 7 NPUT 28 CURRENT 12 BT 8 NPUT BT 9 NPUT BT 10 NPUT 31-15V POWER NPUT 15 BT 11 NPUT V POWER NPUT 16 BT 12 NPUT DGTAL NPUTS BT 1 BT 12 lsb MDS and MDSE Block Diagram HYBRD CURRENT DA 18 REF OUT CURRENT +SV ~SV (M581 BT 1 BT2 BT 3 BT4 BTS BT6 BT7 BT 8 BT9 BT 10 BT 11 BT 12 REFNe 10 to ~.2V- 0 TO SMA ' REF OUT 17 S HYBRD CURRENT DA Z,N = 4.641< Zo-soon '" -SMA F.S. 3.16k gt N 22 ";8; tlov (MAX) 'SOMA (MAX N FXED GAN +SV -SV end MDS-1240 and MDSL Series Block Diagram Page 4 of 8 MDHSeries Block Diagram 1945 D/A S "-,-"""""-""-~'-",,,,,,",,"--

5 MDH SERES APPLCATONS By using external feedback resistor and capacitor as shown in Figures 15 and 16, other full scale output ranges from 2V to 10V may be obtained. DGTAL NPUTS BT 1 BT 12 MDH DA +1SV soon } FS ADJ 30 - ~~DDUTPUT } MAVBE OMTTED Vo. UP TO 10V >6OmA CURRENT SEEBELOW ft DGTAL NPUTS ll BT 12.USE NVERTER OR FF afar 2'S COMPL. 1', DGTAL NPUTS ' -....",,! 4 '5 i '7 ill ~~:: ill 12 i3 i4 is ii 29 _ 24 +NPUT ADJ NOTES' -16V +16V 1. VALUE OF C S APPROXMATE. A FXED CAPACTOR WTH TOLERANCE OF >1pF MAV BE USED F 601< DEGRADATON OF SETTLNG TME S PERMTTED F SETTLNG TME S TO BE OPTMZED,AN ADJUSTABLE CAPAC- TOR SHOULD BE USED FOR C AND ADJUSTED FOR MNMUM SETTLNG TME. 2. NULLNG MAV BE ACCOMPLSHED BV CONNECTNG A 1Ok POTENTOMETER BETWEEN +16V AND -16V, AND CONNECTNG TS ADJUST- ABLE T;.p TO A 1Ok RESSTOR. THE OTHER END OF THE RESSTOR S CONNECTED TO PN 2B. TVPCAL UNCOMPENSATED S '" OF FULL SCALE. VOLTAGE SETTLNG R C TME TEMPCO 0 to +2V 70ns loov/c 2k 10pF 0 to +5V loons 250vfc 8k 2pF Oto+lOV 200ns 500V!'C 18k 0.5pF NOTES' 1. Tho 200n POTENTOMETER S ADJUSTED FOR AN CUTPUT OF -FS WTH ALL ZEROES N THE DGTAL NPUT. 2. THE soon POTENTOMETER S ADJUSTED FOR AN OF +F5-1 WTH ALL ONE'S N THE DGTAL NPUT. -16V +1SV 3. FOR TWO'S COMPLEMENT 12SC! OPERATON, AN EXTERNAL NVERTER MUST BE USED TO COMPLEMENT BT 1-4. AN ADJUSTABLE CAPACTOR MAV BE USED FOR C AND ADJUSTED TO OPTMZE SET- TLNG TME. VOLTAGE SETTLNG TME TEMPCO RL C R :tlv 70ns 100V fc 383 lopf 2k :t2v loons 200V /C 383 2pF 6k :t5v loons 250vfc 9.1k 2pF 8k :tlov 200ns 500vfc 9.1k 0.5pF 18k Figure 15. Binary Coding Unipolar Output Configuration Figure 16. Offset Binary Coding or 2'$ Comp Coding Bipolar Output Configuration 19B5 DA S Page 5 of 8

6 (MDS-1240, MDSL-0825, 1035, 1250 continued) MDSL DGTAL NPUTS Mse BT 1 BT 12 VOLTAGE MDS/MDSE-81S, 1040 DGTAL NPUTS [ DA V +15V REF N CALBRATON PROCEDURE CODE WTH NPUT ADJUST THE SOO1 (R) POTENTOMETER FOR VOLTS. WTH NPUT CODE ADJUST THE (RZ POTENTOMETER FOR VOLTS. R1 soon ZERO Figure 70. Bipolar Current Output «::~1 BT2~ BT S o:il BT ) DA 12 '.~ Figure 77. Voltage Output 11V FS 2.321<11(75011 MOS.240) GROUNO DGTAL NPUTS BT 1 BT 12 SEE NOTE -15V "5\' VOLTAGE Vou,. R111NkOi +1 VOLTS FS UNPOLAR 110V (MAX AT 1100mA R3 SOO1 FS ADJ }EXT REF N NOTES,,. CRCUT SHOWN FOR UNPOLAR POSTVE 4. FOR BPOLAR CONNECT SETTLNG TME S APPROX. POTENTOMETER BETWEEN PNS 29 AND MATELY lsons. 2. FOR OTO +OV R ,R=Skl1. 28 AND 2.32kl1, UN AND VOUT PN 29. R2SSE1..1O (p-p) = 2 (R N Wi "1, CS APPROXMATELY lopf AND MAY BE R3 S ADJUSTED FOR DESRED, ADJUSTED FOR BEST TRANSENT RESPONSE, RANGE S APPROXMATELY +5%. Figure APPLCA nons DGTAL NPUTS 73. Noninverting Unipolar or Bipolar Voltage Output DA NPUT REGSTER :[..f. 1 T 11 i2 i LSii16 R2 300n REFOUT -'5V,'5V MDS '3 R2 200n 9 DGM 1040 VOLTAGE SETTLNG TME. 20no } TWO S UP TO 2V (F-p) MDS-1240, MDSL (all) DGTAL NPUTS BT BT 12 NOTE, DA R 26 VOLTAGE (Vou,. -R x 101 R3 loon TO 1kn REF N } EXT FS ADJ STROBE r-l STWBE -~~ - ~6'~~6f:~~;':;;C'y"MH' NOTES ON DEGLTCHED D/A,,. CONSULT DGM DATA SHEET FOR DEGLTCH CRCUT DETALS. R' S VARED TO OBTAN DESRED 2. LEVEL FOR 0 TO'W OUT. PUT,R'.,oon. Figure 74. Ultra High-Speed Deglitched D/A FOR UNPOLAR VOL TAGE CONNECT JUMPER BETWEEN PNS 29 AND 30. FOR BPOLAR VO.TAGE CONNECT A SOO1POTENTO. METER BETWEEN PNS 28 AND 29 AND ADJUST FOR ZERO WTH NPUT. /'" Figure 72. nverting Unipolar or Bipolar Voltage Output Page 6 of 8 D/A S ~

7 ANALOG BPOLAR, NONNVERTNG +FS,-l +1/2 FS 0-1/2 FS -FS BNARY ANALOG UNPOLAR, NONNVERTNG +FS, -l +3/4 FS + 1/2 FS +1/4 FS 0 STRAGHT BNARY Table 2. nput Coding "B" TRACE 2OMv/DV "A" TRACE 2V/DV 5ns - DV Figure 2. NTERNAL CURRENT DAC CHARACTERSTCS ' 1 R ' 20 /,-a'to 10 L- J CURRENT CONTROLLED BY NPUT DGTAL CODE Figure 3. Current Equivalent Circuit. OJ! 0.1 ~ " , TME.. ns 20 2S Figure 6. Accuracy vs. Time - MDS and MDSE BASC CONNECTONS AND CALBRATONS MDS/MDSE-o DGTAL NPUTS ~~~B,J BT 2 { BT 10 BT \ \\ \ \ \ '\. DA r, R Zo L- J VOLTAGE CONTROLLED BY DGTAL NPUT CODE OffSET Figure 4. Voltage Equivalent Circuit DGTAL NPUTS [ Figure 7. Unipolar Output Current \:'i~1 BT 2 BT 9 BT 13 2 DA i.! 10 MDS-1240, MDSL-o825, 1035, Wl'H NPUT CODE OF 12 ' ADJUST POTENTOMETER FOR 200" ZEROVOLTS ~ 14 ".V MAX Rl Figure 8. Bipolar Output Current 29 > ~ is > DGTAL NPUTS i f T BT '2 lsb DA OVTO"VFS 'B n MDSL.,oon MDS.,240 REF OUT } EXT TO FS "1! ADJ REF N -15V -'5V RL - 1! 350 4("",; 3k 2-4- Figure 5. VOUT vs. Load Resistance MDS.0815, Page 7 of 8 Tho '0011 POTENTOMETER MAY BE OMTTED F ABSOLUTE ACCURACY OF FUll SCALE S NOT REOURED. N THS CASE PNS 17 AND '8 SHOULD BE SHORTFD AND THE FULL SCALE CURRENl' WilL BE SmA.5%. MDS 'O.2mA '5%1 Figure 9. Unipolar Current Output 1965 D/A S "",-~;.;.~.._~ -~ ~~

(continued from page 1915) Each DA is housed in industry standard size cases, and each has an internal precision reference. Bipolar operation is achieved by external pin interconnection.

8 (continued from page 1915) Each DA is housed in industry standard size cases, and each has an internal precision reference. Bipolar operation is achieved by external pin interconnection. n normal circumstances, no external components are required for operation into [ow impedance loads. Designed primarily for PCB mounting, these D/A's may also be plugged into standard DL sockets mounted on 1.8" centers (MDS series 2" centers). For ultra-high reliability, this D/A series is optionally available with burn-in extended beyond the Analog Devices standard of 96 hours at +2SoC. NOTES ON FAST-SETTLNG D/A S nvariably, fast-settling D/A converters use current rather than voltage switching. There are inherent advantages to current-switching converters, since it eliminates an output amplifier. f there is no output amplifier, there is no slew rate limitation which slows settling. The absence of an output amplifier also means there are no overshoot and ringing problems often associated with feedback amplifiers. The settling time of a current-switching is based on: 1. The RC time constant of the converter output. 2. The settling time of the output current change. D/A converter, then, f the settling time of the D/A converter under consideration is determined by the RC time consta~t, the output capacitance and output impedance become very important. As a typical example in the Analog Devices' D/A converters, output capacitance is SpF, and nominal output impedance is 16Sn. For test purposes, the output of these D/A converters are loaded with approximately S0n. (There is no "trick" or "gimmick" in loading the output of the converter; it is done to provide an output voltage of approximately 1.OV to 1.2V.) This loading means RC =80 X S X =DAns. Since settling time is approximately 7 RC, the overall settling time, if determined by the RC time constant, would be 2.8ns. Based on this, it becomes obvious the RC time constant of such converters outputs is not the limiting factor in establishing settling time. nstead, the settling time of the converters is based primarily on the settling time of the overall (outpu t) current change, since the effect of the RC time constant is "swamped." Expressed in another way, this means settling time for the MDS series converters is relatively independent of load resistance, unless substantial load capacitance is present. The settling time of the output current, in turn, is based on: 1. The settling time of each switch within the converter. 2. The time skew among the digital inputs which cause the switching action. Some manufacturers of fast-settling D/A converters spec settling time under the conditions of all digital inputs changing from "0" to "1 H,or vice versa. At first glance, it would appear this is the "worst case" condition for measuring settling time, since maximum current is being switched. Unfortunately, this method of specifying neglects an important characteristic of saturated logic... the propagation delay for negative-going inputs is different from the delay for positive- -~~ ~going inputs on all forms of saturated logic. The TTL or DTL driving logic, and the D/A input circuits for current-switching D/A's are subject to this same characteristic. Thus, the time skew of the individual current switches within the converter is worse when one or more input bits are out of phase with the others. This is true even for ideal inputs in which the digital inputs arrive simultaneously; if there is time skew among the bit inputs, of course, the problem becomes more pronounced. Note, settling times even better than those specified for the MDS series become possible if digital input bit arrivals are deskewed. Page 8 of 8 These differences among the switches cause a discontinuity or "glitch" in the output. The true "worst case" glitch always occurs at the switching point of the Most Significant Bit or the center point of the output range, because nearly equal and opposite currents are being switched within the converter.!n addition, all "0" to all "1" switching overlooks the practical aspects involved. There are relatively few times when all of the input bits will be changing from one state to the other on successive input changes; however, the will switch out of phase with all other bits each time the analog output of the converter crosses the midpoint. n considering the choice of a "fast-settling" D/A converter, then, the user should look for the following points in the data sheet: 1. f the settling time spec has all bits changing state identic~ly, it neglects the phenomenon associated with saturated logic discussed earlier. 2. s the settling time specified with an impractically-owimpedance load? f the RC time constant of the converter output is the major factor in establishing settling time (because of high output capacitance and lor resistance), a low impedance load helps make settling time look better. A low impedance load means the voltage being dev<:loped at the output is oftentimes too small to be useful. A higher-impedance load which can develop a useable output of 1.OV or more sometimes negates the fast settling time of the spec sheet. A test setup for this worst-case measurement is shown in Figure 1. Two pulse generators are used to generate the required out-of-phase pulses, and the delays are adjusted for minimum skew. Figure 2 is an unretouched photo of the oscilloscope trance of an MDS-81S under test. MDS.O.'S Figure 1. HGH SPEEO TTllOGCGATES OR NVERTERS SUCH AS'.H04 OR TYPE EXT. TRG OSCillOSCOPE O/A S ~~ -

OBSOLETE ~ ANALOG W DEVICES HAS-0802/1002/1202 I. Ultra-FastHybrid Analogto-DigitalConverters

OBSOLETE ~ ANALOG W DEVICES HAS-0802/1002/1202 I. Ultra-FastHybrid Analogto-DigitalConverters W DEVCES Ultra-FastHybrid Analogto-DigitalConverters FEA TURES Conversion Times as Low as 1.2.ts Resolution: 8, 10 and 12 Bits Exceptional Accuracy, 0.012% of F.S. Low Power Contained in Glass or Metal