Power Supply Input Signal Level Power Dissipation Ceramic Package: 0.01 Hz to 300 khz 4.5V to 20V. Plastic Package:

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Erick Paul
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XR 2211 FSK Dell1odulator/Tone Decoder The XR-22ll is a monolithic phase-locked loop (PLL) system especially designed for data communications. t is particularly well suited for FSK modem applications.

1 XR 2211 FSK Dell1odulator/Tone Decoder The XR-22ll is a monolithic phase-locked loop (PLL) system especially designed for data communications. t is particularly well suited for FSK modem applications. t operates over a wide supply voltage range of 4.5 to 20V and a wide frequency range of 0.01 Hz to 300 khz. t can accommodate analog signals between 2 mv and 3V, and can interface with conventional DTL, TTL and ECL logic families. The circuit consists of a basic PLL for tracking an input signal within the pass band, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set center frequency, bandwidth, and output delay. Wide Frequency Range Wide Supply Voltage Range DTL/TTL/ECL Logic Compatibility FSK Demodulation, with Carrier-Detection Wide Dynamic Range Adjustable Tracking Range (± 1% to ±80%) Excellent Temp. Stability 0.01 Hz to 300 khz 4.5V to 20V Power Supply nput Signal Level Power Dissipation Ceramic Package: Derate above T A = +25 C Plastic Package: Derate above T A = +25 C 20V 3Vrms 750 mw 6mVtC 625 mw 5.0mWtC FSK Demodulation Data Synchronization Tone Decoding FM Detection Carrier Detection Part Number XR M XR-22llCN XR-22lCP XR-2211N XR-2211P Package Ceramic Ceramic Plastic Ceramic Plastic Operating Temperature -55 C to +125 C O C to +75 C O C to +75 C _40 C to +85 C - 40 C to +85 C 1TMNG CAPACTOR J r LOCK 0 OETECT OUTPUTS L Q LOOP.-OET. OUT. REF. VOLTAGE OUT.

ELECTRCAL CHARACTERSTCS Test Conditions: V+ = +12V, TA = +25 C, R O = 30 Kil, Co = 0.033 JlF. See Fig. 2 for component designation XR-2211/2211M XR-2211C CHARACTERSTCS UNTS CONDTONS MN. TYP. MAX.

2 ELECTRCAL CHARACTERSTCS Test Conditions: V+ = +12V, TA = +25 C, R O = 30 Kil, Co = JlF. See Fig. 2 for component designation XR-2211/2211M XR-2211C CHARACTERSTCS UNTS CONDTONS MN. TYP. MAX. MN. TYP. MAX. GENERAL Supply Voltage V Supply Current ma Ro L 10 Kil. See Fig. 4 OSCLLATOR SECTON Frequency Accuracy Frequency Stability ±1 ±3 ±1 % Deviation from fo = /ROCO Rl = 00 Temperature ±20 ±50 ±20 ppmfc See Fig. 8. Power Supply %fv V+ = 12 ± 1V. See Fig %fv V+ = 5 ± 0.5V. See Fig. 7. Upper Frequency Limit khz RO = 8.2 Kil, Co = 400 pf Lowest Practical Operating Frequency Hz RO = 2 Mil, Co = 50 JlF Timing Resistor, RO See Fig. 5. Operating Range Kil Recommended Range Kil See Fig. 7 and 8. LOOP PHASE DETECTOR SECTON Peak Output Current ±150 ±200 ±300 ±100 ±200 ±300 JlA Measured at Pin 11. Output Offset Current ±1 ±2 JlA Output mpedance 1 1 Mil Maximum Swing ±4 ±5 ±4 ±5 V Referenced to Pin 10. QUADRATURE PHASE DETECTOR Measured at Pin 3. Peak Output Current JlA Output mpedance 1 1 Mil Maximum Swing Vpp NPUT PREAMP SECTON Measured at Pin 2. nput mpedance Kil nput Signal Voltage Required to Cause Limiting mv rms VOLTAGE COMPARATOR SECTONS nput mpedance 2 2 Mil Measured at Pins 3 and 8. nput Bias Current na Voltage Gain db RL = 5.1 Kil Output Voltage Low mv e = 3 ma Output Leakage Current JlA Vo = 12V NTERNAL REFERENCE Voltage Level V Measured at Pin 10. Output mpedance il Figure 1. Functional Block Diagram of a Tone and FSK Decoding System Using XR-22 1.

$r-------- - -,----------T--------------- -,-------, 1. 1 1,,. 1.'''''',0 1 :c.1 1 m., 3 1 :TlCT 1 : 1 5 1 1 L -1- -1. -1. J NT(lNAL VOt.TAOf Nf'\lT'fAW\.$

3 r , T , , ,,. 1.'''''',0 1 :c.1 1 m., 3 1 :TlCT 1 : L J NT(lNAL VOt.TAOf Nf'\lT'fAW\.FR OUAOflATU'U LOCl(TlCT lefullencf NfO lmtttl PMAl OlTlCTOR ex-'a.tol r , , ,.-J RESSTOR.1..1 J VOLrAGE CONTROLLED L()()f' PMAa O(TlCTOfl Flit cc:.f'''''''' TOl OSCilLATOR ''. C 15 E ' - i>q RO/,.: ',./ ffi a: ;;:, a: i> 0+) :> kk: ''. t.... ' iil V 6. :, N:+).... ' ' ' ROi'T -- } - - 1\ J-it= 1000 '- \.. i> '\f!... ) - q,,_ C',. o A' ' r--.. ' i> +Q a 100 ',./ J' 0 >- v o. a: '- 0, o.... <9 0 +) * _ O.<? A' , SUPPLY VOLTAGE, V+ (VOLTS) 1 0 1Hz) lolhl1 Figure 4. Typical Supply Current vs Y+ Figure 5. YCO Frequency vs Timing Figure 6. YCO Frequency vs Timing (Logic Outputs Open Circuited). Resistor Capacitor ' 1.02.,0 fo khz 6 :. 6 V : 1.01 >-!!././ J...- )(... '0.5 - ii :> >- RO'50K VK :: ( V ffi :> K ::; 0. S 7 :: -::::::: { V - c CURVE J 0 ROY r-- a: 1 6K 0. ::; 3 C o,.rn V+ 12V J ( 4 look a: R,.1OR O 8 300K 0 z '0.1 khz R:;' 10RO U 1'\.0 10K. 4 ffi,.-- i 2 10K.. 5 V+CVOlTS) TEMPERATURE (C Figure 7. Typical f O vs Power Supply Characteristics. Figure 8. Typical Center Frequency Drift vs Temperature

Signal nput (Pin 2): Signal is ac coupled to this terminal. The internal impedance at Pin 2 is 20 Kn. Recommended input signal level is in the range of 10 mvrms to 3 Vrms.

4 Signal nput (Pin 2): Signal is ac coupled to this terminal. The internal impedance at Pin 2 is 20 Kn. Recommended input signal level is in the range of 10 mvrms to 3 Vrms. Quadrature Phase Detector Output (Pin 3): This is the highimpedance output of quadrature phase detector, and is internally connected to the input of lock-detect voltage-comparator. n tone detection applications, Pin 3 is connected to ground through a parallel combination of RD and CD (See Fig. 2) to eliminate the chatter at lock-detect outputs. f the tonedetect section is not used, Pin 3 can be left open circuited. Lock-Detect Output, Q (Pin 5): The output at Pin 5 is at high state when the PLL is out of lock and goes to low or conducting state when the PLL is locked. t is an opencollector type output and requires a pull-up resistor, RL, to V+ for proper operation. At low state, it can sink up to 5 ma of load current. Lock-Detect Complement, Q (Pin 6): The output at Pin 6 is the logic complement of the lock-detect output at Pin 5. This output is also an open-collector type stage which can sink 5 ma of load current at low or on state. FSK Data Output (Pin 7): This output is an open-collector logic stage which requires a pull-up resistor, R L, to V+ for proper operation. t can sink 5 ma of load current. When decoding FSK signals, FSK data output is at high or off state for low input frequency; and at low or on state for high input frequency. f no input signal is present, the logic state at Pin 7 is indeterminate. FSK Comparator nput (Pin 8): This is the high-impedance input to the FSK voltage comparator. Normally, an FSK postdetection or data filter is connected between this terminal and the PLL phase-detector output (Pin ). This data filter is formed by RF and CF of Fig. 2. The threshold voltage of the comparator is set by the internal reference voltage, V R' available at Pin 10. Reference Voltage, YR (Pin 10): This pin is internally biased at the reference voltage level, V R : V R = V+/2-650 my. The dc voltage level at this pin forms an internal reference for the voltage levels at pins 5, 8, and 12. Pin 10 must be bypassed to ground with a 0.1 p.f capacitor, for proper operation of the circuit. Th15 terminal is a low-impedance point, and is internally biased at a dc level equal to YR' The maximum timing current drawn from Pin 12 must be limited to 3 ma for proper operation of the circuit. YCO Timing Capacitor (Pins 13 and 14): vca frequency is inversely proportional to the external timing capacitor, CO' connected across these terminals (See Fig. 5). Co must be non-polar, and in the range of 200 pf to 10 p.f. VCO Frequency Adjustment: vca can be fine-tuned by connecting a potentiometer, R X, in series with RO at Pin 12 (See Fig. 9). YCO Free-Running Frequency, fo: XR-2211 does not have a separate vca output terminal. nstead, the vca ou tputs are internally connected to the phase-detector sections of the circuit. However, for set-up or adjustment purposes, vca free-running frequency can be measured at Pin 3 (with CD disconnected), with no input and with Pin 2 shorted to Pin 10. DESGN EQUATONS (See Fig. 2 for Definition 1. vca Center Frequency, f O : fo = /ROCO Hz of Components) 2. nternal Reference Voltage, V R (measured at Pin 10) V R = V+/2-650 mv 3. Loop Low-Pass Filter Time Constant, T: T = R C 4. Loop Damping,: = 1/4 jc o C 5. Loop Tracking Bandwidth, ±t:j.f/fo: t:j.f/fo = RO/R Loop Phase Detector Output (Pin 11): This terminal provides a high-impedance output for the loop phase-detector. The PLL loop filter is formed by R and C connected to Pin (See Fig. 2). With no input signal, or with no phase-error within the PLL, the dc level at Pin is very nearly equal to V R' The peak voltage swing available at the phase detector output is equal to ±V R. YCO Control nput (Pin 12): vca free-running frequency is determined by external timing resistor, R O ' connected from this terminal to ground. The vca free-running frequency, fo' is: 6. FSK Data Filter Time Constant, TF: TF = RFCF 7. Loop Phase Detector Conversion Gain, Kcb: (Kcb is the differential de voltage across Pins 10 and 11, per unit of phase error at phase-detector input) Ktj> = - 2V R/1T volts/radian 8. vca Conversion Gain, K O : (KO is the amount of change in vca frequency, per unit of (e voltage change at Pin ): KO = -lfvrcor 1 Hz/volt 9. Total Loop Gain, KT: KT = 21TKtj>KO = 4/COR rad/sec/volt where Co is the timing capacitor across Pins 13 and 14. For optimum temperature stability, RO must be in the range of 10 Kn to 100 Kn (See Fig. 8). 10. Peak Phase-Detector Current, A: A = VR (volts)/25 ma

5 APPLCATONS FSK DECODNG: NFORMATON Figure 9 shows the basic circuit connection for FSK decoding. With reference to Figures 2 and 9, the functions of external components are defined as follows: RO and Co set the PLL center frequency, R sets the system bandwidth, and C sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for the FSK data output. The resistor RB (= 510 Kn) from Pin 7 to Pin 8 introduces positive feedback across FSK comparator to facilitate rapid transition between output logic states. Recommended component values for some of the most commonly used FSK bands are given in Table. Design Example: 75 Baud FSK demodulator with mark/space frequencies of 1110/1170 Hz: Step : Calculate fo: fo = ( ) (1/2) = 1140 Hz Step 2: Choose RO = 20 Kn (18 Kn fixed resistor in series with 5 Kn potentiometer) Step 3: Calculate Co from Fig. 6: Co = pf Step 4: Calculate R : R = R O (2240/60) = 380 Kn Step 5: Calculate C: C = CO/4 = pf Note: All values except R O can be rounded-off to nearest standard value. FSK BAND COMPONENT VALUES A O 5 Kn A, AX vco FNE TUNE 300 Baud Co = pf CF = pf f l = 1070 Hz C = 0.01 pf R O = 18 Kn f2 = 1270 Hz R = 100 Kn 300 Baud Co = pf CF = pf f l = 2025 Hz C = pf R O = 18 Kn f2 = 2225 Hz R = 200 Kn c, -= Baud Co = pf CF = pf f l = 1200 Hz C = 0.01 pf R O = 18 Kn - 2 = 2200 Hz R =30Kn Recommended Component Values for Commonly Used FSK Bands (See Circuit of Fig. 9) Oesign nstructions: The circuit of Fig. 9 can be tailored for any FSK decoding application by the choice of five key circuit components: RO, R, CO' C and CF For a given set of FSK mark and space frequencies, f and f2, these parameters can pe calculated as follows: a) Calculate PLL center frequency, fo: fl + f2 fo= -- 2 b) Choose value of timing resistor R O, to be in the range of 10 Kn to 100 Kn. This choice is arbitrary. The recommended value is R O '=' 20 Kn. The final value of RO is normally fine-tuned with the series potentiometer, R X- c) Calculate value of Co from design equation () or from Fig. 6: Co = /ROfO d) Calculate R to give a f equal to the mark-space deviation: R = RO (fo/(fl - f2)] e) Calculate C to set loop damping. (See Design Equation No.4). Normally, ' 1/2 is recommended. Then: C = CO/4 for = 1/2 f) Calculate Data Filter Capacitance, CF: For RF = 100 Kn, RB = 510 Kn, the recommended value of CF is: CF ' 3/(Baud Rate) pf Note: All calculated component values except R O can be rounded-off to the nearest standard value, and R O can be varied to fine-tune center frequency, through a series potentiometer, RX. (See Fig. 9). FSK DECODNG WTH CARRER-DETECT: The lock-detect section of XR-2211 can be used as a carrierdetect option, for FSK decoding. The recommended circuit connection for this application is shown in Fig. 10. The open-collector lock-detect output, Pin 6, is shorted to data. output (Pin 7). Thus, data output will be disabled at low state, until there is a carrier within the detection band of the PPL, and the Pin 6 output goes high, to enable the data output. The minimum value of the lock-detect filter capacitance CD is inversely proportional to the capture range, ±fc. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. t is further limited by C. For most applications, fc > f/2. For R D = 470 Kn, the approximate minimum value of CD can be determined by: CD (pf) 16/capture range in Hz. Figure 10. External Connectors for FSK Demodulation with Carrier-Detect Capability. Note: Data Output is Low When No Carrier is Present.

With values of CD that are too small, chatter can be observed on the lock-detect output as an incoming signal frequency approaches the capture bandwidth.

6 With values of CD that are too small, chatter can be observed on the lock-detect output as an incoming signal frequency approaches the capture bandwidth. Excessively-large values of CD will slow the response time of the lock-detect output. TONE DETECTON: Figure shows the generalized circt connection for tone detection. The logic outputs, Q and Q at Pins 5 and 6 are normally at high and low logic states, respectively. When a tone is present within the detection band of the PLL, the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5 ma of load current. Both logic outputs at Pins 5 and 6 are open-collector type stages, and require external pull-up resistors RLl and RL2, as shown in Fig.. With reference to Figs. 2 and, the (unctions of the external circuit components can be explained as follows: R O and Co set VCO center frequency; R sets the detection bandwidth; C sets the low pass-loop filter time constant and the loop damping factor. RLl nd RL2 are the respective pull-up resistors for the Q and Q logic outputs. Design Examples: Tone detector with a detection band of khz ± 20 Hz: a) Choose RO= 20 K11(18 K11in series with 5 K11 potentiometer). b) Choose Co for fo= khz: From Fig. 6: Co = 0.05 JF. c) Calculate Rf R = (RO)(1000/20) = Mil. d) Calculate C: for t = 1/2, C = 0.25, Co = JF. e) Calculate C.D:CD = 16/38 = 0.42JF. f) Fine-tune center frequency with 5 Kil potentiometer, RX' ADJUSTMENT PROCEDURE With the input open-circuited, the loop phase detector output voltage is essentially undefined and VCO frequency may be anywhere within the lock range. There are several ways that fo can be monitored:. Short pin 2 to pin 10 and measure foat pin 3 with CD disconnected; 2. Open R and monitor pin 13 or 14 with a high-impedance probe; or 3. Remove the resistor between pins 7 and 8 and find the input frequency at which the FSK output changes state. NOTE: Do NOT adjust the center frequency of the XR by monitoring the timing capacitor frequency v'ith everything connected and no input signal applied. LOGC OUTPUT 0 -l LOGC OUTPUT.to R O '2 -=- Design nstructions: The circuit of Fig. can be optimized for any tone-detection application by the choice of the 5 key circuit components: RO, R, CO' C and CD' For a given input the tone frequency, fs' these parameters are calculated as follows: a) Choose ROto be in the range of 15 Kil. to 100 Kil. This choice is arbitrary. b) Calculate Co to set center frequency, fo equal to fs: (See Fig. 6). Co = /ROfS c) Calculate R to set bandwidth ±f: (see design Equation No.5): R = RO(fO/f) Note: The total detection bandwidth covers the frequency range of fo ± f. d) Calculate value of C for a given loop damping factor: C = CO/16t 2 Normally t :::::: 112 is optimum for most tone-detector applications, giving C = 0.25 CO, ncreasing C improves the out-of-band signal rejection, but increases the PLL capture time. e) Calculate value of filter capacitor CD' To avoid 'chatter at the logic output, with RD = 470 Kil, CD must be: CD(.uF) (6/capture range in Hz) ncreasing CD slows down the logic output response time. -=- R 1 RF V+ '00 Kn c, -=- Figure 12. Linear FM Detector Using XR-2211 and an External Op. Amp. (See section on Design Equations, for Component Values) LNEAR FM DETECTON: XR-2211 can be used as a linear FM detector for a wide range of analog communications and telemetry applications. The recommended circuit connection for this application is shown in Fig. 12. The demodulated output is taken from the loop phase detector output (Pin ), through a post detection filter made up of RF and CF, and an external buffer amplifier. This buffer amplifier is necessary because of the high impedance output at Pin. Normally, a non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Fig. 12. The FM detector gain, i.e., the output voltage change per unit of FM deviation, can be given as: Vout = R VR/l 00 R O Volts/%deviation where VR is the internal reference voltage. (VR = V+/2-650 mv). For the choice of external components R, Ro, CD, C and CF, see section on Design Equations.

FSK DEMODULATOR / TONE DECODER

FSK DEMODULATOR / TONE DECODER GENERAL DESCRIPTION The is a monolithic phase-locked loop (PLL) system especially designed for data communications. It is particularly well suited for FSK modem applications,