UNISONIC TECHNOLOGIES CO., LTD

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1 UNISONIC TECHNOLOGIES CO., LTD PHASE LOCKED LOOP WITH CO DESCRIPTION The U74HC4046A is a phase-locked-loop circuit including a linear voltage-controlled oscillator (CO), three different phase comparators (PC1, PC and PC3), a common signal input amplifier and a common SOP-16 comparator input. The signal can be directly coupled to large voltage signals or with a series capacitor coupled to small voltage signals. Small voltage signals can be kept within the linear region of the input amplifiers with a self-bias input circuit. The U74HC4046A and a passive low-pass filter form a second-order loop PLL. With a linear op-amp, the CO achieves excellent linearity. The CO requires an external capacitor and resistor. R1 (between R1 TSSOP-16 and GND) and capacitor C1 (between C1A and C1B) determine the frequency range of the CO. R (between R and GND) enables the CO to have a frequency offset if required. For the high input impedance of the CO, the design of low-pass filters is simplified, and the designer has a wide choice of resistor/capacitor ranges. At pin 10 (DEM OUT ), a demodulator output of the CO input voltage is provided in order not to load the low-pass filter. In conventional techniques, the DEM OUT voltage is one threshold voltage lower than the CO input voltage, but the DEM OUT voltage of U74HC4046 equals the CO input voltage. When DEM OUT is used, a load resistor (RS) should be connected from DEM OUT to GND; but if unused, DEM OUT should be left open. The CO output (CO OUT ) can be connected directly or via a frequency-divider to the comparator input (COMP IN ). If the CO input is held at a constant DC level, the CO output signal has a duty factor of 50% (maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the CO and demodulator, while a HIGH level turns both off to minimize standby power consumption. FEATURES * Low Power Consumption * Operating Power Supply oltage Range: Digital Section.0 to 6.0 CO Section 3.0 to 6.0 * Up to 17 MHz (typ.) Centre Frequency at CC = 4.5 * Excellent CO Frequency Linearity * CO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption * Minimal Frequency Drift * Three Phase Comparators: EXCLUSIE-OR; Edge-Triggered JK Flip-Flop; Edge-Triggered RS Flip-Flop * Zero oltage Offset due to OP-Amp Buffering * Standard Output Capability * MSI I CC Category 1 of 19 Copyright 013 Unisonic Technologies Co., Ltd

2 ORDERING INFORMATION Ordering Number Lead Free Halogen Free Package Packing U74HC4046AL-S16-R U74HC4046AG-S16-R SOP-16 Tape Reel U74HC4046AL-P16-R U74HC4046AG-P16-R TSSOP-16 Tape Reel UNISONIC TECHNOLOGIES CO., LTD of 19

3 PIN CONFIGURATION PCP OUT 1 16 CC PC1 OUT 15 PC3 OUT COMP IN 3 14 SIG IN CO OUT 4 13 PC OUT INH 5 1 R C1A 6 11 R1 C1B 7 10 DEM OUT GND 8 9 CO IN LOGIC SYMBOL IEC SYMBOL UNISONIC TECHNOLOGIES CO., LTD 3 of 19

4 PIN DESCRIPTION PIN NO SYMBOL FUNCTION 1 PCP OUT Phase comparator pulse output PC1 OUT Phase comparator 1output 3 COMP IN Comparator input 4 CO OUT CO output 5 INH Inhibit input 6 C1 A Capacitor C1 connection A 7 C1 B Capacitor C1 connection B 8 GND Ground 9 CO IN CO input 10 DEM OUT Demodulator output 11 R1 Resistor R1 connection 1 R Resistor R connection 13 PC OUT Phase comparator output 14 SIG IN Signal input 15 PC3 OUT Phase comparator 3 output 16 CC Positive supply voltage UNISONIC TECHNOLOGIES CO., LTD 4 of 19

5 FUNCTIONAL DIAGRAM LOGIC DIAGRAM UNISONIC TECHNOLOGIES CO., LTD 5 of 19

6 ABSOLUTE MAXIMUM RATINGS DC Supply oltage CC DC Input Diode Current ±I IK for IN < 0.5 or IN > CC ma DC Output Diode Current ±I OK for OUT < 0.5 or OUT > CC ma DC Output Source or Sink Current ±I O for 0.5 < OUT < CC ma DC CC or GND Current ±I CC, ±I GND 50 ma Power Dissipation per Package for temperature range: 40 to +15 C 750 mw Plastic DIL above +70 C: derate linearly with 1 mw/k P D Power Dissipation per Package for temperature range: 40 to +15 C 500 mw Plastic Mini-Pack(SO) above +70 C: derate linearly with 8 mw/k Storage Temperature Range T STG C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. RECOMMENDED OPERATING CONDITIONS DC Supply oltage CC DC Supply oltage if CO Section is not used CC DC Input oltage Range IN 0 CC DC Output oltage Range OUT 0 CC CC = ns Input Rise and Fall Times (pin 5) t R, t F CC = ns CC = ns Ambient Operating Temperature T OPR see DC and AC CHARACTERISTICS QUICK REFERENCE DATA (GND = 5; T = 5 C) C C CO Centre Frequency f o C1 = 40 pf; R1 = 3 kω; CC = 5 19 MHz Input Capacitance (pin 5) C IN 3.5 pf Power Dissipation Capacitance per Package C PD (Note) 4 pf Note : C PD is used to determine the dynamic power dissipation (P D in μw): PD = CPD CC f i + (CL CC fo ) where: f i = input frequency in MHz; C L = output load capacitance in pf; CC = supply voltage in ; f o =output frequency in MHz; (CL CC f O ) = sum of outputs. UNISONIC TECHNOLOGIES CO., LTD 6 of 19

7 DC CHARACTERISTICS (T A =5 C, unless otherwise specified) Input Resistance (SIG IN, COMP IN ) R IN Quiescent Supply Current (oltages are referenced to GND (ground = 0 )) Pins 3, 5 and 14 at Quiescent Supply Current CC ; I (CO Disabled) CC CC =6.0 Pin 9 at GND; I IN at pins 3 and 14 to be excluded 8.0 μa Phase Comparator Section DC Coupled CC = (HIGH Level Input oltage SIG IN, IH CC = COMP IN ) CC = DC Coupled CC = (LOW Level Input oltage SIG IN, IL CC = COMP IN ) CC = CC = HIGH Level Output oltage I = IH or IL, OH CC = (PCP OUT, PC nout ) - I OUT = 0μA CC = HIGH Level Output oltage CC =4.5, - I O = 4.0 ma OH I = IH or IL, (PCP OUT, PC nout) CC =6.0,- I O = 5. ma CC = LOW Level Output oltage I = IH or IL, OL CC = (PCP OUT, PC nout ) - I OUT = 0μA CC = LOW Level Output oltage OL CC =4.5, I O = 4.0 ma I = IH or IL, (PCP OUT, PC nout ) CC =6.0, I O = 5. ma CC = Input Leakage Current I = CC or CC = ±I IN (SIG IN, COMP IN ) GND CC = μa CC = State (OFF-state current PC OUT ) ±I OZ OUT = CC or GND, I = IH or IL, CC = μa CC =4.5 point; Δ I = 0.5; 50 kω CC =3.0 IN at self-bias operating 800 kω CC =6.0 (Fig. 7) 150 kω LOW Level Input oltage INH IL CO Section (oltages are Referenced to GND (Ground = 0 )) HIGH Level Input oltage INH IH CC = CC = CC = CC = CC = CC = HIGH Level Output oltage CO OUT OH CC = I = IH or IL, CC = I OUT = 0μA CC = CC =4.5, -I OUT = 4.0 ma HIGH Level Output oltage CO OUT OH I = IH or IL CC =6.0, -I OUT = 5. ma LOW Level Output oltage CO OUT OL CC = I = IH or IL, CC = I OUT = 0μA CC = CC =4.5, I OUT = 4.0 ma LOW Level Output oltage CO OUT OL I = IH or IL CC =6.0, I OUT = 5. ma CC =4.5, I OUT = 4.0 ma 0.4 LOW Level Output oltage C1 A, C1 B OL I = IH or IL CC =6.0, I OUT =5. ma 0.4 Input Leakage Current(INH, CO IN ) ±I IN CC =6.0, I = CC or GND 0.1 μa UNISONIC TECHNOLOGIES CO., LTD 7 of 19

8 DC CHARACTERISTICS(Cont.) CO Section (Cont.) CC = R1 CC = kω Resistance Range CC = CC = R CC =4.5 (Note) kω CC = CC = Capacitor Range C1 CC = pf CC = CC =4.5 specified for R1; CC =3.0 Over the range CC =6.0 for linearity (Fig10) Note: The parallel value of R1 and R should be more than.7 kω. Optimum performance is achieved when R1 and/ or R are/is > 10 kω. Resistor Range R S Offset oltage CO IN to DEMOUT OFF Demodulator Section (oltages are Referenced to GND (Ground = 0 )) CC =4.5 the leakage current can kω CC =3.0 At R S > 300 kω CC =6.0 influence DEMOUT CC =4.5 values taken over R S ±0 m CC =3.0 I = COIN =1/ CC ; ±30 CC =6.0 range ±10 CC =3.0 5 Dynamic Output Resistance at R D CC =4.5 DEMOUT = 1/ CC 5 DEM OUT CC =6.0 5 Ω UNISONIC TECHNOLOGIES CO., LTD 8 of 19

9 AC CHARACTERISTICS (T A =5 C, unless otherwise specified) Output Transition Time t PHZ / t PLZ Phase Comparator Section (GND = 0 ; t R = t F =6ns; C L = 50pF) CC = Propagation Delay SIG IN, t PHL / t PLH CC =4.5 Fig COMP IN to PCP OUT CC = ns CC = ns Propagation Delay SIG IN, t PHL / t PLH CC =4.5 Fig COMP IN to PC3 OUT CC = CC = State Output Enable Time t PZH / t PZL CC =4.5 Fig SIG IN, COMP IN to PC OUT CC = ns CC = State Output Disable Time t PHZ / t PLZ CC =4.5 Fig SIG IN, COMP IN to PC OUT CC = ns CC =4.5 Fig ns CC = CC = CC =.0 9 AC Coupled Input Sensitivity CC = (Peak-To-Peak alue) IN(P-P) f i = 1MHz CC = at SIG IN or COMP IN CC = m CO Section (GND = 0 ; t R = t F = 6 ns; C L = 50 pf) CC =3.0 IN = COIN = 1/ CC ; Frequency Stability with Δf/T CC =4.5 R1 = 100 kω; R = ; Temperature Change CC =6.0 C1= 100 pf %/K CC =3.0 COIN = 1/ CC ; CO Centre Frequency f o CC =4.5 R1 = 3 kω;r = ; (duty Factor = 50%) CC =6.0 C1 = 40 pf MHz CO Frequency Linearity Δf CO CC = R1 = 100 kω; R = ; CC = C1 = 100 pf;(fig.10) CC = % CC = Duty Factor at CO OUT δ CO CC = % CC = UNISONIC TECHNOLOGIES CO., LTD 9 of 19

10 PHASE COMPARATORS If the signal swing is between the standard HC family input logic levels, the signal input (SIG IN ) can be directly coupled to the self-biasing amplifier at pin 14. Capacitive coupling is required for signals with smaller swings. Phase comparator 1 (PC1) This is an EXCLUSIE-OR network. To obtain the maximum locking range, the signal and comparator input frequencies (f I ) must have a 50% duty factor. The transfer characteristic of PC1, assuming ripple (f r = f i ) is suppressed, is: CC DEMOUT = ( φsigin φcompin ) π Where DEMOUT is the demodulator output at pin 10; DEMOUT = PC1OUT (via low-pass filter). The phase comparator gain is: CC K P = ( / r ) π As shown in Fig.1, the average output voltage from PC1, fed to the CO input via the low-pass filter and seen at the demodulator output at pin 10 ( DEMOUT ) is the resultant of the phase differences of signals (SIG IN ) and the comparator input (COMP IN ). The average of DEMOUT is equal to CC / when there is no signal or noise at SIG IN and with this input the CO oscillates at the centre frequency (f O ). As shown in Fig. it is the typical waveforms for the PC1 loop locked at f O. π Fig.1 Phase comparator 1: average output voltage versus input phase difference. SIG IN COMP IN CO OUT PC1 OUT CO IN CC GND Fig. Typical waveforms for PLL using phase comparator 1, loop locked at f O. The frequency capture range (f c ) is he frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (f L ) is the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the low-pass filter characteristics determine the capture range which can be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the CO centre frequency. UNISONIC TECHNOLOGIES CO., LTD 10 of 19

11 PHASE COMPARATORS (Cont.) Phase comparator (PC) This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. PC is comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down counter (Logic Diagram) for SIG IN causes an up-count and COMP IN causes a down-count. The transfer function of PC, assuming ripple (f r = f i ) is suppressed, is CC DEMOUT = ( φsigin φcompin ) 4π where DEMOUT is the demodulator output at pin 10; DEMOUT = PCOUT (via low-pass filter). The phase comparator gain is: CC KP = ( / r ) 4π As shown in Fig.3, DEMOUT is the resultant of the initial phase differences of SIG IN and COMP IN. Typical waveforms for the PC loop locked at f o are shown in Fig.4. 4π Fig.3 Phase comparator : average output voltage versus input phase difference. Fig.4 Typical waveforms for PLL using phase comparator, loop locked at f o. If the frequencies of SIG IN and COMP IN are equal but the phase of SIG IN leads that of COMP IN, the p-type output driver at PC OUT is held ON for a time corresponding to the phase difference (φ DEMOUT ). If the phase of SIG IN lags that of COMP IN, the n-type driver is held ON. If the frequency of SIG IN is higher than that of COMP IN, the p-type output driver is held ON for most of the input signal cycle time, and for the remainder of the cycle both n and p-type drivers are OFF (3-state). If the frequency of SIG IN is lower than that of COMP IN, the n-type driver that is held ON for most of the cycle. Then the voltage at the capacitor (C) of the low-pass filter connected to PC OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable state the voltage on C remains constant as the PC output is in 3-state and the CO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator pulse output (PCP OUT ) is a HIGH level, and it indicates a locked condition. For PC, there is no phase difference between SIG IN and COMP IN over the full frequency range of the CO. And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and this is independent of the low-pass filter. The CO adjusts to its lowest frequency via PC when no signal present at SIG IN. UNISONIC TECHNOLOGIES CO., LTD 11 of 19

12 PHASE COMPARATORS (Cont.) Phase comparator 3 (PC3) This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. If this comparator is used, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. The transfer characteristic of PC3, assuming ripple (f r = f j ) is suppressed, is: CC DEMOUT = ( φsigin φcompin ) π where DEMOUT = PC3OUT (via low-pass filter). The phase comparator gain is: CC K P = ( / r ) π As shown in Fig.5, the average output voltage from PC3, fed to the low-pass filter and seen at the demodulator output at pin 10 ( DEMOUT ), is the resultant of the phase differences of SIG IN and COMP IN. As shown in Fig.6, it is the typical waveforms for the PC3 loop locked at f o. CC DEMOUT (A) DEMOUT = PC3OUT = DEMOUT = ( SIGIN - 1/ CC CC ( SIGIN - COMPIN) π 0 COMPIN) DEMOUT Fig.5 Phase comparator 3: average output voltage versus input phase difference. Fig.6 Typical waveforms for PLL using phase comparator 3, loop locked at f o. The phase-to-output response characteristic of PC3 (Fig.5) differs from that of PC, as the phase angle between SIG IN and COMP IN varies between 0 o and 360 o and 180 o is the centre frequency. And the voltage swing of PC3 is greater than that of PC for input phase differences, but as a consequence the ripple content of CO input signal is higher. Both of the PLL lock range and capture range of this type of phase comparator are dependent on the low-pass filter. The CO adjusts to its lowest frequency via PC3, when no signal present at SIG IN. UNISONIC TECHNOLOGIES CO., LTD 1 of 19

13 FIGURE REFERENCES FOR DC CHARACTERISTICS I IN IN IN Self-Bias Operating Point Fig.7 Typical input resistance curve at SIG IN, COMP IN. UNISONIC TECHNOLOGIES CO., LTD 13 of 19

14 AC WAEFORMS SIG IN, COMP IN M PCP OUT PC1 OUT PC3 OUT t PHL t PLH M M = 50%, H = 90%, L = 10% t THL t TLH Fig.8 Waveforms showing input (SIG IN, COMP IN ) to output (PCP OUT, PC1 OUT, PC3 OUT ) propagation delays and the output transition times. Fig.9 Waveforms showing the 3-state enable and disable times for PC OUT. Fig.10 Definition of CO frequency linearity: = 0.5 over the CC range: For CO linearity f 0 = (f 1 +f )/, linearity (f 0 +f 0 )/f 0 100% UNISONIC TECHNOLOGIES CO., LTD 14 of 19

15 APPLICATION INFORMATION This is a reference for the values of external components to be used with the U74HC4046A in a PLL system. The ranges of the values of the components: Component R1 R R1+R C1 alue 3 kω ~ 300 kω 3 kω ~ 300 kωd Parallel value >.7 kω Greater than 40 pf CO Frequency Without Extra Offset (Phase comparator: PC1, PC or PC3) Frequency Characteristic: With R = and R1 between 3 kω and 300 kω, the characteristics of the CO operation will be as shown in Fig.11 (Due to R1, C1 time constant a small offset remains when R = ). Fig.11 Frequency characteristic of CO operating without offset: f 0 = centre frequency; f L = frequency lock range. UNISONIC TECHNOLOGIES CO., LTD 15 of 19

16 APPLICATION INFORMATION(Cont.) CO Frequency with Extra Offset (Phase Comparator: PC1, PC or PC3) Frequency characteristic: With R1 and R between 3 kω and 300 kω, the characteristics of the CO operation will be as shown in Fig.1. f CO f MAX f 0 f L due to R1, C1 f MIN f OFF due to R, C1 0.9 ½ CC CC 0.9 CC CO IN Fig.1 Frequency characteristic of CO operating with offset: f 0 = centre frequency; f L = frequency lock range. PC1, PC or PC3 Selection of R1, R and C1 Given f o and f L, determine the value of R1 C1 Calculate f OFF from the equation f OFF = f O 1.6f L Obtain the values of C1 and R Calculate the value of R1 from the value of C1 and R1 C1. Subject Phase comparator Design considerations PC1 CO adjusts to f o with φ DEMOUT = 90 and CONIN = 1/ CD (Fig.1). PLL Conditions with no PC CO adjusts to f o with φ DEMOUT = -360 and CONIN = min. (Fig.3). Signal at the SIG IN Input PC3 CO adjusts to f o with φ DEMOUT = -360 and CONIN = min. (Fig.5). UNISONIC TECHNOLOGIES CO., LTD 16 of 19

17 APPLICATION INFORMATION(Cont.) PLL Frequency Capture Range (Phase comparator: PC1, PC or PC3) Loop filter component selection F( jω ) ω τ A small capture range (f C ) is obtained if 1 fc π fl / τ π Fig.13 Simple loop filter for PLL without offset; R3 500 Ω. τ R3 INPUT (a) R4 C τ 1 = R3 C τ = R4 C τ 3 = (R3 + 4) C OUTPUT F( jω ) m 1/ τ 3 1/ τ ω (b) Amplitude Characteristic R4 m = R3 + R4 Fig.14 Simple loop filter for PLL with offset; R3 + R4 500 Ω. -1/ τ -1/ τ 3 (c) Pole-Zero Diagram Subject Phase comparator Design considerations PLL Locks on Harmonics at Centre Frequency PC1 or PC3 Yes PC No Noise Rejection at Signal Input PC1 High PC or PC3 Low PC1 f r = f i, large ripple content at φ DEMOUT = 90 AC Ripple Content when PLL is Locked PC f r = f i, small ripple content at φ DEMOUT = 0 PC3 f r = f i, large ripple content at φ DEMOUT = 180 UNISONIC TECHNOLOGIES CO., LTD 17 of 19

18 PLL DESIGN EXAMPLE The parameters of the frequency synthesizer in Fig.15: Output frequency: MHz to 3 MHz Frequency steps: 100kHz Settling time: 1ms Overshoot: < 0% The Open-Loop Gain is: Fig.15 Frequency Synthesizer. H ( s) G( s) = K p Kf Ko Kn Where: K p = phase comparator gain The programmable counter ratio K n can be found as follows: fout MHz NMin = = = 0 f 100kHz step K f = low-pass filter transfer gain K o = K v /s CO gain K n = 1/n divider ratio fout 3MHz NMax = = = 30 fstep 100kHz The CO is set by the values of R1, R and C1, R = 10 kω (adjustable). The values can be determined using the information in the section DESIGN CONSIDERATIONS. With f o =.5MHz and f L =500 khz this gives the following values ( CC = 5.0 ): R1 = 10 kω; R = 10 kω; C1 = 500 pf The CO gain is: fl π 1MHz K = = π ( 0.9) 3. CC 6 r / s / The gain of the phase comparator is: The transfer gain of the filter is given by: K CC = 4 π p = 0.4 / s 1+ τ S K f = 1+ ( τ + τ )S The characteristics equation is: 1 + H(S) G(S) = 0 1 Where: τ 1 = R3C and τ = R4C This results in: 1+ K p Kv K S + ( τ + τ ) 1 n τ Kp K v Kn S + ( τ + τ ) 1 = 0 The natural frequency ω n is defined as follows: ω = n K K p v K ( τ 1 + τ ) n Damping alue ζ is Defined as follows: 1 1+ K p Kv K ζ = ω ( τ + τ ) n 1 n τ UNISONIC TECHNOLOGIES CO., LTD 18 of 19

19 UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD 19 of 19