TOSHIBA MOS MEMORY PRODUCTS TMM20 I 6AP- I 0 BLOCK DIAGRAM ~,--- 0: UJ A, ~ ~ 0 f=> U UJ -::"" ~ ;: 0. A, v- A 7. ::f~ ~"I '""
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1 MOS MEMORY PRODUCTS 2,048 WORD x 8 BT STATC RAM TMM20 6AP-90 TMM20 6AP- 0 DESCRPTON TMM20 6AP- 2 TMM20 6AP- 5 The TMM2016AP is a 16,384 bits high speed and low power static random access memory organized as 2,048 words by 8 bits and operates from a single 5V supply. Toshiba's high performance device technology provides both high speed and low power features with a maximum access time of 90ns/100ns/ 120ns/150ns and maximum operating current of 80mA/65mA/65mA/65mA. When CS is a logical high, the device is placed in a low power standby mode in which maximum standby current is 7mA. Thus the TMM2016AP is most suitable for use in microcomputer peripheral memory where the low power applications are required. The TMM2016AP is fabricated with ion implanted N channel silicon gate MOS technology for high performance and high reliability. FEATURES Access Time and Current l Access Part Number Time (Max.1 J Operating Standby Current Current (Max. (Max.) TMM2016Ap 90 90ns SOmA 7mA TMM2016Ap l0 loons 65mA 7mA TMM2016AP ns 65mA 7mA 'TMiv12016AP ns 65mA 7mA Single 5V Power Supply Fully Static Operation Power Down Feature: CS Output Buffer Control: OE Three Stage Outputs All nputs and Outputs: Directly TTL Compatible nputs protected: All inputs have prtoection against static charge. PN CONNECTON Vee A, A8 As A9 A4 WE A3 DE AjO CS 1/0, 1/07 1/02 lio, 1/ GND 1/04 PN NAMES SYMBOL Ao A3 A4 A,o CS WE /O, /O, OE Vee GND NAME Column Address nputs Row Address nputs Chip Select nput Write Enable nput Data nput/output Output Enable nput Power (5V) Ground BLOCK DAGRAM A 4 v-,--- A 5 A, A 7 A, v- A 9 0- v- 0: 0 UJ U UJ 0 0 f=> -::"" ;: 0 0: u ::f " '"" MEMORY CELL ARRAY (128 x 16 x 8) Vee ----a GND 1t... 1/0 CRCUT... COLUMN DECODER ffff == 1111
2 MAXMUM RATNGS SYMBOL TEM RATNG UNT Vcc Power Supply Voltage V V'N, VOUT npul/output Voltage V Topr. Operating Temperature 0-70 c Tstg. Storage Temperature c Tsolder Soldering Temperature Time 260' 10 c. sec Po Power Dissipation (Ta 70 C) 1.0 W D.C. RECOMMENDED OPERATNG CONDTONS (Ta = 0-70 C) SYMBOL PARAMETER MN. TYP. MAX. UNT VH nput High Voltage Vcc +1.0 V V,L nput Low Voltage V Vcc Supply Voltage V D.C. CHARACTERSTCS (Ta = 0-70 C, Vee = 5.0V ± 10"10) SYMBOL PARAMETER CONDTONS MN. TYP. MAX. UNT,L nput Leakage Current V,N OV - 5.5V /1A VOH Output High Voltage lout -1.0mA V VOL Output Low Voltage lout 2.1mA V LO Output Leakage Current CS V,H orwe V,L or OE V'H, VOUT OV - 5.5V /1A ssp Peak Power-on Current CS Vcc, lout OmA ma ss Standby Current CS V'H, lout OmA ma CC1 Operating Current TMM20 16AP l 0/ 12/ 15 CS V'L, lout OmA ma CC2 Operating Current TMM2016AP 90 CS V'L, lout OmA ma CAPACTANCE* (Ta = 25 C, f = 1.0 MHz) i SYMBOL i PARAMETER CONDTONS MAX. UNT C'N nput Capacitance V,N A.C. Ground 5 pf COUT Output Capacitance V,N A.C. Ground 10 pf.. Note: This parameter is periodically sampled and is not 100% tested
3 A.C. CHARACTERSTCS (Ta = 0 70 C. Vee = 5V ± 10",{,) READ CYCLE MM201:O_ 16AP-10 jtmm2016ap-12 TMM2015AP-15 SYMBOL PARAMETER UNT M.N. MAX. MN. MAX. i MN. MAX. MN. MAX. trc Read Cycle Time ns tacc Address Access Time ns tco Chip Select Access Ti me ns toe Output Enable Time , - 55 ns Output Data Hold Time from toh Address Change ns tclz Output in Low-Z from CS ns tchz Output in High-Z from CS ns tolz Output in Low-Z from OE ns tohz Output in High-Z from OE ns tpu Chip Selection to Power Up Time - -b ns tpd ChipDeselection to Power Down Time ns WRTE CYCLE TMM2015AP-90 TMM2016AP-10 TMM2016AP-12 TMM2016AP-15 SYMBOLl PARAMETER UNT MN. MAX. MN. MAX. MN. MAX. MN. MAX_ f.--twc Write Cycle Time ns tcw Chip Selection to End of Write ns f.--- tas Address Set up Time ns f--.- twp Write Pulse Width ns --f----- Write Recovery Time twr a - a ns tos Data Set up Time ns toh Data Hold Time a ns twlz Output in Low-Z from WE ns - Output in High-Z from WE L - 50 ns A.C. TEST CONDTONS nput Pulse Leveis nput Rise and Fall Time o -3.5V 10 ns nput and Output Reference Le')els 1.5V Output Load 1 TTL Gate & CL loop F 79
4 TMNG WAVEFORMS (A) READ CYCLE [1] (1) RC ADDRESSES tacc \\\\\\\\\\ toe HGH MPEDANCE DOUT UNKNOWN toh OUTPUT DATA VALD to HZ ljllil HGH MPEDANCE WMN. (B) READ CYCLE [2](1)(21 Supply Current :::mnm"t UNKNOWN OUTPUT DATA VAllO (C) WRTE CYCLE [1] (31 twc ADDRESSES DOUT
5 (D) WRTE CYCLE [2]13) twe ADDRESSES DOUT Note: (1) The WE is high for read cycle. Device is continuously selected, CS = VL in read cycle [11. (2) All address are valid perior to or simultaneously with CS transistions. (3) A write occurs during the overlap of low CS and low WE. The tcw is specified as the time from the chip selection to end of write in write cycle, and the twp is specified as the overlap time of low CS and low WE. OE is allowed to be low or high level in write cycle. f the 6E is high, the output buffers remain in a high impedance state in this period. (4) f the CS low transistion occurs simultaneously with or latter to the WE low transition, the output buffers remain in a high impedance state in this period. (5) f the CS high transition occurs simultaneously with WE high transition, the output buffers remain in a high impedance state in this period. These parameters are specified as follows and measured by using the load shown in Fig. 1. (A) tclz, tolz, twlz.. (8) tchz, tohz. twhz.. Output Enable Time Output Disable Time (;S, OE r f-- l- A) HGH MPEDANCE SV O.lSV O.lSV 18) O.lSV GH MPEDANCE O.lSV 1.8Kn DOUTo---r----- CL =30pF r 1.0Kn Fig. 1 Output load condition for enable and disable time measurement. 81
6 OUTLNE DRAWNGS Unit: mm ::c:::] X 32.4 MAX ± ±O.15 «:; TYP. t::!:t 17.4 MAX. O.5±O.15 Note: Each lead pitch is 2.S4mm. All leads are located within O.25mm of their true longitudinal position with respect to No.1 and No, 24 leads. Note: Toshiba does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied, and Toshiba reserves the right, at any time without notice, to change said circuitry. Feb., 1983 Toshiba Corporation
UTRON UT K X 8 BIT LOW POWER CMOS SRAM
FEATURES GENERAL DESCRIPTION Access time : 35/70ns (max) Low power consumption: Operating : 60/40 ma (typical) Standby : 3mA (typical) normal ua (typical) L-version 1uA (typical) LL-version Single 5V power
Rev. No. History Issue Date Remark
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Revision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
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IDT CMOS Static RAM 1 Meg (256K x 4-Bit)
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HY62256A Series 32Kx8bit CMOS SRAM
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10/February/07, v.1.0 Alliance Memory Inc. Page 1 of 13
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* 1Mx32 SRAM 3.3V MODULE FEATURES Access Times of 17, 20, 25ns 4 lead, 2mm CQFP, (Package 511) Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx Commercial, Industrial and Military Temperature
Item Previous Current 8ns 110mA 80mA. 10ns 90mA 65mA 12ns 80mA 55mA 15ns 70mA 45mA 8ns 130mA 100mA
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Revision History No. History Draft Date Remark 0.1 Defined Target Spec. May 2003 Rev. 0.1 / Jan. 2005 1 Series 4 Banks x 4M x 16bits Synchronous DRAM DESCRIPTION The HY5V56D(L/S)FP is a 268,435,456bit
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc. CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: High-speed Address to Valid time Military: 12/15/20/25ns Commercial: 10/12/15/20/25ns (max.) High-speed
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
Part No. Clock Frequency Power Organization Interface Package. Normal. Low power
4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
BSI BH62UV8000. Ultra Low Power/High Speed CMOS SRAM 1M X 8 bit
FEATURES Wide low operation voltage : 1.65V ~ 3.6V Ultra low power consumption : = 3.0V = 2.0V High speed access time : -70 70ns at 1.V at 5 O C Ultra Low Power/High Speed CMOS SRAM 1M X bit Operation
Rev. No. History Issue Date Remark
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
Part No. Clock Frequency Power Organization Interface Package. Normal. Low power
4 Banks x 4M x 4Bit Synchronous DRAM DESCRIPTION The Hynix HY57V654020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
DECODER I/O DATA CONTROL CIRCUIT
1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation: 36 mw (typical) operating 12 µw (typical) CMOS standby TTL compatible
A426316B Series 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE.
64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
32M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 33,578,432-bit high-speed Static Random Access Memory organized as 4M(2M) words
IS62WV10248EALL/BLL IS65WV10248EALL/BLL. 1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating TTL compatible interface levels Single power supply
Auto refresh and self refresh refresh cycles / 64ms. Programmable CAS Latency ; 2, 3 Clocks
4 Banks x 1M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
Revision No. History Draft Date Remark. 0.1 Initial Draft Jan Preliminary. 1.0 Final Version Apr. 2007
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jan. 2007 Preliminary 1.0
SRAM AS5C K x 8 SRAM Ultra Low Power SRAM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATION FEATURES GENERAL DESCRIPTION
512K x 8 Ultra Low Power AVAILABLE AS MILITARY SPECIFICATION SMD 5962-95613 1,2 MIL STD-883 1 FEATURES Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) Fully Static, No
HY57V281620HC(L/S)T-S
4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
Revision No. History Draft Date Remark. 1.0 First Version Release Dec Corrected PIN ASSIGNMENT A12 to NC Jan. 2005
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 1.0 First Version Release Dec. 2004 1.1 1.
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
Revision No. History Draft Date Remark. 0.1 Initial Draft Jul Preliminary. 1.0 Release Aug. 2009
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jul. 2009 Preliminary 1.0
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
1Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 16 I/O 0 -I/O 7
1Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 8 bit N01L83W2A Overview The N01L83W2A is an integrated memory device containing a 1 Mbit Static Random Access Memory organized as 131,072 words by 8 bits.
Part No. Clock Frequency Power Organization Interface Package. Normal. 4Banks x 2Mbits x8. Low power
4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V658020A is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and