Course Summary. 3213: Digital Systems & Microprocessors: L#14_15

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1 Course Summary 1. Course overview 2. Intro to PICOBLAZE, C and Number systems and Boolean Algebra 3. Course overview with microprocessor MU0 (I) 4. Course overview with microprocessor MU0 (II) 5. Verilog HDL 6. Digital system components using schematics and Verilog 7. Combinational logic standard forms. Karnaugh maps 8. Combinational ccts and conﬁgurable logic devices 9. Simple Sequential circuits, ﬂip ﬂops 10. Sequential circuits, counters, registers, memories 11. Non ideal effects in digital circuits 12. Finite State Machines 13. Design of FSMs 14. Register Transfer Level Systems (RTL) systems 15. Design of RTL Systems 16. Non ideal effects in complex digital systems (Karnaugh maps) 17. Complex RTL design 18. The PICOBLAZE Softcore 19. Assembly language programming 20. C and Assembly 21. Other microprocessor architectures 3213: Digital Systems & Microprocessors: L#14_15

2 Exam Time Table Date: Monday 22 June 2009 Reading Time starts: 9.15 am Writing time starts: 9.30 am Writing time ends: pm Permitted materials: no permitted materials (except writing materials) Venue: to be advised in final timetable. 3213: Digital Systems & Microprocessors: L#14_15

3 Introduction Non ideal Effects: Switch debouncing, timing closure Examples RTL systems review 3213: Digital Systems & Microprocessors: L#14_15

4 Non Ideal Effects: Switch Debouncing

5 Non Ideal Effects: Switch Debouncing

6 Non Ideal Effects: Switch Debouncing

7 Non Ideal Effects: Switch Debouncing

8 Non Ideal Effects: Switch Debouncing

9 Non Ideal Effects: Switch Debouncing

10 Non Ideal Effects: Switch Debouncing Switch debouncing can be tricky Electromagnetic Interference (EMI) can also cause apparent switch transitions without activating the switch Best to use intelligent software debouncers

11 Non Ideal Effects: Switch Debouncing

12 Non Ideal Effects: Switch Debouncing // Service routine called by a timer interrupt i.e. Regularly int DebounceSwitch() { static int State = 0; State=(State<<1)!RawKeyPressed() 0xe000; if(state==0xf000) return 1; return 0; }

13 Non Ideal Effects: Switch Debouncing The processor in a keyboard (computer) "debounces" the keystrokes, by aggregating them across time to produce one "confirmed" keystroke. Early membrane keyboards limited typing speed because they had to do significant debouncing. Is it necessary to do keyboard debouncing? Practice!!

14 Non Ideal Effects: Timing Closure Problem: Clock skew and data delays through propagation delays cause leads to the violation of setup and hold times: worse in large designs

15 Non Ideal Effects: Timing Closure If Tsu and Th are not violated the D is transferred to Q after the flip flop clock to output delay, Tcko If Tsu and Th are violated then Q is indeterminate Th can be ignored for Xilinx FPGAs

16 Non Ideal Effects: Timing Closure Real designs usually involve 1000's of flip flops with several levels of combinational logic between them... a multitude of logic paths Can control these logic paths. (Constraints editor, Floorplanner tools) Can verify these logic paths. (Timing analyser or TRCE tool) If timing is OK then the Timing analyser in.twr report says All timing constraints met or else...clock frequency too high or... too many logic levels or...too much routing delay

17 Non Ideal Effects: Timing Closure Safe operation: Tclk >= Tcko + (logic and routing delays) + Tsu

18 Non Ideal Effects: Timing Closure In an ideal design there will be minimal clock skew Optimal for synchronous designs is to attach a dedicated clock resource to a BUFG (2 8 in most Xilinx FPGAs) For a given Fclk and FPGA you only have to control the number of LOGIC DELAYS (LEVELS) such that the sum total of delays does not exceed the clock period

19 Non Ideal Effects: Timing Closure:.TWR report Report shows missed our timing goal: slack NEGATIVE (.662ns) 67% logic budget/33% routing budget (Xilinx recommends opposite)

20 Timing Closure: Large Clock Skwe Must respect Tcko(FFA) > SKEW However due to clock delay, Q output of FFA may be unstable (changing when FFB receives the (delayed) clock edge Clock freq does not affect the problem!!

21 Large clock skew solutions? Compensate for clock skew by adding logic delay in data path. Propagate the clock in the other direction...

22 RTL Design Examples: A Morse Code Translator 3213: Digital Systems & Microprocessors: L#L#16_17

23 Morse Code Transmits telegraphic information using rhythm. Morse code uses a standardized sequence of short and long elements (dots and dashes) to represent information. Originally invented by Samuel F. B. Morse's (April 27, 1791 April 2, 1872) for his electric telegraph in the early 1840s, Morse code was also extensively used for early radio communication beginning in the 1890s. Variable length of the Morse characters made it hard to adapt to automated circuits. Morse code mostly used now by amateur radio operators, although it is no longer a requirement for licensing in many countries.

24 Morse Code Morse code is transmitted using just two states (on and off) so it was an early form of a digital code. Visualize any Morse code sequence as a combination of the following five elements (quinary): 1. short mark, dot or 'dit' ( ) 1 2. longer mark, dash or 'dah' ( ) intra character gap (between the dots and dashes within a character) 0 4. short gap (between letters) medium gap (between words)

25 A Morse Code MO RSE C O DE

26 Design Concept Hang on..not so useless could use for texting? Morse code not amenable to digital implementation due to its syncopated asynchronous human element > Make it amenable by assigning PEGASUS push buttons to the dots, dashes and spaces. > Breaks rules by making Morse code a ternary (actually quaternary) as opposed to a quinary code. dot, dash, space is all we need! PB0 PB1 PB2 DOT DASH SPACE (FINE PRINT: this implementation cannot separate words) 3213: Digital Systems & Microprocessors:L#16_17

27 Pegasus Implementation Use three push buttons PB0, PB1, PB2 3213: Digital Systems & Microprocessors:L#16_17

28 Morse Code Module Data and Control Variables Data: [0:0] PB0,1,2 > [3:0] beeps = {DOT, DASH, SPACE, NULL} > [15:0] morse (aggregate morse code charactre) > Char (Alphanumeric character) Control: [3:0] beeps = {DOT, DASH, SPACE, NULL} > [0:0] rst, inc, chen

29 RTL Interface Let PEGASUS push buttons (PBs) do dot, dash, space. Need a separate interface (ButtonIface.v) to convert PB inputs to some for RTL system. Issues debounce the PBs a must. Need to sync inputs to FSM. DOT, DASH, SPACE, NULL work a bit like KEY/NOKEY in example in RP project description. Will not treat the display driver (HLAB3)

30 ButtonInterface

31 ButtonIface.v

32 Encode Morse dits/dahs in synced variable [3:0] beeps, where beeps can be... // Events use last two bits of DOT and DASH parameter DOT parameter DASH parameter SPACE parameter NULL = 4'b0010; = 4'b0001; = 4'b0011; = 4'b0000; //The Clayton's beep // the beep we had to have

33 ButtonIface.v: Input PB0,1,2 Output DOT/DASH/SPACE/NULL DeBounce DB(clk, PB0, PB1, PB2, X0, X1, X2); //PB* clk) begin become X* if(~x0 & X1 & X2 & ~done) // If ~done did got a ~X0 at last begin beeps <= DOT; done <= 1'b1; / /posedge clk then output a DOT end else if(~x0 & X1 & X2 & done) // begin // beeps <= NULL; done <= 1'b1;...(similar code for DASH and SPACE)... end else begin beeps <= NULL; done <= 1'b0; end If done and still ~X0 then output a NULL and still done // if posedge clk and all Pbs open // then ready to accept button push again

34 ButtonIface.v: QUESTION What happens if more than one button is pushed at a time?

35 Morse Code Controller Functional Description Inputs: beeps = {DOT, DASH, SPACE, NULL} Outputs: rst, inc, chen

36 Controller State Diagram

37 Controller State Transition Table 3213: Digital Systems & Microprocessors:L#16_17

38 Data Path Design Data path has two modules Register KeyHoldReg.v registers DOT, DASH, SPACE, NULL... need to build them up like the KHR in RP. Uses beeps and morse Register Morse2Char.v outputs an alphanumeric character for each Morse code sequence. Uses morse and char Probably would use a Look Up Table (LUT) to store characters given DOTS and DASHES but incorporate this into Morse2Char.v Always control these by binary switch controls from FSM 3213: Digital Systems & Microprocessors:L#16_17

39 RTL diagram

40 KeyHoldReg.v clk) begin if(rst) begin morse <= 16'hffff; // morse stores a word //Reset to a non morse char end else if(inc) begin morse <= {morse[13:2], beeps[1], beeps[0], 1'b0, 1'b0}; //store DOT/DASH incrementally end else morse <= morse;

41 Morse2Char.v parameter S = 14'b ; parameter O = 14'b ; clk) begin if(chen) begin case(morse[15:2]) S: char <= S; O: char <= O; endcase end end

42 Output: print S.O.S

43 A Radio Receiver A radio receiver to communicate data Receives two 16 bit data streams (I,Q) from an ADC Through an ADC Interface

44 Before ADC is analogue part..

45 ADC Interface (assume it exists)

46 Functionality Account for wireless impairments Random noise (Error coding) Intersymbol interference (Equalisation) Carrier offset (Differential coding) Timing offset (Timing recovery state machine)

47 Architecture Use differential Binary Phase Shift Keying (DBPSK) modulation BPSK modulates carrier sine wave by data stream DBPSK the data bits ( 1,1, 1, 1,...) are represented by phase changes of 0 and in the carrier signal avoids issues with carrier offset

48 BPSK No Carrier Offset: I,Q look like

49 BPSK with Carrier Offset: I/Q look like

50 DBPSK No Carrier Offset Data:

51 DBPSK No Carrier Offset Data:

52 Controllers The state description is primary FSM producing control signals Control signals determine actions performed in other parts of the system Autonomous Controller: fixed sequence of states independent of inputs

53 RTL approach Digital system divided into Data and Control subsystems. The state of a system consists of the contents of its registers. Functioning of system performed in a sequence of register transfers synchronous to the clock. The register transfer is a transformation performed on a datum while the datum is transferred from one register to another. The sequencing of the register transfers is controlled by the control subsystem

54 Sequential Execution Graphs Only one node can be executed at a time Loop Unfolded

55 Group Sequential Execution Graph In group sequential execution graphs each group can start when the preceding has been executed 3213: Digital Systems & Microprocessors:L#16_17

56 Transfer Concurrent into Sequential Execution Graph Any concurrent execution graph can be converted into an equivalent sequential graph by sequencing of the concurrent nodes

57 Concurrent vs Sequential (and G.S.) Execution Graphs Sequential execution graphs are easier to develop due to ease of tracking data transformations Control of sequential execution graphs is simpler because A single arc usually goes from one node to its unique successor A node may have several output arcs but a conditional branch determines which path is followed Sequencing can be controlled by a FSM in which each node or group of nodes corresponds to one state of the controller Concurrent graphs are potentially a faster.

Projects. Reverse polish calculator. Wireless terminal. 3213: Digital Systems & Microprocessors: L#15

Projects. Reverse polish calculator. Wireless terminal. 3213: Digital Systems & Microprocessors: L#15 Projects Reverse polish calculator Wireless terminal Reverse Polish Calculator Reverse polish Lukasiewicz (1920) Hewlet-Packard HP-35 (1972) 15 digit display 10 digit mantissa plus sign, decimal pt, two