(19) World Intellectual Property Organization International Bureau

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1 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date (10) International Publication Number 1 February 2007 ( ) PCT WO 2007/ A2 (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every H03K 17/14 ( ) kind of national protection available): AE, AG, AL, AM, AT,AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, (21) International Application Number: CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, PCT/IB2006/ GB, GD, GE, GH, GM, HN, HR, HU, ID, IL, IN, IS, JP, (22) International Filing Date: 13 July 2006 ( ) KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LV,LY,MA, MD, MG, MK, MN, MW, MX, MZ, NA, (25) Filing Language: English NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SY, TJ, TM, TN, TR, TT, TZ, (26) Publication Language: English UA, UG, US, UZ, VC, VN, ZA, ZM, ZW (30) Priority Data: (84) Designated States (unless otherwise indicated, for every July 2005 ( ) EP kind of regional protection available): ARIPO (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, (71) Applicant (for all designated States except US): KONIN- ZW), Eurasian (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), KLUKE PHILIPS ELECTRONICS N.V. [NL/NL]; European (AT,BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, Groenewoudseweg 1, NL-5621 BA Eindhoven (NL). FR, GB, GR, HU, IE, IS, IT, LT, LU, LV,MC, NL, PL, PT, (72) Inventors; and RO, SE, SI, SK, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, (75) Inventors/Applicants (for US only): IONITA, Raz- GN, GQ, GW, ML, MR, NE, SN, TD, TG). van-adrian [RO/FR]; C/o Prof. Holstlaan 6, NL-5656 AA Eindhoven (NL). SANDULEANU, Mihai, A., T. Published: [NL/NL]; C/o Prof. Holstlaan 6, NL-5656 AA Eindhoven without international search report and to be republished (NL). STIKVOORT, Eduard, F. [NL/NL]; C/o Prof. upon receipt of that report Holstlaan 6, NL-5656 AA Eindhoven (NL). For two-letter codes and other abbreviations, refer to the "G uid (74) Agents: ELEVELD, Koop, J. et al; Prof. Holstlaan 6, ance Notes on Codes and Abbreviations" appearing at the beg in NL-5656 AA Eindhoven (NL). ning of each regular issue of the PCT Gazette. (54) Title: TRANSISTOR BULK CONTROL FOR COMPENSATING FREQUENCY AND/OR PROCESS VARIATIONS (57) Abstract: The present invention relates to a method and apparatus for controlling a bulk voltage supplied to at least one tran sistor means of a controlled circuit (260) of an integrated circuit, wherein at least one sensing transistor means is provided adjacent to the at least one transistor means of the controlled circuit (260), and at least one reference transistor means is provided at a location remote from the at least one transistor means of the controlled circuit (260). A predetermined bias voltage is applied to the at least one reference transistor means, and the bulk voltage is controlled based on a comparison of a sensed threshold voltage of the at least one sensing transistor means and a sensed threshold voltage of the at least one reference transistor means. Thereby, process variation can be compensated. Alternatively or additionally, an information indicating a relation between a frequency information and a desired threshold voltage of the at least one transistor means of the controlled circuit (270) may be stored, and the bulk voltage may be controlled to an optimized value based on the stored relation with respect to a frequency of an input signal of the integrated circuit.

2 Transistor Bulk Control for Compensating Frequency and/or Process variations The present invention relates to a method and apparatus for controlling a bulk voltage supplied to at least one transistor element, such as a metal oxide semiconductor (MOS) transistor, of an integrated circuit. A low-voltage trend for digital circuits has been caused by lower power consumption of CMOS (Complementary MOS) logic families operating at lower and lower supply voltages and down-scaling of the oxide thickness for reliability reasons. When speed is at stake, the design of digital building blocks becomes an analog matter since any of the classical solutions working at low speed will not provide the required performance. A fast logic family in MOS technology is the Source Coupled Logic (SCL) family. However, at lower supply voltages SCL fails to work properly due to the stacking of transistors. In this category are included AND, OR, XOR gates and D-latch circuits. The D-latch is the most difficult function to implement since the requirements for small set-up and hold times lead to increased power consumption. At the edge of the possible acquired speed a latch should take decisions and therefore sufficient gain is needed. The transconductance of modern MOS technology is low compared to its bipolar counterpart and therefore wider devices and higher currents are needed to achieve the gain requirements. As a consequence, the rise-fall times are impaired and therefore the speed. Given the CMOS process, a preferable logic iunction in R-NMOS (Resistor N-channel MOS) style is the NOR. Here, the MOS transistors are working with zero backgate voltage and have the largest possible transconductance. Based on this logic function a low-voltage, high-speed latch is desirable to circumvent the above-mentioned drawbacks. In a positive clock (CK) level triggered D-latch of the SCL family, a differential MOS transistor pair is provided, which tracks the input D when the CK level is positive, and on a negative level of CK a latch formed by another MOS transistor pair becomes active taking a hard decision on the output Q. By stacking transistors we get the following disadvantages: The supply voltage will be limited to V GS +2(V GS -V T )+ V, where V GS is the

3 gate-source voltage of one of the transistors of the transistor pairs, i.e. the MOS current source I 0, V T is the threshold voltage defined by the manufacturing process and V is the voltage drop on the resistor needed to bias the transistors of the differential transistor pair. In modern processes like CMOS090 SOI (Silicon-on-Insulator), or triple-well - GP (General Purpose) version, the supply voltage is limited to 1.0V and the circuit should work at 0.90V (1.0V-10%). For triple-well CMOS090 LP (Low Power) technology, the supply voltage is limited to 1.2V, and the circuit should work at 1.08V (1.2V-10%). The transistor pair of the latch and the differential transistor pair share the load resistors. Therefore the latch has the difficult task to take decisions on a large capacitance load given by its own stray capacitances (C GS + C DS )/2, the parasitic capacitances of the differential transistor pair and the load capacitance given by wiring, fan-in and the load resistor. The use of a buffer between the latch and the differential gain stage is excluded due to the lack of voltage range and the lack of good source-followers in baseline digital processes. - The intrinsic delay of the data relative to the clock path. The clock path has a larger delay than the data path and therefore the delay times from CK to Q output (t d cκ >Q) and from D to Q output (t d o-xj) are not equal. This can impair the function of a phase detector and can generate extra offset in a PLL (phase-locked loop) in its locked state. There is a difference in bias level between the D and the CK inputs. As the transistors are stacked, a level shifter is needed between the D level and the CK level, asking for extra source followers or level shifters that decrease the speed of operation and enhance the intrinsic delay between the data path and the clock path. The above-mentioned latch circuit forms the basic building block of a D-latch. The transistors of the differential transistor pair have their sources connected to ground and their source-bulk voltage is zero. Therefore the threshold of these transistors is V T =V T0 and they have the maximum transconductance with the lowest threshold. The loop gain in the latching mode is (g m Ri) 2 >2 for a correct operation. In the last decade, the CMOS process became a viable option for analogue RF circuits and RF SoC (System-on-Chip), in a strong improvement of MOS devices. The threshold voltage, V T, affects the circuit delay, the transconductance of the MOSFET, the transition frequencyfr, and the leakage current. However, a variation of the threshold voltage is caused by fluctuations of gate length, doping concentrations in the bulk, gate oxide thickness, the occurrence of the noise in the substrate, temperature variations, etc. The threshold voltage is a process parameter the value of which can be controlled during the

4 manufacturing process by controlling the doping concentration in the channel. At circuit level, a way to control V T is to modify the bulk-source voltage. Different techniques are proposed in the literature starting from substrate back biasing as described in James W. TSCHANZ et al, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", IEEE JSSC, VOL. 37, NO. 11, Nov. 2002, pp , and Masayuki MIYAZAKI et a "A 1.2-GIPS/W Microprocessor Using Speed- Adaptive Threshold- Voltage CMOS With Forward Bias", IEEE JSSC, VOL. 37, NO. 2, Nov. 2002, pp In a triple-well CMOS technology and Silicon-On-Insulator (SOI) CMOS as well, it is possible to control independently the bulk of NMOS and PMOS transistors, with good substrate isolation. Applying a forward back-bias (FBB) to the bulk of the transistor will decrease V T and increase the speed of the analog circuits. Applying a reverse back-bias (RBB) leads to lower power consumption for integrated circuits, which saves the battery life for portable systems. It is possible to change the value of the threshold voltage by applying a voltage to the bulk node of a MOS transistor. The change V r of the threshold voltage can be positive or negative, according to the voltage applied to the bulk with respect to the source voltage. For an NMOS transistor and positive source-bulk voltage V SB between the source terminal and the bulk terminal, the change V r is positive and the threshold voltage is increased. This is called Reverse Back Bias (RBB). For a negative source-bulk voltage V SB, the change V r becomes negative and the threshold voltage is decreased, which is called Forward Back Bias (FBB). For PMOS transistors, the reference threshold voltage Vτ p o, is defined for VsB=O, where the bulk and source are connected. When the bias voltage of the bulk is changed with respect to the source voltage, for a negative source-bulk voltage V SB, the threshold voltage is increasing in absolute value, and the PMOS transistor is in the RBB. For the other case of FBB, the source-bulk voltage should be positive. Fig. 2 shows a schematic diagram indicating a typical characteristic of the threshold voltage V T in dependence on the source-bulk voltage V SB of an NMOS transistor. As can be gathered from Fig. 2, the threshold voltage V T has a non-linear dependence on the source-bulk voltage V SB - Each variation of the source-bulk voltage V SB leads to a variation of the threshold voltage V T. The presence of a junction diode between the source and bulk terminals limits the forward biasing. When the forward bias becomes higher than 0.7V, the diode starts to

5 conduct and the leakage current increases exponentially. The practical limit of FBB is thus some hundred mv below that value. The RBB is not really limited, except for the capability to apply and form the required voltage. Practically, a limit for RBB is given by the back-bias efficiency. This means that only little improvement is achieved if the bias is going deeply in reverse. For on-chip applications, a bulk voltage higher than the power supply can be achieved by using charge-pumps or conventional DC-DC converters. Otherwise exterior circuits, with the drawback of at least one more external input pin and supply, can provide this voltage. US6, 147,508 discloses a method and apparatus for controlling the speed of a logic device by adjusting the threshold voltage of MOS devices forming the logic device under control. Applying a back bias voltage between the bulk material in which the logic device under control is fabricated, and the most positive electrode of the device controls the threshold voltages of the MOS devices. The back bias voltage value is controlled in response to the temperature of the logic device, thereby closing a feedback loop. However, during the fabrication process of semiconductor devices, variations occur in doping densities, implant doses, and width and thickness of active diffusion, oxide layers and passive conductors. All these process variations are translated in the device performance. Process parameter variations of the technology can result in the manufacturing of dies with variations in maximum operating frequency and power consumption. These variations can be over a single die (so-called within-die variations - WID), or can be different from die-to-die on a wafer or a lot (so-called die-to-die variations - D2D). These variations cause difference in transistor characteristics and device parameter, and will result in a distribution of die frequencies and leakage. This distribution is divided into several regions, "bins", and the chips that meet the power specifications are placed into the highest-possible bin. It is therefore an object of the present invention to provide an improved transistor bulk control method and apparatus, by means of which the characteristic of the controlled device can be optimized in terms of power consumption and frequency. This object is achieved by an apparatus for controlling a bulk voltage supplied to at least one transistor means of a controlled circuit (260) of an integrated circuit, said apparatus comprising:

6 at least one sensing transistor means provided adjacent to said at least one transistor means of said controlled circuit (260); at least one reference transistor means provided at a location remote from said at least one transistor means of said controlled circuit (260); - biasing means (120) for applying a predetermined bias voltage to said at least one reference transistor means; and bulk control means for controlling said bulk voltage based on a comparison of a sensed threshold voltage of said at least one sensing transistor means and a sensed threshold voltage of said at least one reference transistor means. Accordingly, process variations can be compensated in order to find an optimum in terms of frequency and power consumption. On one hand, the threshold voltage can be controlled to compensate within-die (WID) process variations. On the other hand, the threshold voltage can be moved, based on the stored frequency relation, to an optimum threshold voltage that will minimize power consumption. At least one sensing transistor means and the controlled circuit may share the same well region. This measure serves to ensure that variations within the same well are compensated. Additionally, the at least one reference transistor means may be placed in an isolated well region, to ensure independent reference conditions. Furthermore, the biasing means may comprise band gap circuit means, so as to achieve high absolute accuracy. The controlled circuit may comprise a frequency divider circuit, wherein the at least one sensing transistor is placed at a circuit area of a data latching differential transistor pair of the frequency divider circuit. The number of the at least one sensing transistor means corresponds to the number of the at least one reference transistor means. Thereby, better match between the voltage at the output of the threshold monitoring functionality and the reference transistors can be achieved. In particular, the bulk control means may be configured to control the bulk voltage within a positive and negative voltage range. This provides the advantage that the proposed control mechanism covers both RBB and FBB mode. According to a specific but not restrictive example, the bulk control means may comprise a control circuit for receiving the frequency relation information, and a voltage divider circuit controlled by the control circuit. Then, as an example, the control circuit may be configured to decode the frequency relation information and to control switching means of the voltage divider circuit, based on the decoded information, in order to generate the bulk voltage. This voltage divider circuit may comprise a resistive divider connected between a positive supply voltage and a negative

7 supply voltage, so as to generate the bulk voltage within a positive and negative voltage range. The above two bulk control mechanisms may be combined to compensate process variations and to provide power and speed adaptation via threshold control. Furthermore, the integrated circuit may be designed in a triple-well or silicon-on-insulator process. As a modification, additional inductive peaking means may be incorporated for example into a data latching differential transistor pair of the controlled device to improve high-speed performance and to extend circuit bandwidth. According to a specific implementation example, the inductive peaking means may comprise at least one stacked metal inductor, which provides the advantage of easy on-chip integration and less chip area occupied. The bulk control means may comprise first bulk control means for controlling a bulk voltage of an NMOS type transistor, and second bulk control means for controlling a bulk voltage of a PMOS type transistor, wherein the PMOS type transistor is arranged in a N- well of the integrated circuit, and wherein the NMOS type transistor is arranged in a P-well of the integrated circuit. Further advantageous modifications are defined in the dependent claims. The present invention will now be described on the basis of preferred embodiments with reference to the accompanying drawings, in which : Fig. 1 shows a schematic circuit diagram of a static divide-by-two IQ frequency divider with bulk control, in which the present invention can be implemented, Fig. 2 shows a diagram indicating a typical characteristic of threshold voltage vs. source-bulk voltage of an NMOS transistor; Fig. 3 shows a schematic circuit diagram of a D-latch circuit with threshold voltage control; Fig. 4 shows a schematic circuit diagram of a D-latch circuit with threshold voltage control and inductive peaking; Fig. 5 shows a schematic diagram of FBB and RBB effects in frequencydependent input power sensitivity of the IQ frequency divider of Fig. 1; Fig. 6 shows a schematic diagram of back-bias control for finding an optimum input power sensitivity of the IQ frequency divider of Fig. 1;

8 Fig. 7 shows a diagram with input sensitivity curves as a function of frequency with and without inductive peaking; Fig. 8 shows a schematic block diagram of a compensation circuit according to a first preferred embodiment; Fig. 9 shows a schematic block diagram of a compensation circuit according to a second preferred embodiment; Fig. 10 shows a schematic block diagram of a voltage divider which can be used in the second preferred embodiment; Fig. 11 shows a schematic block diagram of a combined compensation arrangement according to a third preferred embodiment; Fig. 12 shows a schematic layout of a stacked metal inductor which can be used for inductive peaking; Fig. 13 shows a schematic circuit diagram of an input and output buffered static divide-by-two IQ frequency divider with bulk control, in which the present invention can be implemented; Fig. 14 shows a schematic circuit diagram of an input buffer with inductive peaking; Fig. 15 shows a schematic circuit diagram of an output buffer; Fig. 16 shows a schematic block diagram of a combined adaptive threshold voltage control for both NMOS and PMOS transistors, according to a fourth preferred embodiment; Fig. 17 shows schematic circuit diagrams of a threshold voltage monitoring principle; Fig. 18(a) and Fig. 18(b) show more detailed circuit diagrams of an implementation of the threshold voltage monitoring principle of Fig. 17; and Fig. 19 shows a schematic block diagram of an adaptive threshold voltage control for only NMOS transistors, according to a fifth preferred embodiment. The preferred embodiments will now be described on the basis of a static divide-by-two IO frequency divider with bulk control as shown in Fig. 1. Frequency dividers circuits are commonly used in frequency synthesizers such as Phase-Locked Loop circuits (PLL). The CMOS frequency divide-by-2 analog circuit of Fig. 1 is based on a chain of two D-latches 10, 12 with a negative feedback, as indicated by

9 the crossed feedback lines. This frequency divider is capable to operate at very low supply voltages (e.g. IV - 1.2V) and very high frequency (e.g. above 30GHz). The function of this frequency divider is to generate output signals I and Q having a frequency corresponding to half of the frequency of the input signal (CK), and being phase-shifted by 90 degrees with respect to each other. The inverted versions of the signals are indicated by the suffix "b". The frequency divider of Fig. 1 may operate above 30GHz and may be designed and implemented with R-NMOS type of logic, in CMOS090 technology (0.1 µm transistor length feature size) with silicon-on-insulator (SOI) and triple-well substrates. CMOS090 SOI is partially depleted technology and provides seven metal layers. Bodycontacted transistors are used for all SOI transistors. For implementation in triple-well process, CMOS090 LP with six metal layers can be chosen. The two identical D-latches 10, 12 (or D-flip-flops) are connected in a master/slave configuration, wherein the output signals of each D-latch are connected to the inputs of the other D-latch. The D-latches are implemented with only one transistors type, e.g., NMOS transistors using the R-NMOS type of logic. The feasibility of CMOS Triple-Well or CMOS SOI technologies provides freedom of controlling the threshold voltage by biasing the bulk of NMOS transistors. This technique is called V T control via back-biasing. The advantage of controlling the bulk, and therefore the threshold voltage, is given by the possibility of controlling this parameter which can vary due to transistor mismatches and process variations. Later it will be shown that the input power sensitivity of the frequency divider, implemented in triple-well and SOI CMOS technologies, is improved by controlling the NMOS transistors threshold voltage by applying a DC voltage to the bulk. Fig. 3 depicts a schematic circuit diagram of each of the D-latch circuit 10, 12 of Fig. 1 with threshold voltage control. An additional input, called "Bulk", controls the bulk of the NMOS transistors Ml to MlO. Via this Bulk input, a DC signal is applied to all NMOS transistors M l to MlO. Fig. 4 shows a schematic circuit diagram of each of the D-latch circuits 10, 12 of Fig. 1 with inductive peaking and threshold voltage control. The inductive peaking effect is achieved by providing additional inductors L, connected between load resistors R2 and supply voltage VDD. The inductive peaking is provided in the latch transistor pair M l and M2 of the D-Latch circuits 10, 12 and is used to improve the high-speed performance. A theoretical bandwidth extension of 70% can be achieved by this additional measure, which in practical applications may decreased to about 30-40%.

10 Fig. 5 shows a diagram indicating the reverse (RBB) and forward back-biasing (FBB) effects in the input power sensitivity of the static divide-by-two IQ frequency divider with bulk control of Fig. 1. Applying a negative or positive D C voltage via the Bulk input to the transistor bulks, in fact to the p-well where the NMOS transistors are built, results in a proportional frequency shift of the input power sensitivity o f the frequency divider. The shift is directed to the left in the frequency domain (i.e. towards a lower frequency fpbb) r a positive DC voltage (FBB), and to the right (i.e. towards a higher frequency frbb) r a negative DC voltage (RBB). This property can b e used for finding the optimum in terms of frequency and power consumption. Fig. 6 shows a schematic diagram o f back-bias control for finding an optimum input power sensitivity of the IQ frequency divider of Fig. 1. To give an example, let's suppose that the frequency divider received at its input a signal with a frequency fi N that is not near to its optimal input frequency - with the working condition corresponding to point A of Fig. 6, where it needs a high power input signal. In point B, the input power is much lower and the frequency divider is dividing the frequency input signal at its optimal input frequency. Moving the point A to the low input power point B can b e achieved by supplying a corresponding positive voltage Vp (FBB mode) to the NMOS transistor bulks, which results in a shift of the characteristic or curve of the input power sensitivity to the left so as to reach its minimum at the frequency f NO M, i.e. to the sensitivity curve with the minimum input power at the input signal frequency ffbb- For the opposite case, when the point A is on the right side of the optimum frequency f NO M, an equivalent scenario can be imagined, but now a negative back-bias (RBB) voltage V RBB should be applied to the NMOS transistor bulks in order to shift the sensitivity curve to the right. Apparently, the input power sensitivity is strongly affected by process variation, especially around the point where the frequency divider reaches its minimum input power, or maximum sensitivity. For example, it can b e observed that the minimum power at the input is shifted by 4GHz between nominal and fast corners situations. The process corner dependency can b e corrected by controlling the bulk of the NMOS transistors in order to shift slower or faster power sensitivity curves to a nominal one. The nominal situation at Vbulk=0V corresponds to the case when the source of the transistors is tied to their bulks. Applying a positive voltage to the p-wells, with respect to the source potential o f the transistor, decreases the threshold voltage (FBB - Forward Back-Bias). For the input power sensitivity o f the frequency divider, the curve shifts to the left on the frequency axis with an

11 amount proportional to the DC voltage applied to the NMOS transistor bulk. Connecting the NMOS bulk to a negative DC voltage, which corresponds to the RBB (Reverse Back-Bias) mode, the threshold voltage increases and the sensitivity curve shifts to the right. The effectiveness of this method becomes very clear from practical measurements of the frequency divider with D-latches incorporating shunt peak coils, as shown in Fig. 4, where application of an FBB voltage of 60OmV has been observed to shift the power sensitivity curve by almost 8GHz. It can be concluded that for moving a slow corner characteristics to an optimum point, it is enough to supply corresponding FBB voltages to the bulk. Similarly, for the case when Vbulk = -20OmV, a shift of the minimum input power by almost 3GHz has been observed. Obviously, following the same criteria, it is possible to move a fast corner characteristics to a nominal one by providing a corresponding RBB voltage to the NMOS transistors in the frequency divider, i.e. a negative voltage with respect to the source potential. For the frequency divider with D-latches without inductive peaking, as shown in Fig. 3, a frequency shift of 7GHz has been observed from the fast corner to the nominal corner with minimum input sensitivity. But also, the impact of the threshold voltage control via back-biasing technique is higher. Applying a 60OmV to the NMOS bulks results in a shift to a lower frequency by 10GHz, and for -20OmV this shift is only by 4GHz frequency to the right. Incorporating the inductive peaking into the frequency divider results in a considerable spread in frequency of e.g. 4 GHz for the minimum input power, between nominal and fast corners, compared to more than 7GHz for the case when the inductive peaking is not present. As mentioned already, also the impact of back biasing is much higher, in terms of frequency spread of the sensitivity, for the case when the shunt-peak coils are not used. Fig. 7 shows a diagram with input sensitivity curves as a function of frequency with and without inductive peaking in nominal corner, i.e. for V bu ik=0v, for the static divideby-two IQ frequency divider of Fig. 1. The dotted curve of Fig. 7 corresponds to the situation without inductive peaking. The difference in frequency is around 2GHz for the input minimum power, but becomes larger with the process variation. An control apparatus according to a first preferred embodiment for controlling the threshold voltage of the transistors in the frequency divider of Fig. 1 in order to compensate the within-die (WID) process variations is proposed in Fig. 8. In Fig. 8, at least one sensing transistor 8 (not shown) is placed between the D- latches of a controlled frequency divider circuit 260 and shares the same well of an integrated

12 circuit (IC) core 100. The frequency divider circuit 260 belongs to an integrated PLL circuit 200 which is provided on the IC core 100 and which comprises a phase detector 220 to which an input circular frequency COj n is supplied, a low-pass filter 240, a voltage-controlled oscillator 250 which generates an output circular frequency CJO 0. The output circular frequency ω o u is fed back to the phase detector 220 via the controlled frequency divider 260 and a non-controlled divide-by-m frequency divider 230. Based on the detected phase difference between the input circular frequency ω o u and the fed-back output circular frequency co o u, a control signal is supplied to the voltage-controlled oscillator 250 via the low-pass filter 240. The threshold voltage V n of the sensing transistor provided in the controlled frequency divider 260 is compared, at an adaptive threshold voltage control circuit 110, with the threshold voltage V n r e f of a reference transistor (not shown), which is biased by a bandgap (BG) circuit 120 with high absolute accuracy (this is the nominal threshold voltage). The reference transistor(s) is placed in an isolated well, "far" away from the sensed well, but very near to the bandgap circuit 120. Using a multi-point sensing technique can increase the accuracy of the control apparatus. Increasing of the number of the V T sensing transistors placed nearby the radio frequency (RF) circuits improves accuracy. For example, for the case of the controlled frequency divider 260 a sensing transistor can be placed close to the data latching differential transistor pair of each D-latch. Then, two transistors sense the NMOS threshold voltage on the area where the frequency divider 260 is placed. In order to provide a better match between the voltage V n at the output of the control circuit 110 and the reference transistors, an equal number of sensing and reference transistors can be placed, for multi-point adaptive threshold voltage control. Fig. 9 shows a schematic block diagram of a compensation circuit according to a second preferred embodiment. Here, the power consumption is optimized for a given input frequency of a frequency divider 270 integrated in a PLL circuit 200 of an IP core as described in connection with Fig. 8. In addition to the circuitry of Fig. 8, the input circular frequency COj n is supplied to the PLL circuit 200 via an Inter-IC (I2 C) bus interface or environment 300 comprising or connecting to a memory block or unit 310. The I 2 C bus is a control bus that provides communications links between integrated circuits in the system. As an alternative, the memory unit 310 may also be integrated on the IC core.

13 In order to take advantage from both RBB and FBB techniques, which needs either positive and negative bulk voltages V bn, the voltage divider 270 has to be supplied with a bulk voltage ranging from positive to negative voltages. The difference between the absolute voltage of the respective voltage sources should cover the full range of voltages necessary to move the sensitivity curves of the frequency divider from slow to fast corners, in the processed frequency domain. In the memory unit 310 the frequency information for each NMOS threshold voltage is stored. The purpose is to find an optimum value in terms of power consumption. For each frequency of the input signal, the system will apply a corresponding voltage, V b, to the transistor bulk in order to move the threshold voltage to an optimum value required to minimize the power consumption. A digital control block or unit 130 decodes a digital value stored in and read from the memory unit 310, and controls switching means of a voltage divider 140 based on the read digital value in order to apply the correct threshold voltage to the transistor bulk. Thus, the digital value provides a relation between the input frequency to be processed by the integrated circuit or particularly the PLL circuit 200 and the correct threshold voltage. Fig. 10 shows a schematic block diagram of the voltage divider 140 of Fig. 9. This voltage divider block 140 is a resistive divider comprising a series connection of a plurality of resistors R l to Rn, connected between a positive voltage, V+, and a negative voltage, V-, so as to cover both RBB and FBB mode. Furthermore, a plurality of corresponding switching elements Sl to Sn are provided, through which the nodes between adjacent resistors can be connected to a common output terminal in order to control the value of the bulk voltage V bn which is then supplied to a bulk terminal 272 of the frequency divider 270. The control of the switching elements Sl to Sn is achieved via a control input connected to the digital control unit 130. Fig. 11 shows a schematic block diagram of a combined compensation arrangement according to a third preferred embodiment, which includes both threshold voltage control options as described in connection with Figs. 8 to 10. The total of all these effects is used in the control or compensation mechanism of Fig. 11. The adaptive threshold voltage control achieved by the bandgap circuit 120 and the control circuit 110 provides a DC bias voltage that is applied to the transistor bulk in the frequency divider in order to compensate the process variations, and, on the other side, the digital control by the digital control circuit 130 and the voltage divider 140 supplies to the controlled circuit, e.g. a frequency divider of a PLL circuit, a bulk voltage in accordance with the optimum working

14 condition between frequencies and power consumption. The to bulk control voltages are added or superposed by an adding function or unit 150 which outputs the bulk voltage V bn to be supplied to the controlled circuit. In order to improve high-speed performance and also extend the bandwidth of the circuit, inductive peaking can be incorporated into the data latching differential transistor pairs of each D-latch of the controlled circuit. Fig. 12 shows a schematic layout of a stacked metal inductor 40 with different windings 42, 44 and 46, which can be used for inductive peaking. The stacked metal inductor 40 can be provided on the M2, M4 and M6 metal layers, so as to avoid the parasitic capacitance between two consecutive layers. These coils do not have a high quality factor, Q, but are easy to integrate on-chip and do not occupy much chip area, compared to single-metal layer inductors, which are normally used in the RF integrated circuits. For decreasing the parasitic capacitance between two consecutive layers, only M2, M4 and M6 metal layers are used for these stacked inductors. Fig. 13 shows a schematic circuit diagram of an input and output buffered static divide-by-two IQ frequency divider with bulk control. For measuring the performance of the frequency divider and also for matching, the static divide-by-two IQ frequency divider has a clock input buffer 18, two output buffers 14, 16 and two D-latches 10, 12 in a masterslave configuration. The clock input and signal output buffers 18, 14, 16 are designed to transmit the differential signals into and from the D-latches 10, 12. They drive an external load of e.g. 50Ω load for a wide frequency range centered on e.g. 30GHz at the divider input and e.g. 15GHz at the IQ outputs, respectively. Fig. 14 shows a schematic circuit diagram of the clock input buffer 18 of Fig. 13 with inductive peaking, and Fig. 15 shows a schematic circuit diagram of the output buffers 14 and 16 of Fig. 13. Both clock input and output buffers 14, 16, 18 consist of a differential transistors pair comprising transistors M l and M2, which acts as a simple differential amplifier, load resistors Ro and a biasing current transistor Mb. Connecting the transistor bulks to its source eliminates the body effect. A bias current of e.g. 2OmA may be provided in the clock input buffer 18, while a bias current of e.g. 10mA may be provided in each of the output buffers 14, 16 if the buffered frequency divider circuit of Fig. 13 is implemented in CMOS090 LP, and 12mA, respectively 6mA if the buffered frequency divider circuit of Fig. 13 is implemented in CMOS090 SOI. Incorporating the inductive peaking between the load resistors Ro and the power supply VDD leads to an enhanced high speed performance of the clock input buffer 18. In a CMOS090 SOI implementation, the

15 circuit symmetry may be respected for a better transistor matching. The electromigration effects can be avoided by using large metal lines and allowing a maximum DC current of 2OmA. The power supply lines may be placed in top and bottom portions of the cell, which leads to an improved the current flow. Fig. 16 shows a schematic block diagram of a combined adaptive threshold voltage control for both NMOS and PMOS transistors, according to a fourth preferred embodiment. Here, the threshold voltage control is performed for n- and p-wells 410, 420, which can be controlled independently in the triple-well CMOS and Silicon-on-Insulator (SOI) CMOS technologies. For the frequency divider, only the part that bias and controls the bulk of NMOS transistors, which are placed in the p-well 420, has to be taken into account. According to Fig. 16, the control of NMOS transistors in the p-well 420 is a achieved by a supply-compatible, rail-to-rail output voltage, class AB operational amplifier 422 realized with NMOS transistors in the differential input stage. Furthermore, the control of PMOS transistors in the n-well 410 is a achieved by a ground-compatible, rail-to-rail output voltage, class AB operational amplifier 412 realized with PMOS transistors in the differential input stage. The supply-compatible operational amplifier 422 is connected to an NMOS monitoring circuit 424, and the ground-compatible operational amplifier 412 is connected to an NMOS monitoring circuit 414. Additionally, a floating current source 432 is provided in order to supply bias currents to the monitoring circuits 414, 424. In particular, a bias transistor network, formed with mirror current sources provides these bias current. Moreover, reference voltage generators 430, 434 are provided for generating reference voltages V R and V RP. The power supplies V DD and Vss are the same for the monitoring circuits 414, 424, reference voltage generators 430, 434 and the floating current source 432. These power supplies can be identical with the IP-core power supplies. The operational amplifiers 412, 422 are supplied with additional dedicated supply voltages V CC AI, V SS AI and V CC A2, VssA2, respectively, which are different from VDD and Vss- Furthermore, respective reference bulk voltages VsBp re f and VβBn re f are supplied to the monitoring circuits 414, 424 by a bandgap circuit (not shown). The function of the monitoring circuits 414, 424 is to measure the equivalent threshold voltage V or Vτ p of the IP-core, using a single sensing transistor or using the multi-point technique in the respective n-well 410 or p-well 420, and then to generate a difference Vτ n or Vτ p between the threshold voltage measured in the IP core (VTII or Vτ p ) and a respective reference threshold voltage Vτn_ re f or Vτ p re f, provided from a circuit outside the IP core (by the reference transistors - placed in an isolated well, outside the IP core). The gate of the sensing PMOS or NMOS transistor(s) - placed inside the IP

16 core, is biased by the reference voltage generators 430, 434. The reference threshold voltages V τn_ref or Vxp ref are obtained by measuring the threshold voltage V T of a reference transistor(s) placed in an isolated well. The differential inputs of the operational amplifiers 412, 422 are supplied with respective first input voltages corresponding to the sum of the difference Vm or Vτ p and the respective constant reference voltage V R or V RP at their inverting input, and with the respective constant reference voltage V R or V RP at their noninverting input, so as to generate respective adapted bulk voltages V BB and V BBP supplied to the respective n-well 410 and p-well 420. Controlling the substrate of the n-well 410 and the p-well 420 well, using the circuit presented in Fig. 16, can move the threshold voltages of the n-well 410 and the p-well 420 of the IP-core towards a specific process corner. In this way, process compensation can b e achieved. Fig. 17 shows schematic circuit diagrams o f the monitoring circuit 424 (Fig. 17(a)) for the NMOS threshold and the monitoring circuit 414 (Fig. 17(b)) for the PMOS threshold. The monitoring circuit 414 for the threshold voltages of PMOS transistors is similar with NMOS threshold voltage monitoring circuit 424 but is realized with complementary transistors. In Fig. 17(a), a reference transistor MNd is placed in an isolated well (outside the IP-core), and a sensing transistor MNs is placed inside the IP-core - where the threshold voltage variation is monitored. Similarly, in Fig. 17(b), a reference transistor MPd is placed in an isolated well (outside the IP-core), and a sensing transistor MPs is placed inside the IP-core - where the threshold voltage variation is monitored. The role of the sensing transistors MNs and MPs is to detect the differences between the threshold voltage of the transistors of the IP-core and the reference threshold voltage V T of the reference transistors MNd and MPd. The respective reference transistors MPd, MNd are placed on-chip and have identical dimensions with the respective sensing transistors MPs, MNs. Here, the number of sensing and reference transistors is identical. The output voltage of the monitoring circuit 424 of the NMOS threshold voltage can b e calculated as follows: V 0 =VR 11 + V Tn = V R 11 + (V Tn - V Tn _ re f) Similarly, the output voltage of the monitoring circuit 414 of the PMOS threshold voltage is obtained as follows: VO=VR P - V Tp = V Rp - (V Tp - V Tp _ ref )

17 A current mirror circuit 510 mirrors the supply current flowing through the respective sensing transistors MNs, MPs to a supply branch of the respective reference transistors MNd, MPd. The V T compensation can be done on-chip, if the bulk of the respective reference transistors MNd, MPd is tied to the source. As an alternative, V T compensation can be done externally by process compensation, if the bulk of the respective reference transistors MNd or MPd is used as an external input. In that case, this isolated well is connected to VβBn r e for VβBp r ef. Fig. 18 shows more detailed circuit diagrams of possible implementations of the monitoring circuit 424 (Fig. 18(a)) for the NMOS threshold and the monitoring circuit 414 (Fig. 18(b)) for the PMOS threshold. This variant is in fact a small feedback circuit, where the voltages generated by the reference transistors MNd, MPd and the sensing transistors MNs, MPs drive the gates of respective input differential pairs MN1/MN2 and MP1/MP2. In Fig. 18(a), transistors MNl, MN2, MN3, and MN4 have their bulk connected to their sources. Similarly, for the PMOS variant (see Fig. 18(b)), transistors MPl, MP2, MP3, and MP4 have the bulks tied to their source. The sensing transistor(s) MNs or MPs are placed on the IP-core, so that their bulks are connected to the output of the respective class AB operational amplifier 422, 412 shown in Fig. 16. The well of the respective reference transistor(s) MNd and MPd is connected to a pin or terminal called VβBn j -ef and VβBp j -ef, respectively. This pin represents a voltage applied to the well of the reference transistors MNd, MPd - the diode-connected transistors, which are placed in a well isolated from the IP-core. By controlling this bulk it is possible to compensate process fluctuations, because the monitoring circuits 414, 424 will follow the threshold voltage of the reference transistors MNd, MPd. The bulk of the reference transistors MNd, MPd can also be interpreted as an input for the threshold voltage control system, providing a dynamic backbiasing, or it can be tied to its source, for a static compensation. In the second case, only WID variations can be compensated. The output voltage Vo is equal to the drain-source voltage of the sensing transistor MNs or MPs. Due to the internal feedback, the circuits shown in Fig. 18 will track very accurate the drain voltages of reference and sensing transistors MNd, MPd, MNs, MPs. For this reason, this approach is less sensitive to transistor mismatches and temperature variations. The dimensions of the transistors can be chosen in order to minimize the deterministic offset between the voltages in the two branches of the feedback circuit.

18 These circuits of Fig. 18(a) and Fig. 18(b) can ensure good tracking between the two branches of the monitoring circuits 414, 424 with a maximum simulated error of around ImV. The two current sources (Ibias and 2Ibias) should be perfectly matched. For this purpose, a circuit based on a floating current source (FCS) 432 as shown in Fig. 16 can be used. The buffered 30GHz static divide-by-two IQ frequency divider with bulk control can be implemented in a triple-well and SOI CMOS090 technologies using only NMOS transistor type, in both versions, i.e. with and without inductive peaking. This correspond to a general case in RF integrated circuits, which are using normally only NMOS transistors due to the fact that they are faster than PMOS transistors for electron mobility reasons. Fig. 19 shows a schematic block diagram of an adaptive threshold voltage control for only NMOS transistors, according to a fifth preferred embodiment. Here, the schematic of adaptive threshold voltage control for NMOS and PMOS transistors shown in Fig. 16, which is more general for CMOS processes, can be simplified for the case of controlling only the threshold voltage of the NMOS transistors of the RF IC, as shown in Fig. 19. The principle of this circuit has been already presented before in connection with the fourth preferred embodiment. A bandgap circuit (not shown) precisely generates the reference back-bias voltage, VβBn j ē f, or this voltage can be provided from an external pin, in order to change the threshold voltage on the IC core 600. The functions of the blocks of the fifth preferred embodiment shown in Fig. 19 correspond to those of Fig. 16 and can therefore be omitted here. As described above, a static divide-by-two IQ frequency divider with bulk control has been proposed as an example for a controlled circuit, which can be implemented with and without inductive peaking. As further examples, two different CMOS technologies, a triple-well (CMOS090_LP) and Silicon-on-Insulator (CMOS090 SOI), have been suggested. Both technologies have the same transistor feature size of e.g. O.lnm. In summary, a method and a system has been proposed to improve the high speed performance of any transistor circuit, in terms of maximum sensitivity, for ICs that are affected by the process variation. The mismatch control is achieved by controlling the threshold voltage of the transistors via bulk-biasing techniques. This method is useful also for small input signals. The bulk voltages of the transistors are controlled to improve the circuit performance and to avoid process mismatches and process spread. As an additional measure, inductive peaking can be incorporated to increase the high-speed performance. In particular, at least one sensing transistor means is provided adjacent to at least one transistor means of the controlled circuit, and at least one reference transistor means is provided at a location

19 remote from the at least one transistor means of the controlled circuit. A predetermined bias voltage is applied to the at least one reference transistor means, and the bulk voltage is controlled based on a comparison of a sensed threshold voltage of the at least one sensing transistor means and a sensed threshold voltage of the at least one reference transistor means. Thereby, process variation can be compensated. Alternatively or additionally, an information indicating a relation between a frequency information and a desired threshold voltage of the at least one transistor means of the controlled circuit may be stored, and the bulk voltage may be controlled to an optimized value based on the stored relation with respect to a frequency of an input signal of the integrated circuit. It is to be noted that the description of the invention shall not be seen as limitation to the invention. Basically, the inventive principle of the present invention may be applied to any transistor bulk control. Moreover, any combination of the above first to fifth embodiments is covered by the scope of the present invention. In particular, an independent control of the bulk voltage of NMOS and PMOS bulk transistors is allowed. The digital control proposed in the second preferred embodiment may as well be incorporated to the circuits of the fourth and fifth preferred embodiments. The proposed latch works at low voltages and has the advantage of providing the same delay from CK to Q output and from D to Q output. The resulted function is a general-purpose building block, which can be employed in D flip-flops, registers, multiplexers, demultiplexers. One application of it is a high-speed prescaler which can be used for high frequencies, e.g. above the 10GHz range. The preferred embodiment may thus vary within the scope of the attached claims. Finally but yet importantly, it is noted that the term "comprises" or "comprising" when used in the specification including the claims is intended to specify the presence of stated features, means, steps or components, but does not exclude the presence or addition of one or more other features, means, steps, components or group thereof. Further, the word "a" or "an" preceding an element in a claim does not exclude the presence of a plurality of such elements. Moreover, any reference sign does not limit the scope of the claims.