250MHz Triple Differential Receiver/ Equalizer with I 2 C Interface

Transcription

1 5MHz Triple Differential Receiver/ Equalizer with I C Interface ISL599 The ISL599 is a triple channel differential receiver and equalizer optimized for RGB and YPbPr video signals. It contains three high speed differential receivers with programmable frequency compensation. The ISL599 features manual or automatic offset calibration and ±4dB of gain adjustment range with a resolution of.db. The ISL599 has a bandwidth of 5MHz and consumes only m from a ±5V supply in normal operation. When deasserted, the ENBLE pin puts the amplifiers into a low power, high impedance state, minimizing power when not needed and also allowing multiple devices to be connected in parallel, allowing two or more ISL599 devices to function as a multiplexer. The ISL599 can also directly decode the sync signals encoded onto the common modes of three pairs of Cat 5 cable (by an ISL59, EL454, or similar device) or it can output the actual common mode voltages for each of the three channels. The ISL599 is available in a Ld QFN package and is specified for operation over the full -4 C to +85 C temperature range. Features 5MHz -db bandwidth 5 djustable EQ bands: MHz, MHz, 6MHz, MHz, and khz rd-order lowpass filter at output with programmable corner ±4dB fine gain control with.db (7-bit) resolution Offset calibration minimizes output offset voltage Decodes H SYNC and V SYNC signals embedded in common mode I C interface with four unique addresses ±5V m Ld 5mm x 6mm QFN package pplications KVM monitor extension Digital signage General-purpose twisted-pair receiving and equalization High-resolution security video +5V -5V TWISTED-PIR RGB VIDEO RECEIVER ISL59 OR EL454 TRIPLE DIFFERENTIL VIDEO DRIVER UP TO m OF CT X CBLE TERMINTION NETWORK k.µf TERMINTION NETWORK TERMINTION NETWORK R P +5V R P +5V C BYPSS * R IN+ R IN - x G IN + G IN - B IN + B IN - DDR DDR V+ V- and THERML PD ISL599 * C BYPSS *See Power Supply Bypassing on x page for more information. R OUT G OUT B OUT R REF G REF B REF HS OUT /R CM VS OUT/G CM 75 x ISL599 ISL599 ISL599 or ISL599 VIDEO DELY LINE 74HC4 or SIMILR SYSTEM MICRO- CONTROLLER I C INTERFCE SCL SD ENBLE GND B CM NC FIGURE. TYPICL PPLICTION CIRCUIT September, FN7548. CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil mericas Inc.. ll Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. ll other trademarks mentioned are the property of their respective owners.

2 ISL599 Block Diagram R IN + R IN - G IN + G IN - B IN + B IN - Differential to Single- Ended Conversion + Common Mode Extraction CM R CM G CM B MHz Sync Decoding Equalizer MHz 6MHz MHz khz Gain (R) Gain (G) Gain (B) Noise Filter HS OUT/R CM VS OUT /G CM B CM R OUT G OUT B OUT R REF G REF ENBLE Control Logic B REF SD SCL I C Interface DDR DDR Pin Configuration DDR V- D V- R IN + R IN - G IN + G IN DDR SD ISL599 ( LD QFN) TOP VIEW SCL GND 9 THERML PD R REF 8 G REF GND 7 EXPOSED DIEPLTE SHOULD BE CONNECTED TO V- (-5V) R OUT V- R G OUT V+ G 9 V+ R V- G V+ B B IN B OUT Ordering Information PRT NUMBER (Notes,, ) PRT MRKING PCKGE (Pb-free) PKG. DWG. # B IN V- B V+ HS OUT /R CM VS OUT /G CM B CM ENBLE GND 4 6 B REF 5 ISL599IRZ 599 IRZ Ld QFN L.5x6C ISL599IRZ-EVLZ Evaluation Board NOTES:. dd -T* suffix for tape and reel. Please refer to TB47 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see device information page for ISL599. For more information on MSL please see techbrief TB6. FN7548. September,

3 Pin Descriptions ISL599 PIN NUMBER PIN NME PIN FUNCTION DDR Digital Input. I C ddress select bit, used with DDR to select the ISL599 I C address (see ISL599 Serial Communication on page ). Note: If power supply sequencing cannot be guaranteed, DDR must be held low during power-up. See Power Supply Sequencing on page for more information. V- D Power Supply Pin. -5V for internal digital logic (internal logic operates between GND and V- D ). Connect to the same -5V supply as V-. V- Power Supply Pin. -5V supply for analog core of chip, also tied to thermal pad. Connect to a -5V supply. 4 R IN + nalog Input. Red positive differential input 5 R IN - nalog Input. Red negative differential input 6 G IN + nalog Input. Green positive differential input 7 G IN - nalog Input. Green negative differential input 8 B IN + nalog Input. Blue positive differential input 9 B IN - nalog Input. Blue negative differential input V+ Power Supply Pin. +5V supply for analog core of chip. Connect to a +5V supply. HS OUT /R CM Output configuration (Note 4) = : Digital Output. Decoded Horizontal Sync signal Output configuration (Note 4) = : nalog Output. Red common-mode voltage at inputs VS OUT /G CM Output configuration (Note 4) = : Digital Output. Decoded Vertical Sync signal Output configuration (Note 4) = : nalog Output. Green common-mode voltage at inputs B CM Output configuration (Note 4) = : Digital Output. Logic low Output configuration (Note 4) = : nalog Output. Blue common-mode voltage at inputs 4 ENBLE Digital Input. Chip enable logic signal. V: ll analog circuitry turned off to reduce current. 5V: Normal operation. 5 GND Power Supply Pin. Ground reference for ISL599. This pin must be tied to GND. 6 B REF nalog Input. Blue channel analog offset reference voltage. Typically tied to GND. 7 V- B Power Supply Pin. -5V supply for blue output buffer. Connect to the same -5V supply as V-. 8 B OUT nalog Output. Blue output voltage referenced to B REF pin. 9 V+ B Power Supply Pin. +5V supply for blue output buffer. Connect to the same +5V supply as V+. V+ G Power Supply Pin. +5V supply for green output buffer. Connect to the same +5V supply as V+. G OUT nalog Output. Green output voltage referenced to G REF pin. V- G Power Supply Pin. -5V supply for green output buffer. Connect to the same -5V supply as V-. V- R Power Supply Pin. -5V supply for red output buffer. Connect to the same -5V supply as V-. 4 R OUT nalog Output. Red output voltage referenced to R REF pin. 5 V+ R Power Supply Pin. +5V supply for red output buffer. Connect to the same +5V supply as V+. 6 GND Power Supply Pin. Ground reference for ISL G REF nalog Input. Green channel analog offset reference voltage. Typically tied to GND. 8 R REF nalog Input. Red channel analog offset reference voltage. Typically tied to GND. 9 GND Power Supply Pin. Ground reference for ISL599. This pin must be tied to GND. SCL Digital Input. I C Clock Input SD Digital Input/Open-Drain Digital Output. I C Data Input/Output DDR Digital Input. I C ddress select bit, used with DDR to select the ISL599 I C address. Thermal Pad Thermal Pad Power Supply Pin. Connect to -5V supply plane with multiple vias to reduce thermal resistance and more effectively spread heat from the ISL599 to the PCB. NOTE: 4. Output Configuration is controlled via Configuration Register x, bit. FN7548. September,

4 ISL599 bsolute Maximum Ratings (T = +5 C) V+ = V+ R = V+ G = V+ B, V- = V- R = V- G = V- B = V- D Supply Voltage between V+ and V V Maximum bsolute Slew Rate of V+ and V ±V/µs Maximum Continuous Output Current per Channel ±m Power Dissipation See Power Dissipation on page Pin Voltages V- -.5V to V+ +.5V ESD Ratings Human Body Model (tested per JESD-4) V Machine Model (Tested per JESD-5) V Charged Device Model (Tested per JESDCC) V Latch Up (Tested per JESD78; Class II, Level ) m Thermal Information Thermal Resistance (Typical) θ J ( C/W) θ JC ( C/W) Ld QFN (Notes 5, 6) Storage Temperature C to +5 C Die Junction Temperature C Pb-Free Reflow Profile see link below Operating Conditions Temperature Range C to +85 C V+ Supply Range V to 5.5V V- Supply Range V to -5.5V CUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θ J is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB For θ JC, the case temp location is the center of the exposed metal pad on the package underside. IMPORTNT NOTE: ll parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T Electrical Specifications V+ = V+ R = V+ G = V+ B = +5V, V- = V- R = V- G = V- B = V- D = -5V, T = +5 C, all registers at default settings (equalizer stages set to minimum boost, noise filter set to max bandwidth, x gain mode, GIN DC = db), all analog inputs at V, auto offset calibration executed, R L = 5pF (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified. PRMETER DESCRIPTION CONDITIONS POWER SUPPLY Positive Supply Voltage (V+) Negative Supply Voltage (V-) Operating Current (I D +) Operating Current (I D -) Disabled Current (I D + DISBLED ) Disabled Current (I D - DISBLED ) MIN (Note 7) TYP MX (Note 7) V+ = V+ R = V+ G = V+ B V V- = V- R = V- G = V- B = V- D V Sum of currents into all V+ pins 4 m Sum of currents out of all V- pins, including thermal pad UNIT 5 m Sum of currents into all V+ pins ENBLE = V.5.5 m Sum of currents into all V- pins, including thermal pad ENBLE = V.5.5 m PSRR DC Power Supply Rejection Ratio 55 db C PERFORMNCE BW Full Power Bandwidth 5 MHz GIN MHz Maximum MHz ll three MHz filters set to maximum 6 db GIN MHz Maximum MHz MHz filter set to maximum 9.5 db GIN 6MHz Maximum 6MHz 6MHz filter set to maximum 7.5 db GIN MHz Maximum MHz MHz filter set to maximum. db GIN.MHz Maximum khz khz filter set to maximum.75 db GIN DC DC Gain djustment Range ±4 db f NOISE_MIN -db Corner Freq of Noise Filter, High Noise Filter Register = x 5 MHz f NOISE_MX -db Corner Freq of Noise Filter, Low Noise Filter Register = xf 5 MHz SR DIFF Output Slew Rate V IN = -V to +V V/ns THD Total Harmonic Distortion f = MHz,.7V P-P input sine wave dbc 4 FN7548. September,

5 ISL599 Electrical Specifications V+ = V+ R = V+ G = V+ B = +5V, V- = V- R = V- G = V- B = V- D = -5V, T = +5 C, all registers at default settings (equalizer stages set to minimum boost, noise filter set to max bandwidth, x gain mode, GIN DC = db), all analog inputs at V, auto offset calibration executed, R L = 5pF (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified. (Continued) PRMETER DESCRIPTION CONDITIONS BW CM Common Mode mplifier Bandwidth k 5pF load 4 MHz SR CM Common Mode Slew Rate V IN = -.5V to +.5V. V/ns INPUT CHRCTERISTICS CMIR Common-mode Input Range Differential signal passed undistorted. Effective headroom is reduced by the p-p amplitude of differential swing divided by. -./+4. V CMRR Common-mode Rejection Ratio Measured at khz 88 db Measured at MHz 58 db C INDIFF Differential Input Capacitance Capacitance between V INP and V INM.5 pf R INDIFF Differential Input Resistance Resistance between V IN + and V IN - (due to common mode input resistance) kω C INCM CM Input Capacitance Capacitance from V IN + and V IN - to GND. pf R INCM CM Input Resistance Resistance from V IN + and V IN - to GND 5 kω V INDIFF_P-P Max P-P Differential Input Range Delta V IN + - V IN - when slope gain falls to.9.9 V OUTPUT CHRCTERISTICS V OUT Output Voltage Swing ±.75 V I OUT Output Drive Current R L = Ω, V IN + - V IN - = ±V ± m V(V OUT ) OS Output Offset Voltage Post-offset calibration mv R(V CM ) CM Output Resistance of VCM_R/G/B (CM Output Mode) t khz.5 Ω Gain Gain x mode x mode ΔGain Channel-to-Channel Gain Mismatch x and x modes ± % O NOISE Integrated Noise at Output GND through 5Ω. m of Equalization (Nominal) m of Equalization 4 mv RMS SYNCOUT HI High Level output on VS/HS OUT k 5pF load, SYNC Output Mode V+ -.5 V SYNCOUT LO Low Level output on VS/HS OUT k 5pF load, SYNC Output Mode.4 V SCL, SD PINS f MX Maximum I C Operating Frequency 4 khz V OL SD Output Low Level V SINK = 6m.4 V V IH Input High Level V V IL Input Low Level.5 V V HYST Input Hysteresis.55 V I LEKGE Input Leakage Current ± µ t GLITCH Maximum Width of Glitch on SCL (or SD) Guaranteed to be Rejected 5 ns ENBLE, DDR, DDR PINS MIN (Note 7) V IH Input High Level V V IL Input Low Level.8 V I LEKGE Input Leakage Current ± µ NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design TYP.. MX (Note 7).5. UNIT V/V 5 FN7548. September,

6 ISL599 Typical Performance Curves 5 x x MGNITUDE (db) MGNITUDE (db) CODE 6 CODE 4 CODE CODE.. MGNITUDE (db) MGNITUDE (db) CODE CODE 7 CODE 6 CODE 5 CODE CODE 4 CODE CODE FIGURE 4. FREQUENCY RESPONSE vs MHz BITS 4: CODE. FREQUENCY (MHz) FIGURE 5. FREQUENCY RESPONSE vs MHz BITS 7:5 CODE F CODE F 9 MGNITUDE (db) MGNITUDE (db) CODE 7 FREQUENCY (MHz) FIGURE. FREQUENCY RESPONSE vs MHz BITS : FIGURE. NOMINL FREQUENCY RESPONSE WITH DEFULT SETTINGS. FREQUENCY (MHz) FREQUENCY (MHz) CODE. FREQUENCY (MHz) FIGURE 6. FREQUENCY RESPONSE vs MHz BITS 7: CODE FREQUENCY (MHz) FIGURE 7. FREQUENCY RESPONSE vs 6MHz BITS : FN7548. September,

7 Typical Performance Curves (Continued) ISL CODE F.5 CODE F MGNITUDE (db) 4 MGNITUDE (db)..5 CODE -.5 CODE -.. FREQUENCY (MHz) FIGURE 8. FREQUENCY RESPONSE vs MHz BITS 7:4 FIGURE 9. FREQUENCY RESPONSE vs khz BITS : -... FREQUENCY (MHz) MGNITUDE (db) CODE CODE B CODE F CODE CODE CODE 9-6 FREQUENCY (MHz) FIGURE. FREQUENCY RESPONSE vs LOW PSS FILTER BITS : 7 FN7548. September,

8 ISL599 Register Listing DDRESS REGISTER (DEFULT VLUE) BIT(S) FUNCTION NME DESCRIPTION x Device ID (read only) : Device Revision = initial silicon, = first revision, etc. 7:4 Device ID x = ISL599 x General Configuration (x) Output Configuration : H SYNC + V SYNC (like EL9 and ISL599) : V CM (like EL9 and ISL599) Nominal Gain : db (V/V) : 6dB (V/V) Power Down : Normal Operation : Low power mode, all amplifiers turned off x High djust (x) : MHz Stage b: Min boost b: Max boost 4: MHz Stage b: Min boost b: Max boost 7:5 MHz Stage b: Min boost b: Max boost x Mid djust (x) : 6MHz b: Min boost b: Max boost 7:4 MHz b: Min boost b: Max boost x4 Low djust (x) : khz b: Min boost b: Max boost 7:4 MHz b: Min boost b: Max boost x5 Noise Filter djust (x) : Noise Filter djusts -db frequency of noise filter at output x: Max frequency xf: Min frequency x6 Red Channel Gain (x4) 6: Red Gain x: -6dB x4: db x7f: +6dB Note: Due to gain trim at production test, the minimum guaranteed usable gain range is ±4dB. x7 Green Channel Gain (x4) 6: Green Gain x: -6dB x4: db x7f: +6dB Note: Due to gain trim at production test, the minimum guaranteed usable gain range is ±4dB. x8 Blue Channel Gain (x4) 6: Blue Gain x: -6dB x4: db x7f: +6dB Note: Due to gain trim at production test, the minimum guaranteed usable gain range is ±4dB. x9 Red Channel Manual Offset (x) (Default is auto-calibrated) 6: Red Offset x: -4mV Offset x7f: +4mV Offset (Output Referred) 7 Manual Offset Control (Red) : Offset is auto calibrated - value in bits 6: is ignored : Offset DC set to value in bits 6: x Green Channel Manual Offset (x) (Default is auto-calibrated) 6: Green Offset x: -4mV Offset x7f: +4mV Offset (Output Referred) 7 Manual Offset Control (Green) : Offset is auto calibrated - value in bits 6: is ignored : Offset DC set to value in bits 6: 8 FN7548. September,

9 ISL599 Register Listing (Continued) DDRESS REGISTER (DEFULT VLUE) BIT(S) FUNCTION NME DESCRIPTION xb Blue Channel Manual Offset (x) (Default is auto-calibrated) 6: Blue Offset x: -4mV Offset x7f: +4mV Offset (Output Referred) 7 Manual Offset Control (Blue) : Offset is auto calibrated - value in bits 6: is ignored : Offset DC set to value in bits 6: xc Offset Calibration Control (x) Start Cal Set to to initiate offset calibration. Bit is reset to when calibration is complete (in ~µs or less). Cal Mode : nalog inputs disconnected from external pins and internally shorted together during calibration. : nalog inputs remain connected to external circuitry during calibration. Useful for calibrating out system-wide offsets. External offsets of up to ~±6mV can be eliminated. Short Inputs : Normal operation : Inputs shorted together (independent of the Cal Mode bit) xd - x Reserved 7: Reserved Reserved. Do not write anything to these addresses. x Initialization 7: Initialization fter initial power on, write x6 to this register, followed by a write of x to this register. NOTE: ll registers are read/write unless otherwise noted. 9 FN7548. September,

10 ISL599 pplications Information ISL599 Overview Differential video signals sent over long distances of twisted pair wire encounter are increasingly attenuated as frequency and distance increase, resulting in loss of high frequency detail (blurring). The exact loss characteristic is a function of the wire gauge, whether the pairs are shielded or unshielded, the dielectric of the insulation, and the length of the wire. The loss mechanism is primarily skin effect. The signal can be restored by applying a filter with the inverse transfer function of the cable to the far end signal. The ISL599 is designed to compensate for losses due to long cables, and incorporates the functionality and flexibility to match a wide variety of loss characteristics. Power Supply Sequencing Power to the ISL599 s negative supply pins should be applied before the positive supply ramps. s shown in Figure, V- should reach -V before V+ reaches V. If this power supply sequence cannot be guaranteed, then the DDR pin must be held low during power-up until V- has crossed -V. V+ V- -V +V If this power supply sequencing requirement is not met and if DDR is high, there is a small chance that the ISL599 factory trim will become permanently corrupted. Power Supply Bypassing t > ms FIGURE. POWER SUPPLY SEQUENCING For best performance, all ICs need bypass capacitors across some or all of their power supply pins. The best high-frequency decoupling is achieved with a.μf capacitor between each power supply pin and GND. djacent supply pins (pins and, 9 and, and, and 5 and 6) can share the same decoupling capacitor. Keep the path to both pins as short as possible to minimize inductance and resistance. Pins and provide power to the internal equalizer, while supply pins between pin 7 and pin 5 provide power to the analog output buffers. For best performance, the equalizer supplies should be somewhat isolated from the buffer supplies. separate path back to the power source should be adequate. μf capacitor on each of the V+ and V- supplies provides sufficient low-frequency decoupling. The μf capacitors do not need to be particularly close to the ISL599 to be effective, but should still have a low-impedance path to the supply rails. In many mixed-signal ICs, separation of the analog and digital supplies and grounds is critical to prevent digital noise from appearing on the analog signals. Because the digital logic in the ISL599 is only active during a one-time configuration, the analog and digital supply pins (and grounds) can be connected together, simplifying PCB layout and routing. Input Termination The differential input signal from a Cat x cable should have a characteristic impedance of Ω and is therefore terminated by the two 5Ω resistors across the differential inputs, as shown in Figure on page. The 5Ω resistor and.µf capacitor connected to the midpoint keep the C impedance low at high frequencies, providing common-mode C termination while allowing the low-frequency component of the common mode (containing the embedded H and V sync signals) to move freely. The k resistor provides a higher-impedance DC path to ground, so the common mode voltage is set to V when no cable is connected. Device Initialization To ensure that the ISL599 functions properly, the following steps must be taken after initial power-up:. Ensure that the ENBLE pin is high.. Through the serial interface, write x6 to register x, then write x to the same register. This ensures that the DC gain of the device is accurate.. Perform an offset calibration by setting bit of register xc to. The bit is automatically resets to upon completion of calibration. If offset calibration is not performed, the ISL599 may have large DC offsets. Communicating with the ISL599 The ISL599 is controlled through the industry standard I C serial interface. djustments to the frequency response over five distinct frequency bands, gain and offset fine-tuning, and several other functions are made through this interface as described in the Register Listing starting on page 8. This level of control enables much more accurate and flexible response matching than previous solutions. The ISL599 also has an external Chip Enable (ENBLE) pin, allowing hardware control of whether the chip is operating or in a low-power standby mode. Programming the ISL599 for a Specific Cable and Length Determining the optimum settings for the ISL599 s multiple equalizer frequencies, gain, and low pass filter can initially seem quite challenging. To equalize any cable type of any length, transmit a step (a pure white screen works well, since the video in H SYNC region is black) and adjust the filters, starting at khz and working up to MHz, so that the response at the receive end is as flat as possible. Once the response is flat, the gain should be adjusted as necessary to compensate for the DC losses. This technique is not usually practical in the field, where the best solution is a lookup table for each cable type. Table shows the best values for a typical Cat 5 cable. FN7548. September,

11 ISL599 Length (m) Offset Calibration Historically, programmable video equalizer ICs have had large and varying offset voltages, often requiring external circuitry and/or manual trim to reduce the offset to acceptable levels. The ISL599 improves upon this by adding an offset calibration circuit that, when triggered by setting bit of I C register xc, shorts the inputs together internally, compares the R OUT, G OUT, and B OUT voltages to their corresponding R REF, G REF, and B REF voltages and uses a DC with a successive-approximation technique to minimize the delta between them (see Figure ). V IN + V IN - Reg When the ISL599 is first powered up, the offset error is undefined until an offset calibration is performed. The output offset voltage of the ISL599 also varies as the filter and gain settings are adjusted. To minimize offset, always perform an offset calibration after finalizing the filter and gain settings. n offset calibration only takes about μs, so offset calibrations can be performed after every register write without adding significant time to the adjustment process. This minimizes offset throughout the entire equalization adjustment procedure. Output Signals TBLE. Cat 5 LOOK-UP TBLE Reg Reg 4 Reg 5 Reg 6-8 x x x x x4 5 x x x x x4 5 x4 x x x x44 75 x5 x x x x44 x49 x44 x4 x x48 5 x69 x55 x5 x x48 5 x89 x75 x6 x x4c 75 x9 x86 x7 x4 x4c x96 x96 x8 x6 x5 5 x97 x7 x9 x8 x5 5 xb7 xb8 xb x9 x54 75 xd7 xc9 xc x x54 xf7 xe xd xc x58 INPUT BUFFER EQ ND GIN The R OUT, G OUT, and B OUT outputs can drive either a standard 75Ω video load in x gain mode or a 5Ω source-terminated load (75Ω in series at source end [ISL599 output pin], plus 75Ω termination to ground at receive end) in x mode. If the output of the ISL599 is going directly into an ISL599 or DC SR LOGIC OUTPUT BUFFER COMPRTOR FIGURE. OFFSET CLIBRTION (ONE CHNNEL SHOWN) V OUT V REF similar delay line, termination to ground is not necessary, however, a ~75Ω series resistor at each output pin will help isolate the outputs from the PCB trace capacitance, improving the flatness of the frequency response. When ENBLE is low, the R OUT, G OUT, and B OUT outputs are put in a high-impedance state, allowing multiple ISL599 devices to be configured as a multiplexer by paralleling their outputs and using ENBLE to select the active RGB channel. Common Mode and H SYNC /V SYNC Outputs In addition to the incoming differential video signals, the ISL599 also processes the common mode voltage on the differential inputs and can output the signal in one of two ways (as determined by the Output Configuration bit in register x). When the Output Configuration bit is set to (the default), the common mode input voltages are sent to comparators that decode the voltage into H SYNC and V SYNC signals according to the EL454/ISL59 standard encoding scheme shown in Figure and in Table on page. The H SYNC signal appears on the HS OUT /R CM pin, the V SYNC signal on VS OUT /G CM. The B CM output pin is held at a logic low (v). To minimize noise coupling into the analog section from the sync output drivers, the HS OUT and VS OUT outputs have limited current drive, and should be buffered by 74HC4 or similar CMOS buffers, as shown in Figure, before driving any significant loads (such as a VG cable). When the Output Configuration bit is set to, buffered versions of the three common mode input voltages are available on the R CM, G CM, and B CM pins. Making the raw common mode signal available allows for custom encoding schemes and/or transmission of analog signals on the video signals common mode..v.v.v.v.v.v.5v V.5V V TIME (.5ms/DIV) FIGURE. H ND V SYNC SIGNL ENCODING TBLE. H ND V SYNC DECODING BLUE CM GREEN CM RED CM V SYNC H SYNC RED CM GREEN CM BLUE CM H SYNC V SYNC.5V.V.V Low Low.V.V.5V Low High.V.V.5V High Low.5V.V.V High High FN7548. September,

12 Power Dissipation The ISL599 is designed to operate with ±5V supply voltages. The supply currents are tested in production and guaranteed to be less than 4m per channel. Operating at ±5V power supply, the total power dissipation is shown by Equation : V OUTMX PD MX = V S I SMX + V ( S - V OUTMX ) R L (EQ. ) Where: PD MX = Maximum power dissipation V S = Supply voltage = 5V I MX = Maximum quiescent supply current = 4m V OUTMX = Maximum output voltage swing of the application = V The term comes from the number of channels R L = Load resistance = 5Ω PD MX =.4W θ J required for long term reliable operation can be calculated. This is done using Equation : θ J = ( T J T ) PD= ( 46 C) W (EQ. ) Where: T J is the maximum junction temperature (+5 C) T is the maximum ambient temperature (+85 C) For a Ld QFN package in a proper layout PCB heatsinking copper area, C/W θ J thermal resistance can be achieved. To disperse the heat, the bottom heatspreader must be soldered to the PCB. Heat flows through the heatspreader to the circuit board copper, then spreads and converts to air. Thus the PCB copper plane becomes the heatsink. This has proven to be a very effective technique. separate application note that details the pin QFN PCB design considerations is available. ISL599 FN7548. September,

13 ISL599 ISL599 Serial Communication Overview The ISL599 uses the I C serial bus protocol for communication with its host (master). SCL is the Serial Clock line, driven by the host, and SD is the Serial Data line, which can be driven by all devices on the bus. SD is open drain to allow multiple devices to share the same bus simultaneously. Communication is accomplished in three steps:. The host selects the ISL599 it wishes to communicate with.. The host writes the initial ISL599 Configuration Register address it wishes to write to or read from.. The host writes to or reads from the ISL599s Configuration Register. The ISL599s internal address pointer auto increments, so to read registers x through xb, for example, one would write x in step, then repeat step three 8 times, with each read returning the next register value. The ISL599 has a 7-bit address on the serial bus, <a><a>b, where is fixed and a and a are the state of the DDR and DDR pins, respectively. This allows up to four ISL599 devices to be independently controlled by the same serial bus. To control more than four devices (or more than two, if DDR is tied low as discussed in Power Supply Sequencing on page ) from a single I C host, use a chip select signal for each device. For example, in the firmware, the host can fix the I C address to b for all devices, selecting the device to be communicated to by taking its DDR pin high while the DDR pins of all other devices remain low. The selected device recognizes its current address (b) and respond normally, while the remaining devices will have an address of b and therefore ignore the communication. This requires one additional GPIO for each ISL599, but it permits as many ISL59 devices to be controlled as desired, without any additional external logic. The bus is nominally inactive, with SD and SCL high. Communication begins when the host issues a STRT command by taking SD low while SCL is high (Figure 4). The ISL599 continuously monitors the SD and SCL lines for the start condition and does not respond to any command until this condition has been met. The host then transmits the 7-bit serial address plus a R/W bit, indicating if the next transaction is a Read (R/W = ) or a Write (R/W = ). If the address transmitted matches that of any device on the bus, that device must respond with an CKNOWLEDGE (Figure 5). Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a STOP command, where SD rises while SCL is high (Figure 4), or a second STRT command, which is commonly used to reverse data direction without relinquishing the bus. The I C spec requires that data on the serial bus must be valid for the entire time SCL is high (Figure 6). To ensure incoming data has settled, data written to the ISL599 is latched on a delayed version of the rising edge of SCL. When the contents of the ISL599 are being read, the SD line is updated after the falling edge of SCL, delayed and deglitched in the same manner. SCL SD STRT STOP FIGURE 4. VLID STRT ND STOP CONDITIONS SCL FROM HOST 8 9 DT OUTPUT FROM TRNSMITTER DT OUTPUT FROM RECEIVER STRT CKNOWLEDGE FIGURE 5. CKNOWLEDGE RESPONSE FROM RECEIVER FN7548. September,

14 ISL599 SCL SD DT STBLE DT CHNGE DT STBLE FIGURE 6. VLID DT CHNGES ON THE SD BUS Configuration Register Write Figure 7 shows two views of the steps necessary to write one or more words to the Configuration Register STRT Command ISL599 Serial Bus 4 R/W D7 D6 D5 D4 D D D D (Repeat if desired) DDR DDR Signals the beginning of serial I/O ISL599 Device Select ddress Write The first 7 bits of the first byte select the ISL599 on the -wire bus at the address set by the DDR and DDR pins. The R/W bit is a, indicating that the next transaction will be a write. ISL599 Register ddress Write This is the address of the ISL599 s Configuration Register that the following byte will be written to. ISL599 Register Data Write(s) This is the data to be written to the ISL599 s Configuration Register. Note: The ISL599 Configuration Register s address pointer auto-increments after each data write. Repeat this step to write multiple sequential bytes of data to the Configuration Register. Signals from the Host SD Bus Signals from the ISL599 S T R T STOP Command Serial Bus ddress aaaaaaa C K Register ddress C K Data Write* dddddddd C K S T O P Signals the ending of serial I/O * The Data Write step can be repeated to write to the ISL599 s Configuration Register sequentially, beginning at the Register ddress written in the previous step. FIGURE 7. CONFIGURTION REGISTER WRITE 4 FN7548. September,

15 Configuration Register Read Figure 8 shows two views of the steps necessary to read one or more words from the Configuration Register. ISL599 STRT Command Signals the beginning of serial I/O 7 6 ISL599 Serial Bus 5 4 STRT Command DDR DDR R/W ISL599 Device Select ddress Write The first 7 bits of the first byte select the ISL599 on the -wire bus at the address set by the DDR and DDR pins. R/W =, indicating that the next transaction will be a write. ISL599 Register ddress Write This sets the initial address of the ISL599 s Configuration Register for subsequent reading. Ends the previous transaction and starts a new one. ISL599 Serial Bus DDR DDR R/W ISL599 Serial Bus ddress Write This is the same 7-bit address that was sent previously, however the R/W bit is now a, indicating that the next transaction(s) will be a read. D7 D6 D5 D4 D D D D Signals from the Host SD Bus Signals from the ISL599 S T R T (Repeat if desired) STOP Command Serial Bus ddress aaaaaaa C K Register ddress C K R E S T R T Serial Bus ddress FIGURE 8. CONFIGURTION REGISTER RED ISL599 Register Data Read(s) This is the data read from the ISL599 s Configuration Register. Note: The ISL599 Configuration Register address pointer auto-increments after each data read: repeat this step to read multiple sequential bytes of data from the Configuration Register. Signals the ending of serial I/O Data Read* aaaaaaa dddddddd C K S T O P C K * The Data Read step may be repeated to read from the ISL599 s Configuration Register sequentially, beginning at the Register ddress written in the previous two steps. 5 FN7548. September,

16 Revision History ISL599 The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DTE REVISION CHNGE 9// FN7548. Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. For a complete listing of pplications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL599 To report errors or suggestions for this datasheet, please go to FITs are available from our website at 6 FN7548. September,

17 ISL599 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) X.75 C (E) N LEDS L N (N-) (N-) b (N/) D PIN # I.D. MRK TOP VIEW (N/). M C B (D) (N-) (N-) N 7 NE E B X.75 C PIN # I.D. 5 L.5x6C (One of Packages in MDP46) LED QUD FLT NO-LED PLSTIC PCKGE (COMPLINT TO JEDEC MO-) MILLIMETERS SYMBOL MIN NOMINL MX NOTES D 5. BSC - D.5 REF - E 6. BSC - E 4.5 REF - L b c. REF - e.5 BSC - N REF 4 ND 7 REF 6 NE 9 REF 5 Rev 9/5 NOTES:. Dimensioning and tolerancing per SME Y4.5M Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/) as shown. BOTTOM VIEW C SETING PLNE e. C C (c).8 C N LEDS & EXPOSED PD SEE DETIL "X" SIDE VIEW DETIL X (L) N LEDS For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 7 FN7548. September,

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