Internal Dynamics of IGBT Under Fault Current Limiting Gate Control

Transcription

1 Internal Dynamics of IGBT Under Fault Current Limiting Gate Control University of Illinois at Chicago Dept. of EECS 851, South Morgan St, Chicago, IL 667 Malay Trivedi, Vinod John *, Thomas A. Lipo, Krishna Shenai * GE - CRD 1 Research Circle Schenectady, NY1239 john@crd.ge.com University of Wisconsin - Madison Dept. of ECE 1415 Engineering Dr., Madison, WI 5376 lipo@engr.wisc.edu Abstract - With the advent of high power high voltage IGBTs, it is feasible to use sophisticated gate drive circuits to obtain improved switching performance and ruggedness. Shortcircuit and over-current fault protections are critical issues in gate drive circuits for high power converters. This paper evaluates the effect of gate control to limit the fault current in an IGBT in terms of its internal dynamics. The internal dynamics are analyzed using a two-dimensional device simulator. The effects of short-circuit and over-current faults in an IGBT power converter are studied by examining the fault characteristics over a range of fault inductance values. This study highlights the advantages of reduced fault current level, reduced power dissipation, and improved ruggedness that can be gained by the fault current limiting gate protection techniques. The simulation studies match trends observed in experimental results. Collector de-saturation voltage and Gate signal Control circuit Collector current estimation and de-saturation voltage detection circuit Pre-charge Voltage Control Circuit Drive stage collector voltage detection Gate resistor D 1 Q D 2 Z Kelvin emitter Power collector Power emitter I. INTRODUCTION C fclc Z fclc The design of insulated gate bipolar transistors (IGBT) involves resolution of the trade-off between on-state voltage, switching time, and safe operation area (SOA). Reliability of the switch, defined in terms of the SOA, is determined by the ability of the device to withstand stressful switching situations, such as a short circuit. Short circuit situations across a device are classified in two types. The Hard Switched Fault (Type I) is said to occur when the switch turns on with full bus voltage across itself. Fault Under Load (Type II) occurs when the device is in on-state. Several circuits have been proposed to improve the short circuit performance of the IGBT under both conditions [1-3]. Considering the importance of these faults on IGBT performance, study of device internal dynamics during fault can be used as a tool for gate drive design. Investigations of the internal short circuit dynamics of IGBTs reported thus far have focussed on the operation of the device under normal gate driving conditions [4,5]. These device simulation studies were primarily concerned with the way the IGBT was destroyed. However, the impact of the protection circuits on the internal dynamics of the IGBT has not been analyzed so far. This study shows that the approach required for IGBT protection differs from that for MOSFETs because of bipolar phenomena occurring within the IGBT. GND Fig. 1. Detailed schematic of the FCLC used in the IGBT gate drive V DC 4V Gate drive circuit R g V gg Short circuit control switch Variable fault inductance (L f ) C fclc S fclc L g Z fclc G FWD C E load 25A DUT Fig. 2. Simplified circuit used to simulate the IGBT characteristics with a fault current limiting gate drive.

2 v ce i c i g (a) (b) Fig. 3. Fault characteristics of an IGBT simulated under conditions of varying fault inductance. The values of the fault inductance are 1nH, 5nH, and 1nH. A two dimensional device simulator, ATLAS TM, was used to obtain an accurate physical model of the device [6]. The input to the simulator is the 2D geometry and doping profile of the IGBT and the material characteristics of Si. External circuit components can be added to this physical device model. Figure 1 indicates the functional diagram of the Fault Current Limiting gate drive control Circuit (FCLC) used to protect the IGBT. Detailed operation of the circuit components is discussed in [3]. Considering that 2-D mixed device and circuit simulations are complex and time consuming, the FCLC was greatly simplified and only the essential components were retained for the simulation study to reduce computational load. The external circuit used for 2-D simulations is shown in Fig. 2. The reduced behavioral circuit simplifies the topology without altering the switching stress experienced by the device. II. IGBT SHORT-CIRCUIT PERFORMANCE This section reports the internal dynamics of the IGBT under short-circuit stress without the FCLC circuit. In practical applications, the short circuit fault involves a parasitic inductance that might appear, for instance, due to long cables that connect the power converter with the load. This necessitates a study of the short circuit performance of the device in presence of circuit inductance. An experimental and numerical study was carried out to study device performance under Hard Switched Fault (HSF) short circuit conditions. In a voltage source converter, an HSF situation can occur when the IGBT turns-on with full bus voltage across itself and the only current limiting would be the parasitic inductance of the DC link power circuit. Another situation where such fault can occur is when the load has a short circuit and the power converter is switched on. The fault inductance is much higher in the latter case. The fault inductance was varied from 1nH to 1.5µH in the simulation study. At the lower end, this represents the package inductance of the device, while the upper end represents the inductance associated with long cables used to connect the load. Typical short-circuit performance of the IGBT under conditions of varying fault inductance is illustrated in Fig. 3. In all cases, it is observed that the device current rises initially in a rapid manner. After achieving a maximum value, the current starts decreasing, primarily due to temperature rise and decrease in carrier mobility in the MOS channel. However, it is observed that the peak current spike depends on the fault inductance. This is because the gate voltage tends to increase during fault conditions at higher fault inductance, as explained below. Fig. 4 plots the variation in peak short circuit current with inductance, revealing a curve with a bell-shaped nature. The gate resistance recommended by the manufacturer is used for the study. The applied positive on-state gate voltage is 15V. When the IGBT is turned on with very low fault inductance the current rise-time is solely determined by the device. The IGBT collector voltage stays close to the dc bus voltage (Fig. 3 (a)), and there is no increase in gate voltage due to the Miller capacitance. As the fault inductance is increased, the current ramp rate induces a voltage across the inductor. Once the device current reaches close to the maximum, the inductive voltage drop disappears. The imposed dv ce /dt across the device is transferred to the gate through the Miller capacitance. This instantaneous rise in the gate voltage leads to further rise in the collector current. The change in v ce once the current peak is reached increases with fault inductance. This leads to an initial increase in the peak fault current with inductance.

3 Current 6 55 Ic_p Vge_p Voltage temp. [K] 7 6 5,, Inductance [nh] Fig. 4 Influence of fault inductance on short circuit current and gate voltage Fig. 6. Maximum temperature within the IGBT cell as fault proceeds. Three cases of fault inductance - 1nH, 5nH, and 1nH are shown on the plot temp. [K] without FCLC with FCLC Fig. 5. The BJT and MOS components of IGBT collector current under hard switched fault. The three cases correspond to fault inductance of 1nH, 5nH, and 1nH. At much larger values of fault inductance, the inductance controls turn-on di c /dt rather than the device itself. The device current rises towards its saturation value at a rate determined by the inductance. The voltage across the device starts rising once the device current saturates. Since the device makes a smooth transition from linear to saturation region, the dv ce /dt is lower for the case of very large fault inductance values. Correspondingly, the gate voltage rise across the device caused by the Miller capacitance is also reduced. This leads to a reduction in the peak fault current. Fig. 4 also plots the peak gate voltage as a function of inductance. The maximum current spike appears for the value of inductance that barely requires the entire dc bus voltage to support the turn-on di c /dt of the IGBT. The IGBT operates as a bipolar transistor with base current supplied by a MOSFET [7]. The and components of the IGBT current under HSF conditions, with Fig. 7. Effect of FCLC on maximum temperature within the IGBT cell. varying fault inductance are plotted in Fig. 5. When the current is rising, and rise in accordance with the gain of the intrinsic bipolar transistor of the IGBT. Poor current gain of the bipolar transistor is evident from Fig. 5. Once the device saturates, the voltage across the device starts rising rapidly. This voltage is supported by an expanding depletion that shrinks the quasi-neutral base. Reduced effective base width of the bipolar transistor results in a corresponding rise in bipolar current gain, and a further rise in the hole current as shown in Fig. 5. As the current rises, the increase in gate voltage due to the Miller capacitance initially raises the current supplied by the MOS channel. The MOS current eventually starts falling due to reduced mobility with rising temperature. The peak temperature in the device as the fault proceeds is plotted in

4 v ce i c time (µs) C fclc = 3nF C fclc = 1nF time (µs) time (µs) (a) (b) C fclc = 47nF Fig. 8. IGBT fault current limiting characteristics (a) for different values of C fclc. The cases are 3nF, 1nF, and 47nF. (b) and components for the different values of C fclc. Fig. 6. It shows that the device internal temperature reaches about 8K in 2.5µs. The different fault inductance did not make any substantial difference for the temperature rise time in the IGBT. However, if the power dissipation in the IGBT is reduced due to the collector voltage staying closer to the on-state saturation voltage due to very large fault inductance, then the rise time for temperature is increased. A concern with higher peak fault current is that a turn-off command given under the high current density at the peak current conditions can damage the device. III. FAULT CURRENT LIMITING CIRCUIT A fault under load (FUL) short circuit is known to be more stressful on IGBTs than HSF because of the higher peak fault currents[8]. The FUL situation occurs when the device is in the on-state. If the peak fault current is beyond the short circuit safe operating area and a modulation command is given to turn-off the device, then there can be inductive turn-off failure [9,1]. It has also been shown that having an intermediate clamp voltage level prevents IGBT failure when gate turn-off occurs before the IGBT voltage desaturates [11]. The main aim of the fault current limiting circuit (FCLC) shown in Fig. 1 is to limit the gate voltage under fault and thus limit the power dissipation in the device. Appearance of the fault drastically increases the power dissipation in the device, and associated failure because of thermal runaway, as shown in Fig. 7. The FCLC limits collector current by reducing the gate voltage under fault conditions, so that the device de-saturates rapidly and clamps the fault current to a lower level. However, it has been a challenge to limit the initial peak fault current in IGBTs when compared to MOSFETs, especially under FUL conditions. It has been shown that a combined capacitor (C fclc ) and Zener based FCLC is most effective in limiting the peak fault current in the IGBT [3]. This section shows that the FCLC can effectively extend the short circuit handling capability of the device. Upon detection of a fault, C fclc and the zener rapidly clamp the gate voltage to a lower level, thus limiting the fault current. The transient performance of the IGBT on appearance of a fault is sensitive to the choice of the capacitor (C fclc ) in the FCLC. Fig. 8(a) shows the collector voltage, collector current and gate voltage and Fig. 8(b) shows the electron and hole current components within the IGBT for different values of

5 i c nH 4.5µH i c nF 2nF nH v ce µH v ce nF 1-1 2nH 4.5µH 1-1 2nF Fig. 9. Hard switched fault test results for Toshiba MG1Q2YS4 for various values of fault inductance as follows:.2, 2.5, 4.5µH. Other conditions are: T = 24 o C, V dc = 45V, V ge = 15V. C fclc. The internal dynamics can be used to explain the high performance that can be obtained from the FCLC shown in Fig. 1. On appearance of a short circuit fault, the gate voltage is designed to drop from 15V to 9V and the collector current is limited to the saturation current corresponding to 9V. If there is no protection circuit, the device fails in less than 5µs at an on-state gate voltage of 15V. With the FCLC, the device can easily withstand more than 15µs of short circuit stress (Fig. 7), resulting in considerable enhancement of device robustness. The effect of the Zener (Z fclc in Fig. 1) is to vary the level of the steady state fault current in the IGBT. This can be explained in terms of the steady state v ce versus i c characteristics of the IGBT. The influence of the capacitor in the FCLC (C fclc ) on the transient performance of the IGBT under FUL conditions shows a more complex behavior. When the C fclc is much smaller in magnitude than the IGBT input capacitance (C iss ), it charges up rapidly and the gate voltage is quickly clamped at 9V, as can be observed from the gate voltage waveform in Fig. 8(a). The rising device voltage induces additional hole current resulting in a high current spike almost three times the clamped fault current in magnitude, which is show in Fig. 8(b) for the case of small C fclc. A similar large transient current spike also occurs in the absence of C fclc. Hence, if C fclc is too small compared to C iss the current spike is not effectively suppressed. The waveforms corresponding to C fclc much Fig. 1. Test results for Toshiba MG1Q2YS4 under variation of capacitance, C fclc. Fault under load with selected capacitance as follows: 1, 3, 6, 1, 2nF. Pre-charge level of C fclc is at 4.8V. Other conditions are: Fault inductance = 2nH, T = 24 o C, V dc = 45V, V ge = 15V. larger than C iss are shown in Fig. 8(b). On appearance of a fault, gate voltage abruptly falls below the threshold voltage. This cuts off the MOS channel that provides base current to the internal bipolar transistor. The device then starts turning off with the characteristic hard-switching turn-off characteristics. The gate voltage continues to rise as C fclc charges up slowly. The electron current turns on again once the gate voltage rises above the threshold voltage. The collector current rises and attains the clamped fault current level. In this case, the MOS channel is turned on again after the device turns off. This situation is undesirable because the turning off of the fault current and turning the IGBT back on again can cause high device stress and generate considerable noise in the circuit. If the value of C fclc is chosen such that the MOS channel turns on just as the device is turning off, it is possible to eliminate the current spike without spurious device turn-off. This happens when C fclc is comparable to C iss, and the electron and hole current components for this case are shown in Fig 8(b). In this case the gate voltage is momentarily brought below the threshold voltage during the collector voltage rise time. This allows the hole component of the current to flow till the collector voltage reaches the dc link voltage and to the sweep out of carriers from the drift region of the IGBT. When the gate voltage comes back above the threshold voltage, the collector current will correspond to the

6 reduced gate voltage level of the FCLC. Thus the initial peak in the fault current is drastically reduced. Also the power dissipation in the device is reduced because both the peak and the clamped fault current levels are reduced compared to the case where there is no FCLC. The increase in the peak fault current level as the fault inductance is increased form 2 nh to 4.5 µh can be observed in Fig. 9. Experimental results with variation of C fclc are shown in Fig. 1. The same decrease in the peak fault current that is observed in the simulation as C fclc is increased can also be seen in the experimental results. The IGBTs used for the experiment and simulation were of comparable ratings. The simulation had a simplified equivalent circuit with no parasitics. Hence, only trends in the performance characteristics are studied. These show good qualitative agreement with measured results. IV. CONCLUSIONS In conclusion, the internal dynamics of an IGBT with fault current limiting circuit are studied with the help of measurements and 2-D simulations. The IGBT overcurrent and short circuit fault conditions can lead to severe device stress and high power dissipation. A fault current limiting circuit can be used to reduce the power dissipation and the peak fault current under such conditions. In this paper, the effect of the fault inductance has been studied under hard switched fault conditions. It has been shown that the peak fault current increases initially as the fault inductance is increased. Fault under load condition is a severe fault situation based on the peak fault current. The combination of the capacitor and the zener in the fault current limiting circuit can effectively limit the peak fault current. This has been explained in terms of the electron and hole current flow in the IGBT. The simulation studies replicate the trends observed in experimental results. REFERENCES [1] R. Chokhawala and G. Castino, IGBT fault current limiting circuit, IEEE-IAS Conf. Rec., 1993, pp [2] R. Chokhawala and S. Sobhani, Switching voltage transient protection schemes for high current IGBT modules IEEE-APEC Conf. Rec., 1994, pp [3] V. John, B. S. Suh, and T. A. Lipo. Fast-clamped short-circuit protection of IGBTs, IEEE Trans. Ind. Appl., vol. 35, no. 2, pp , [4] H. Hagino, J. Yamashita, A. Uenishi, and H. Haruguchi, An experimental and numerical study on the forward biased SOA of IGBTs, IEEE Trans. Electron Devices, vol. 43, no. 3, pp. 49-5, [5] M. Trivedi and K. Shenai, Investigation of the short circuit performance of an IGBT, IEEE Trans. Electron Devices, vol. 45, no. 1, pp , [6] ATLAS Users Manual, Silvaco International, Santa Clara, [7] H. Yilmaz, W. R. VanDell, K. Owyang, and M. F. Cjang, Insulated gate transistor modeling and optimization, IEEE IEDM Tech. Dig., 1984, p [8] H.G. Eckel and L. Sack, Optimization of the shortcircuit behaviour of NPT-IGBT by the gate drive, EPE Conf. Rec., pp , [9] M. Trivedi and K. Shenai, IGBT dynamics for clamped inductive switching, IEEE Trans. Electron Devices, vol. 45, no. 12, pp , December [1] M. Hierholzer, R. Bayerer, A. Porst, and H. Brunner, Improved characteristics of 3.3 kv IGBT modules, PCIM Conf. Rec., 1997, pp [11] A. Bhalla, S. Shekhawat, J. Gladish, J. Yedinak, and G. Dolny, IGBT behavior during desat detection and short-circuit fault detection, Proc. IEEE ISPSD, 1998, pp