Emulation of junction field-effect transistors for real-time audio applications

Transcription

1 This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Emulation of junction field-effect transistors for real-time audio applications Diego Hernandez 1a and Jin Huang 2b 1 Department of Mechanical and Aeronautical Engineering Feng Chia University, Taichung, Taiwan 2 Department of Mechanical and Computer-Aided Engineering Feng Chia University, Taichung, Taiwan a) p @fcu.edu.tw b) jhhuang@fcu.edu.tw Abstract: This work presents a nonlinear model for Junction Field-Effect Transistors (JFET) that is suitable for audio emulations in real-time. The model is implemented by using Wave Digital Filters (WDF), which offer accurate and real-time capability on digital processors. As emulation examples, a common source amplification stage and an electric guitar preamplifier are implemented in real-time in a reconfigurable Field Programmable Gate Array. For verification purposes, the WDF simulations were compared with the ones obtained by SPICE circuit analysis software. It is demonstrated how the JFET model and the emulation examples accurately work in real-time, matching the harmonic content of the reference SPICE simulations. Keywords: circuit simulation, JFET, nonlinear system, wave digital filters Classification: Electron devices, circuits, and system References IEICE 2016 DOI: /elex Received March 22, 2016 Accepted May 6, 2016 Publicized May 26, 2016 [1] J. Pakarinen and D. T. Yeh: Comput. Music J. 33 [2] (2009) 85. DOI: /COMJ [2] D. T. Yeh, J. S. Abel, and J. O. Smith: Audio Speech Lang. Process. IEEE Trans. On, 18 [4] (2010) 728. DOI: /TASL [3] D. T. Yeh: Audio Speech Lang. Process. IEEE Trans. On 20 [4] (2012) DOI: /TASL [4] V. Välimäki, J. Pakarinen, C. Erkut, and M. Karjalainen: Rep. Prog. Phys. 69 [1] (2006) 1. DOI: / /69/1/R01 [5] R. Rabenstein, S. Petrausch, A. Sarti, G. De Sanctis, C. Erkut, and M. Karjalainen: IEEE Signal Process. Mag. 24 [2] (2007) 42. DOI: /MSP [6] Fettweis: Proc. IEEE 74 [2] (1986) 270. DOI: /PROC [7] D. T. Yeh and J. O. Smith: Proceedings of the Digital Audio Effects (DAFx 08) [1] (2008) 1. [8] R. C. D. Paiva, S. D Angelo, J. Pakarinen, and V. Valimaki: IEEE Trans. Circuits Syst. II Express Briefs 59 [10] (2012) 688. DOI: /TCSII

2 [9] S. D Angelo, J. Pakarinen, and V. Valimaki: IEEE Trans. Audio Speech Lang. Process. 21 [2] (2013) 313. DOI: /TASL [10] Pakarinen and M. Karjalainen: IEEE Trans. Audio Speech Lang. Process. 18 [4] (2010) 738. DOI: /TASL [11] R. C. D. de Paiva, J. Pakarinen, V. Välimäki, and M. Tikander: EURASIP J. Adv. Signal Process [1] (2011) DOI: /2011/ [12] Fiedler and H. Grotstollen, IEEE Trans. Ind. Appl. 33 [1] (1997) 49. DOI: / [13] Fettweis: USA Patent US A, (1976). [14] G. Busatto: IEEE Industry Applications Society Annual Meeting 2 (1991) 1456 DOI: /IAS [15] National Instruments: CompactRIO 1 Introduction The modeling of analog systems is a vibrant field of study with extensive research published in recent decades. A large body of research focuses on musical applications and emulation of analog electronics, e.g., synthesizers, valve amplifiers or musical instruments [1, 2, 3, 4, 5]. These emulations allow the implementation in digital devices of obsolete, heavy, expensive or high current consumption electronic devices that still have a high market demand. An electric circuit can be represented by the Kirchhoff method with the pair of variables current and voltage, where local equations define the elements and global equations define how the elements connect to each other. Using a linear transformation, the Wave Digital Filter (WDF) method substitutes the pair of Kirchhoff variables with a pair of digital waves [6], so that the analog elements become represented by two variables and one port resistance. Among electric modeling techniques, some focus on solving differential equations, state-space or nodal analysis; however, they are not efficient for the implementation of nonlinear systems in real-time, where the user need to sense the output as immediate. In WDF method, the discretized input signal is processed sample by sample in time domain, enabling an efficient real-time modeling on digital signal processors. Therefore, WDFs have been widely used to emulate diodes [7], operational amplifiers [8], vacuum tubes [9, 10], audio transformers [11], among other analog electric systems [12]. Junction Field-Effect Transistors (JFET) are commonly used in audio and musical applications. Due to their nonlinear behavior, they are good candidates for applications where certain amount of distortion at the output is desired. This work presents a JFET nonlinear WDF model that is suitable for analog audio emulations in real-time. The proposed structure is modular, allowing the connection of different type of components to the transistor and several stages in cascade. As emulation examples, the model is included in a common source amplification stage and a guitar preamplifier, which are both implemented in real-time in a reconfigurable Field Programmable Gate Array (FPGA). For verification, the WDF emulations are first validated via SPICE circuit simulation software. Then, when the emulations run in real-time, they are verified by acquiring and analyzing 2

3 the signals from the FPGA input and output modules via data acquisition system. This work is organized as follows. First, a general introduction for WDF theory is given. This is followed by a description of the WDF system implementation. Next, the JFET model and the application examples are presented. Finally, conclusions and future work is addressed. 2 Wave Digital Filters WDFs are a class of digital filters that offer a real-time simulation of systems expressed as analog electric circuits. The electric variables voltage (v) and current (i) can be expressed as the wave variables [13] a v R b v R where a is the incident (incoming) wave and b is the reflected (outgoing) wave. R p denotes the port resistance, which must be a positive value. p p i i (1) 2.1 Elements and adaptors Basic electrical elements can be represented as one-port WDF elements. Each port has two terminals, one for incident waves and one for reflected waves. Additionally, there is a parameter for the port resistance. The electric components used in this work are shown in Table I, where R is the electric resistance [Ohm], C is the capacitance [F], v is the voltage [V], i is the current [A] and F s is the sample rate [Hz]. Table I. WDF Elements Element Dataflow Block Resistor (R) Capacitor (C) Voltage (Vs) Series Junction Parallel Junction 3

4 The electric topology of the analog circuit is implemented by adaptors, which are multi-port WDF elements that connect one-port elements and implement their correct impedance coupling. The series and parallel circuit topology is typically defined as three-port elements, and the circuit can be represented as a binary tree. Table I shows the outgoing waves and port resistance dataflow for the three-port series and parallel adaptors. 2.2 Computational scheduling The waves are first propagated from the leaves to the root. After arriving at the root element, the waves are propagated back to the leaves, and the entire process is repeated for the next sample. In the representation, the symbol Ⱶ indicates the matched or reflection-free port, where the incident waves do not depend on the reflected waves. The port resistances between the root and the adapted port should be equal, which requires defining the root element outgoing wave. If the root element is a resistor, the reflecting wave b can be calculated by expressing the Ohm s law relation (I=V/R) in terms of wave variables b R R p a (2) R R 2.3 Nonlinearities Nonlinear elements are defined by expressing their functions in terms of wave variables and solving the reflected waves. The port resistance becomes a function of the wave variables, but the wave variables in turn depend on the port resistance. Iterating can solve this problem, but the rest of the circuit port resistances must to be updated. If the nonlinear element is placed as the root element, the nonlinearity can be solved by local iteration without propagation to the rest of the binary tree. Analog components commonly have several nonlinearities. In practice, extra nonlinearities can be added if components are connected by delay elements, which can easily cause stability problems in certain conditions. Aliasing is a common problem, and applying oversampling factors may be important. p 3 WDF JFET model The JFET is a semiconductor that is widely used for analog low-signal amplification. JFETs have an n-type or p-type channel and three terminals: the drain (D), the source (S) and the gate (G). By applying a voltage to the gate terminal, the current that flows through the source and drain can be controlled. The output characteristic for an n-channel JFET can be defined in three working regions as I 0 for V V 0 (3) D 2 GS p V 1 GS I D IDSS for 0 VGS Vp VDS (4) Vp 4

5 I D IDSS GS p DS DS p I V V V V for 0 VDS VGS Vp (5) V The gate-source voltage (V GS ) at which the channel is switched off is known as the pinch-off voltage (V p ). When V GS is lower than V p, the JFET is in the cut-off region, and there is no drain current (I D ). I DSS is the drain-source saturation current and is obtained at zero V GS. When V GS is between V p and V DS, the JFET operates in the saturation region, where a variation in V DS results in a nearly linear change in I D, meaning that the saturation region can be considered linear. If V GS continues to increase, the JFET enters the resistance region, where an increase in V DS does not result in a further increase in I D. Traditional JFET models, such as the ones used in Spice simulation software [14], can include channel-length modulation, capacitances, resistances, and temperature coefficients, among other parameters. These models can be further simplified for the audio applications covered in this work. As shown in Fig. 1, a JFET can be represented as a current source (I D ) controlled by voltage (V GS ). Because I G is very small (I G 0), the input port (gate) can be considered as an open circuit. Additionally, the parallel resistor of the current source is very large and can be omitted. Fig. 1. Simplified equivalent circuit of a JFET. 3.1 WDF model As illustrated in Fig. 2, the JFET is modeled in the WDF domain as a three-port block element. This block is composed of the nonlinear resistor R NL, a series adaptor, a resistor, two delay units and three voltage probes. The voltages probes obtain V S, V G and V DS from the corresponding incoming and outgoing waves (a and b respectively) as V=(a-b)/2. In order to use this JFET block in WDF circuit emulations, it is also necessary to add extra components for the gate, source and drain circuits, as is indicated in the emulation examples. Fig. 2. WDF structure of the nonlinear JFET. 5

6 In the JFET block, the nonlinear drain-to-source resistance is calculated as R NL =V DS /I D. V DS is obtained as the voltage over R NL and delayed one sample to avoid a delay-free loop inside the block. The current I D is then evaluated by using Eq. (3), (4) and (5). To avoid an undefined value due to a zero division, I D is defined as a very small value in the cut-off region. The gate-to-source voltage fed to R NL is calculated as V GS =V G -V S, where V S is delayed one sample. V G is obtained over a high resistance value resistor placed at the input, and V S is obtained from the incoming and outgoing ports connected to the external source circuit. The gate voltage V G is read directly from a large value resistance placed at the input of in the block. This resistor can be placed in series with the nonlinear element, combining all elements of the circuit in the same binary tree. However, to increase the performance and versatility of the model, V G is obtained by placing the resistor as an element of a preceding tree (gate circuit). This separation allows computing several parts of the circuit separately, to avoid long wave propagation and to connect several JFET stages in cascade. In order to solve the nonlinearity by local iteration, the nonlinear resistor R NL is then placed as root element, making all the adapted ports point towards this element. 3.2 Output characteristics The output characteristic curves of a transistor represent the current I GS as a function of the voltage V DS at different V GS values, being a useful tool to design the polarization circuit. Fig. 3 shows the matching of the output characteristics obtained from WDF simulation and the ones numerically calculated. In the simulation, the electrical characteristics of the transistor are I GS = 0.6 ma and V P = -0.8 V. For low V DS, the current I GS rises rapidly and becomes almost constant when V DS reaches the V P value. The horizontal lines show that a change in V D has no effect on I DS, due to the high output resistance in this region. Fig. 3. Output characteristics of the JFET and bias point of the amplification stage. 4 WDF implementation The WDF elements and adaptors are created by defining their reflected waves and port resistances as a function of the incident waves, as shown in Table I. The 6

7 resulting dataflow codes can be grouped to appear as blocks to create a modular method for programming the WDF binary tree. The real-time emulations are implemented in a reconfigurable FPGA with 40 MHz time base [15], where the input and output is sampled at 51.2 khz. To verify the accuracy of these emulations, signals from the FPGA input and output modules are analyzed via data acquisition system. Oversampling is a common method to obtain high frequency accuracy in nonlinear WDF simulations. However, in the real-time implementations it is necessary to consider the hardware limitations. For the application examples presented in this work, the FPGA memory allows to apply an oversampling factor of three. 5 JFET amplification stage emulation JFET small signal amplifiers are commonly implemented as common source class A amplifiers similar to the one depicted in Fig. 4. The input voltage is amplified, phased inverted and distorted when reaches nonlinear regions. Fig. 4. Schematic of a common source JFET class A amplifier. In class A amplification, the transistor conducts the entire cycle of the input signal, being necessary a bias voltage to let the signal swing between zero and the supply voltage (V DD ). The bias voltage can be established by using self-bias with the resistors R G, R D and R S. The operating point is determined by applying a voltage drop over the gate to source junction. R G connects the gate to the ground, R D determines the value of I D and R S provides the negative bias for the gate to source junction. Fig. 5 shows a JFET (I DSS = 0.6 ma and V p = -0.8 V) class A amplifier with R G = 1 MΩ, R D = 15 kω, and R S = 1.5 kω. As shown in Fig. 3, these resistance values give the bias point V DSQ = 5.5 V. In the simulation, the input voltage signal is generated by the voltage source V IN, and the output is obtained at the load resistor R L. Fig. 5. WDF tree of the JFET class A amplifier. 7

8 The JFET amplifier circuit is mapped to the WDF domain as depicted in Fig. 5. The input signal is generated in a voltage source element with a negligible series resistance, and the output is obtained by computing the voltage over the load resistor element. Fig. 6 shows the parity of the Spice simulation (denoted as SPICE ) and the WDF simulation oversampled 20 times (denoted as WDF ) output signals, obtained by a 1 khz sinusoidal stimulus at several input amplitudes. It can be observed that the clipping generated in the resistance region (negative cycle) is softer than that generated in the cut-off region (positive cycle). Fig. 6. Time domain output signal of the JFET class A amplifier at several amplitudes as shown. Fig. 7. Harmonic content of the JFET class A amplifier stage output signal. To verify the WDF model and real-time implementation over the audible frequency range, Fig. 7 compares the harmonic content (obtained by applying a 1 V peak swept step stimulus) of the Spice simulation (denoted as SPICE ), the WDF simulation oversampled 20 times (denoted as WDF (x20) ), the WDF simulation oversampled three times (denoted as WDF (x3) ), and the real-time implementation oversampled three times (denoted as FPGA (x3) ). The results show that the WDF simulation and the real-time implementation match over all the considered frequency range when using the same oversampling rate. Comparing the three- and 20-times oversampled simulations; it can be observed how the 8

9 aliasing effect degrades the signal at high frequency, keeping a good accuracy for the lower frequency. Although the JFET SPICE model contains extra parameters [14] (channel-length modulation, capacitances, resistances, temperature ) that are not considered in the WDF model, the frequency responses were made nearly identical in the coverage frequency range by oversampling 20 times. 6 Electric guitar preamplifier emulation Fig. 8 shows an electric guitar preamplifier circuit based on two JFET amplification stages. Between the first and second stages, a band-pass filter composed of R 1, C 1 and C 2 attenuates the high- and low-frequency distortion generated in the second stage. The overall amount of distortion is controlled by the potentiometer R Gain, where Gain [0,1]. The amplification stages are followed by the tone control and end with the potentiometer R Volume, which acts as a volume control, where Volume [0,1]. Fig. 8. Schematic of the guitar preamplifier composed of two JFET amplification stages with tone, gain and volume control. The WDF structure of the modeled circuit is depicted in Fig. 9. The potentiometers are represented as two resistors, where R Gain1 = (1 - R Gain Gain), R Gain2 = (R Gain Gain), R v1 = (1 - R Volume Volume), and R v2 = (R Volume Volume). The input is generated in the voltage source with a negligible series resistance, and the output is obtained by computing the voltage over the resistor R V2. Although several nonlinearities are included in the same model, each transistor element divides the binary tree by introducing one delayed sample and avoiding the propagation of the waves throughout the circuit. Fig. 9. WDF tree of the guitar preamplifier composed of two JFET amplification stages. 9

10 Fig. 10 shows the output of the circuit generated by a 0.75 V peak stimulus, where Gain is 0.5, Tone is 0.3 and Volume is 1. It can be observed that the generated distortion is a combination of both stages, where the harmonic content of the second stage is influenced by the first stage output and the gain control. The results show that the harmonic content of the WDF simulation oversampled 20 times is closely similar to the reference Spice simulation. Moreover, the WDF simulation and real time implementation (both three times oversampled) also provide nearly coincident performance. Fig. 10. Harmonic content of the guitar preamplifier output signal. 7 Conclusions and future work This work presented a JFET nonlinear WDF model and its real-time implementation. A common source JFET amplification stage and a guitar preamplifier were used as application examples. Verifications were performed by comparing the WDF models with electric Spice circuit simulations in time and frequency domain. The JFET model was found to be accurately working in audio amplification stages. WDFs demonstrated to be a proper method to model analog systems on FPGAs, offering a versatile and reliable real-time emulation platform. Limitations were found in the FPGA real-time emulation, where oversampling was necessary to achieve high-frequency accuracy due to the nonlinear WDF model. In the simulations, the oversampling factors were applied as many times as required. However, in the real-time implementations, the FPGA memory and speed limitations were considered, limiting the oversampling factor. Future work may look into the WDF modeling of other analog nonlinear systems where real time processing is required. 10