SLAC-LLNL ILC Damping Ring Kicker High Availability Modulator R&D Program

Transcription

1 SLAC-LLNL ILC Damping Ring Kicker High Availability Modulator R&D Program Craig Burkhart for the SLAC-LLNL Team: E. Cook (LLNL) A. Krasnykh, R. Larsen, T. Tang (SLAC) Slide

2 Overview Americas SLAC-LLNL program is investigating two approaches Inductive adder topologies DSRD (opening switch) topologies FY07 results and present program status FY08 Plans Slide 2

3 ATF Kicker Modulator Output connector Trigger Cables Positive and negative polarity pulses. Measurements made with two identical high voltage probes Houses trigger distribution, power supplies, etc Courtesy of E. Cook Slide 3

4 Ultra-fast Switch R&D: Cascode VS+ Vgate C bypass VS+ VH 8 C bypass R Vgate D T2 2 OE 3 IN R T2 4 Gnd Out VL VS C coupling R 3 S2 3 Vcc R Vcc C bypass V clamp R Vclamp C gate G R bias S µf R L VS+ R 4 R Vs+ EL758 4 G2 D2 5,6 C clamp D2 C bypass 2 VS+ OE Out VH 8 7 C bypass C coupling 2 D 7,8 G S Si4532ADY 0ž R Vs- G2 S2 T R T 3 IN VL 6 R VS- C neg. bias 4 Gnd VS- 5 R 2 EL758 Reduced loading on driver circuit Lower impedance output stage drive Higher driver voltage Short pulse duration: 2.5 ns FWHM Fast rise/fall time: <2 ns Challenge: controlling output voltage Data courtesy of E. Cook Slide 4

5 Ultra-fast Switch R&D: Hybrid Die-form driver & FET Eliminate package inductance Better control of gate charge Reduce source LdI/dt voltage Fast output risetime:.2 ns (Ch) Excellent gate control (Ch2) High output voltage Low R DS-on V D = 400 V Driver not optimized for short pulse Data courtesy of T. Tang Slide 5

6 Ultra-fast HV Diagnostic R&D Prototype broadband power divider Compact, 2 nd generation version under construction, using tested SMD resistors Comparison with commercial, low power, low voltage, high bandwidth divider Data courtesy of A. Krasnykh Slide 6

7 DSRD Diagnostic Test Stand PROGRAMMABLE LOGIC ARRAY GENERATES CONTROL TERMS, CLOCK TERMS, AND LOGIC TERMS BASED ON DESIGN OF PEP TFB GAGE BOARD TRIGGER SYSTEM XCR3064XL Vi_low<0.4V Vi_high>2.4V 62.5 MHz CLOCK (6.54 ns) CH0 MULTI CHANNEL PROGRAMMABLE PULSE GENERATOR (3 MHz TRAIN, 5 PPS) 0 V DC/DC CONVERTER +- 5V, +5V HV ISOLATION CH CH2 2 U3 4 3 DRIVER2 OPTO RECIVER2 L 2 0 U2 HV D C MOSFET R LOAD D2 D R4 R2 MOSFET2 DSRD STACK 2 L2 C2 D4 HV2 DC/DC CONVERTER +- 5V, +5V HV ISOLATION DRIVER OPTO RECIVER 0 Characterize DSRD to 6 kv Independent forward and reverse drive Data courtesy of A. Krasnykh Slide 7

8 FY08 Inductive Adder Program 2 nd generation hybrid driver/fet circuit Module development; parallel arrays Cascode Hybrid Adder structures Conventional adder structure cannot meet 3 ns bunch spacing requirements; transit time > ns Investigate compact structures, e.g. transmission line transformer Scale modulators Identify bandwidth limitations of module and adder cell approaches Slide 8

9 FY08 DSRD Program Develop prototype DSRD kicker modulator ±5 kv into 50 Ω Flattop ~2 ns, rise/fall ~ ns (fundamental limit for 500 V p-n Si junction) PRF thermally limited (DSRDs from Ioffe, no thermal management structure, DTI has USDOE SBIR funding to work with VMI to commercialize DSRD with heat sinks) Deliver to KEK for testing on ATF2 Slide 9

10 Prototype Schematic L0 C C0 L0 C C0 50 ohm coax: ~ ns DSRD Stacks 50 ohm coax to loads 50 ohm loads MOSFET-based pump (LLNL inductive adder module) Slide 0

11 Summary FY07 Results Modest progress (funding limitations) Ultra-fast FET switching High bandwidth HV diagnostics DSRD test stand FY08 Program Scaled inductive adder assemblies Prototype DSRD modulator Funding cuts may limit progress Slide