SiC MOSFETs: Gate Drive Optimization

Transcription

1 SiC MOSFETs: Gate Drive Optimization Steve Mappus

2 Agenda SiC Introduction SiC MOSFET characteristics SiC MOSFET dynamic switching Discrete SiC gate drive circuit NCP51705 SiC MOSFET gate driver Distinguishing features System performance Application circuit (EVB) NCP51705 parametric test results Double pulse test Closing Summary 2

3 SiC Introduction 3

4 Si Verses WBG Material Properties 4

5 SiC MOSFET Characteristics Most Critical for Gate Drive 5

6 SiC MOSFET: I D vs V DS Output Characteristics SiC has no linear/saturation distinction Behaves like voltage controlled resistor Need over current protection ( DESAT ) 6

7 SiC MOSFET: On Resistance PTC: Increase T J =Increase R DS NTC: Increase T J =Decrease R DS For Si MOSFET whenever V GS >V TH, R DS has PTC SiC has NTC for V GS <16 V ΔR DS /ΔT J slope is negative Can not be easily paralleled for V GS <16 V R DS R CH +R DRIFT +R J R DRIFT +R J are PTC resistances Dominant at high V GS R CH is NTC resistance Dominant at low V GS 7

8 SiC MOSFET: Internal Gate Resistance, R GI Relatively high R GI Much lower C ISS Slightly lower C GD & C OSS R GI is inversely proportional to die size Smaller SiC die means higher R GI But. Lower Q G Lower C iss Lower R GI xc iss time constant 8

9 SiC MOSFET: Gate Charge Gate charge loss limits operating frequency Negative gate drive during off-time R GI is high V GS <0 V to ensure fast dv DS /dt dv DS /dt immunity against low V TH Miller plateau Higher V GS compared to Si Not flat due to low g m 9

10 SiC MOSFET Dynamic Switching 10

11 SiC MOSFET Switching: Turn-On VDD ID V DD (~20 V) V GS V GS(MP)(~8 V) CDD CGD D V TH (~1 V) V EE (~-3 V) t RHI RGATE G RGI CDS CGS S CEE I G VEE V DS I D t t t t0 t1: V GS <V TH, gate drive delay t1 t2: V TH <V GS <V GS(MP), I D is increasing t2 t3: V GS =V GS(MP), V DS discharges Need high I G during this interval t3 t4: V GS >V GS(MP), R DS(ON) reaches minimum value and has PTC t0 t1 t2 t3 t4 11

12 SiC MOSFET Switching: Turn-Off VDD ID V DD (~20 V) D V GS V GS(MP)(~8 V) CDD CGD RLO RGATE RGI CDS V TH (~1 V) V EE (~-3 V) t G CGS S VEE I G V DS I D t t t t0 t1: V DD <V GS <V TH(MP), R DS(ON) increasing t1 t2: V GS =V GS(MP), V DS increasing t2 t3: V GS =V GS(MP), I D decreasing, body-diode blocking t3 t4: V GS(MP) <V GS <V EE, R DS reaches maximum value Need high I G (I SNK ) during this interval t0 t1 t2 t3 t4 12

13 SiC MOSFET Gate Driver Requirements Summary of SiC gate drive requirements 1. Able to withstand 35 V rail-to-rail (V DD =25 V and V EE =-10 V) 2. V GS must have fast rise and fall edges (~few ns) 3. High I SRC across the Miller plateau (several amps) 4. Must have high I SNK to guarantee hold off and high dv DS /dt immunity 5. V DD UVLO level matched to SiC thermal capabilities 6. DESAT function for monitoring over current across SiC MOSFET R DS(ON) 7. Low parasitic inductance package 8. Small driver package able to be located close to SiC MOSFET 13

14 Discrete SiC Gate Drive Circuit 14

15 SiC Discrete Gate Drive Example General purpose low-side gate driver V DD(MAX) >25 V Requires two dc-dc converters Post-regulation for isolator 5-V bias Low transformer winding capacitance. Example: I C(PARA ) = C dv 100 V = 1 pf = 100 ma dt 1 ns BUT Limited driver choices No DESAT protection V DD UVLO based on 12 V No V EE UVLO 15

16 Integrated SiC Gate Drive Circuit 16

17 NCP51705 SiC Gate Driver NCP51705 V5V UVSET IN+ IN- XEN SGND 23 25μA VEESET 5V_OK VDD_OK VEE_OK 6 VCH UVLO PROTECTION LOGIC CHARGE PUMP REG 5V REG CPCLK 7 C+ TSD RUN INPUT LOGIC CHARGE PUMP POWER STAGE 8 C- VEE VEE DESAT / CURRENT SENSE DRIVER LOGIC & LEVEL SHIFT PGND PGND VDD VDD OUTSRC OUTSRC OUTSNK OUTSNK 16 PGND 15 SVDD DESAT /CS PGND Features V DD rated for 28 V I SRC =6 A, I SNK =10 A at ~V DD /2 5 V, 20 ma bias regulator Separate signal, power ground Separate OUTSRC, OUTSNK Internal thermal shutdown Separate IN+, IN- TTL inputs Differentiating Features DESAT, OCP Internal V EE charge pump Programmable V DD UVLO XEN, fault and driver status 4 mm x 4 mm MLP 17

18 NCP51705 DESAT NCP51705 DESAT Function Q Q S R IN 3.3 V DESAT_FLT ENABLE 200 µa 1.25 V V DD 100 k 20 k Remove (Option) SiC Drive 5 DESAT 500ns Timer OUTSRC OUTSNK R 1 D 1 I D Q 1 V DS DESAT is in addition to PWM OCP Protects SiC MOSFET against excessive power dissipation R DS, V DS while I D is maximum V DD or V GS too low Short-circuit or overload Monitors V DS only during on-time 500ns timer allows V DS time to fall Programmable by R 1, D 1 selection R 1 = V DESAT V D1 I D R DS 200 μa = 7.5 V 1.5 V (20 A 200 mω) 200 μa = 10 kω 13 Select D 1 with lowest C J 18

19 NCP51705 V EE Charge Pump, VEESET ADJUST 5 6 VEESET V CH V DD LDO 9 V NCP51705 VEE Charge Pump G LDO 390 khz fixed frequency (290 khz option) Three small SMD ceramic capacitors V EE UVLO ~80 % set value V EE programmable by VEESET VEESET=GND, V EE UVLO is disabled C CH P P I D N N SiC Drive (SINK) 14 Q 1 V DS OUTSNK 13 C C 7 8 V EE C F C VEE 19

20 NCP51705 UVSET NCP51705 UVSET Function VDD V5V Active at V DD =7 V Fixed 1 V, V DD UVLO hysteresis V OFF =V ON -1 V 25 µa Two UVLO conditions to enable OUT 6 1. V DD >V ON 2. V EE <80 % set value UVSET 24 R UVSET R UVSET chosen for desired V ON by: R UVSET = V ON 6 25 μa 20

21 NCP51705 UVSET, HV Start-Up Considerations 21

22 NCP51705 Package 4 mm x 4 mm MLP Low inductance Double pins, double bond for power connections digital on left side for easy PWM interface Bottom pad is electrically isolated, thermally conductive; heatsink to PCB (do not connect to PGND or SGND) Power dissipation concerns Disable internal charge pump, use external V EE No load on V5V (5 V) Lower switching frequency Get creative with top side heatsinking 22

23 NCP51705 Start Up 23

24 NCP51705 V EE Start Up V EE slow control loop Slight undershoot ~400 µs correction Regulates to -3 V, -5 V or -8 V by VEESET pin strapping 24

25 NCP51705 Shut Down 25

26 NCP51705 Propagation Delay 26

27 NCP51705 DESAT 27

28 NCP51705 Mini EVB 28

29 NCP51705 Mini EVB Mounting into existing power PCB Hardwire to EVB XVDD/XGND (digital isolator primary +5 V) V DD /GND (NCP V) IN+/XGND (PWM input signal) 29

30 Parametric Test Results 30

31 Double Pulse Test Clamped inductive switching Compare switching performance between NCP51705 mini EVB and basic SiC opto-coupler driver 31

32 V GS Dynamic Switching 32

33 V DS Dynamic Switching, Vary R GATE 33

34 V DS Dynamic Switching 34

35 Closing Summary Gate drive: Most critical but often overlooked Simple, reliable, high performance gate drive is critical for SiC success NCP5170 Simple Flexible High-speed Minimal components Reliable 35

36 Thank You For more information regarding these products or our complete portfolio of products, please contact your local sales person or authorized distributor. 36