LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

Transcription

1 ; Rev ; 4/2 LVDS or LVTTL/LVCMOS Input to General Description The 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 2ps maximum output-to-output skew and ±1ps maximum added peak-to-peak jitter. The is designed to operate with a 3.3V supply voltage over the extended temperature range of -4 C to +85 C. This device is available in 28-pin exposed- and nonexposed-pad TSSOP and 32-lead 5mm x 5mm QFN packages. Cellular Base Stations Servers Add/Drop Multiplexers TOP VIEW OUTA5 1 OUTA6 2 ENA 3 SEL 4 SE_IN 5 6 GND 7 IN+ 8 IN- 9 GND 1 Applications Digital Cross-Connects DSLAMs Networking Equipment Typical Application Circuit and Functional Diagram appear at end of data sheet. Pin Configurations 28 OUTA4 27 OUTA3 26 GND 25 OUTA2 24 OUTA OUTA 21 OUTB6 2 GND 19 OUTB5 Features LVDS or LVTTL/LVCMOS Input Selection LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination Two Output Banks with Separate Bank Enables Integrated Output Series Termination for 6Ω Lines 2ps (max) Output-to-Output Skew ±1ps (max) Peak-to-Peak Added Output Jitter 42% to 58% Output Duty Cycle at 125MHz Guaranteed 125MHz Operating Frequency LVDS Input Is High Impedance with = V or Open (Hot Swappable) 28-Pin Exposed- and Nonexposed-Pad TSSOP or 32-Lead QFN Packages -4 C to +85 C Operating Temperature 3.V to 3.6V Supply Voltage Ordering Information PART TEMP RANGE PIN-PACKAGE EUI -4 C to +85 C 28 TSSOP AEUI -4 C to +85 C 28 TSSOP-EP** EGJ* -4 C to +85 C 32 QFN-EP *Future product contact factory for availability. **Exposed pad. Function Table EN_ SEL SE_IN V ID OUT_ H H H X H H H H H L or open L or open L or open X X +5mV H X -5mV L L RSET ENB OUTB4 H L or open X Op en, und r i ven shor t, or und r i ven p ar al l el ter m i nati on H OUTB OUTB OUTB3 OUTB2 TSSOP Pin Configurations continued at end of data sheet. L or Open V ID = V IN+ - V IN- H = high logic level X X X L L = low logic level X = don t care Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS to GND...-.3V to +4V IN+, IN- to GND...-.3V to +4V SE_IN, EN_, SEL, RSET, OUT_ to GND...-.3V to +.3V Output Short-Circuit Duration (OUT_) (Note 1)...Continuous Continuous Power Dissipation (T A = +7 C) 28-Pin TSSOP (derate 12.8mW/ C above +7 C)...124mW 28-Pin TSSOP-EP (derate 23.8mW/ C above +7 C)..194mW 32-Pin QFN (derate 21.2mW/ C above +7 C)...174mW Note 1: Short one output at a time. Do not exceed the absolute maximum junction temperature. Storage Temperature Range C to +15 C Junction Temperature C Operating Temperature Range...-4 C to +85 C ESD Protection Human Body Model (IN+, IN-)...±16kV Human Body Model (SE_IN)...±8kV Soldering Temperature (1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ( = 3.V to 3.6V, ENA = ENB = high, RSET = 12kΩ ±1%, differential input voltage IV ID I =.5V to 1.2V, input common-mode voltage V CM = IV ID /2 I to 2.4V - IV ID /2 I, T A = -4 C to +85 C, unless otherwise noted. Typical values are at = 3.3V, IV ID I =.2V, V CM = 1.2V, T A = +25 C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (SE_IN, ENA, ENB, SEL) Input High Voltage V IH 2. V Input Low Voltage V IL GND.8 V Input Clamp Voltage V CL I CL = -18mA V Input Current I IN V IN = high or low µa SE_IN Capacitance (Note 4) C IN SE_IN to GND 6.1 pf LVDS INPUT (IN+, IN-) Differential Input High Threshold V TH 5 mv Differential Input Low Threshold V TL -5 mv.5v IV ID I.6V Input Current I IN+, I IN-.6V < IV ID I 1.2V Power-Off Input Current I IN+(off).5V IV ID I.6V, = V or open I IN-(off).6V < IVID I 1.2V, = V or open Input Resistor 1 R IN1 = 3.6V or V, Figure kω Input Resistor 2 R IN2 = 3.6V or V, Figure kω Input Capacitance (Note 4) C IN IN+ or IN- to GND 6. pf OUTPUTS (OUT_) Output Short-Circuit Current (Note 1) I OS SEL = high, SE_IN = high, V OUT = V SEL = low, V ID = 1mV, V OUT = V 2 µa µa ma Output Capacitance (Note 4) C O OUT_ to GND 9 pf Output High Voltage V OH Fail-Safe Output High Voltage V OHFS open, undriven short, or undriven parallel SEL = low, inputs I OH = -1µA -.2 I OH = -4mA 2.4 I OH = -8mA 2.1 I OH = -1µA -.2 I OH = -4mA 2.4 terminated I OH = -8mA 2.1 V V

3 DC ELECTRICAL CHARACTERISTICS (continued) ( = 3.V to 3.6V, ENA = ENB = high, RSET = 12kΩ ±1%, differential input voltage IV ID I =.5V to 1.2V, input common-mode voltage V CM = IV ID /2 I to 2.4V - IV ID /2 I, T A = -4 C to +85 C, unless otherwise noted. Typical values are at = 3.3V, IV ID I =.2V, V CM = 1.2V, T A = +25 C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I OL = 1µA.2 Output Low Voltage V OL I OL = 4mA.4 I OL = 8mA.8 SEL = high, SE_IN = high or low, no load 15 µa Supply Current I CC SEL = low, V ID = -1mV or 1mV, no load 7. 1 ma V Output Series Resistance (Note 5) Output switched high, V OUT = 1.65V 72 R S Output switched low, V OUT = 1.65V 61 Ω AC ELECTRICAL CHARACTERISTICS ( = 3.V to 3.6V, C L = 2pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ ±1%, differential input voltage IV ID I =.15V to 1.2V, input common-mode voltage V CM = IV ID /2I to 2.4V - IV ID /2 I, T A = -4 C to +85 C, unless otherwise noted. Typical values are at = 3.3V, IV ID I =.2V, V CM = 1.2V, T A = +25 C.) (Notes 6, 7, 8) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time t R ns Fall Time t F Figures 2 and ns Low-to-High Propagation Delay IN+, IN- to OUT_ High-to-Low Propagation Delay IN+, IN- to OUT_ Low-to-High Propagation Delay SE_IN to OUT_ High-to-Low Propagation Delay SE_IN to OUT_ 1 1 SEL = low SEL = low RSET = 12kΩ RSET = open RSET = 12kΩ RSET = open SEL = high ns 2 SEL = high ns Added Peak-to-Peak Output Jitter t J 1mV peak-to-peak supply noise at 2kHz, 3.3V supply Output Duty Cycle ODC f IN = 125MHz f IN = 35MHz ns ns 1 ps Outp ut- to- Outp ut S kew ( N ote 9) t SKOO 2 ps SE_IN to OUT_, SEL = high.9 Part-to-Part Skew (Note 1) t SKPP1 IN+, IN- to OUT_, SEL = low 2.2 % ns SE_IN to OUT_, SEL = high 1.6 Part-to-Part Skew (Note 11) t SKPP2 IN+, IN- to OUT_, SEL = low 2.7 ns Maximum Switching Frequency (Note 12) f MAX 125 MHz Note 2: Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except V TH, V TL, and V ID. Parameter limits over temperature are guaranteed by design and characterization. Devices are production tested at T A = +25 C. 3

4 AC ELECTRICAL CHARACTERISTICS (continued) ( = 3.V to 3.6V, C L = 2pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ ±1%, differential input voltage IV ID I =.15V to 1.2V, input common-mode voltage V CM = IV ID /2I to 2.4V - IV ID /2 I, T A = -4 C to +85 C, unless otherwise noted. Typical values are at = 3.3V, IV ID I =.2V, V CM = 1.2V, T A = +25 C.) (Notes 6, 7, 8) Note 4: Guaranteed by design and characterization. Note 5: Total of driver output resistance and integrated series resistor. Note 6: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 7: C L includes scope probe and test jig capacitance. Note 8: Pulse generator conditions for SE_IN input: frequency = 125MHz, 5% duty cycle, Z O = 5Ω, t R = 1.2ns, and t F = 1.2ns (2% to 8%), V OH =, V OL = V. Pulse generator conditions for IN+, IN- input: frequency = 125MHz, 5% duty cycle, Z O = 5Ω, t R = 1ns, and t F = 1ns (2% to 8%). V ID, V CM as specified in AC Electrical Characteristics general conditions. Note 9: Measured between outputs with identical loads at /2 for a same-edge transition. Note 1: t SKPP1 is the greatest difference in propagation delay between different parts operating under identical conditions within rated conditions. Note 11: t SKPP2 is the greatest difference in propagation delay between different parts operating within rated conditions. Note 12: All AC specifications met at f MAX. Typical Operating Characteristics ( with RSET = 12kΩ ±1%, = 3.3V, C L = 2pF, ENA = ENB = high, IV ID I =.2, V CM = 1.2V, f IN = 125MHz, T A = +25 C, unless otherwise noted.) DIFFERENTIAL PROPAGATION DEALY (ns) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE toc1 SINGLE-ENDED PROPAGATION DELAY (ns) SINGLE-ENDED PROPAGATION DELAY vs. TEMPERATURE toc2 DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE toc TEMPERATURE ( C) TEMPERATURE ( C) SUPPLY VOLTAGE (V) 4

5 Typical Operating Characteristics (continued) ( with RSET = 12kΩ ±1%, = 3.3V, C L = 2pF, ENA = ENB = high, IV ID I =.2, V CM = 1.2V, f IN = 125MHz, T A = +25 C, unless otherwise noted.) SINGLE-ENDED PROPAGATION DELAY (ns) SINGLE-ENDED PROPAGATION DELAY vs. SUPPLY VOLTAGE toc4 DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE toc5 OUTPUT VOLTAGE HIGH (V) OUTPUT VOLTAGE HIGH vs. TEMPERATURE I LOAD = -4mA toc SUPPLY VOLTAGE (V) COMMON-MODE VOLTAGE (V) TEMPERATURE ( C) OUTPUT VOLTAGE LOW (V) OUTPUT VOLTAGE LOW vs. TEMPERATURE I LOAD = 4mA TEMPERATURE ( C) toc7 OUTPUT VOLTAGE HIGH (V) OUTPUT VOLTAGE HIGH vs. SUPPLY VOLTAGE I LOAD = -4mA SUPPLY VOLTAGE (V) toc8 OUTPUT VOLTAGE LOW (V) OUTPUT VOLTAGE LOW vs. SUPPLY VOLTAGE I LOAD = 4mA SUPPLY VOLTAGE (V) toc9 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. FREQUENCY ALL CHANNELS SWITCHING C L = 18pF SINGLE-ENDED INPUT toc1 DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. OUTPUT CAPACITANCE toc11 TRANSITION TIME (ns) TRANSITION TIME vs. TEMPERATURE t R t F toc FREQUENCY (MHz) OUTPUT CAPACITANCE (pf) TEMPERATURE ( C) 5

6 Typical Operating Characteristics (continued) ( with RSET = 12kΩ ±1%, = 3.3V, C L = 2pF, ENA = ENB = high, IV ID I =.2, V CM = 1.2V, f IN = 125MHz, T A = +25 C, unless otherwise noted.) TRANSITION TIME (ns) TRANSITION TIME vs. SUPPLY VOLTAGE t R t F SUPPLY VOLTAGE (V) toc13 DIFFERENTIAL PROPAGATION DELAY (ns) DIFFERENTIAL PROPAGATION DELAY vs. RSET RSET (kω) toc14 OUTPUT JITTER (psp-p) OUTPUT JITTER vs. 2kHz SUPPLY NOISE AMPLITUDE DIFFERENTIAL INPUT SUPPLY NOISE AMPLITUDE (mv P-P ) toc15 Pin Description QFN PIN TSSOP NAME FUNCTION 1 4 SEL LVCMOS/LVTTL Level Logic Input. SEL = high selects SE_IN. SEL = low or open selects IN+, IN-. SEL is pulled to GND by an internal resistor. 2 5 SE_IN LVCMOS/LVTTL Level Input. SE_IN is pulled to GND by an internal resistor. 3, 12, 16, 22, 29 4, 7, 13, 19, 25, 28 6, 17, 23 Positive Supply Voltage. Bypass with.1µf and.1µf capacitors to ground. 7, 1, 2, 26 GND Ground 5 8 IN+ Noninverting Input of Differential Input 6 9 IN- Inverting Input of Differential Input 8 11 RSET 9 12 ENB Connect a 12kΩ ±1% resistor to ground to decrease the minimum to maximum IN+, IN- to OUT_ propagation delay. LVCMOS/LVTTL Level Logic Input. When ENB = high, outputs OUTB_ are enabled and follow the selected input. When ENB = low or open, outputs OUTB_ are driven low. ENB is pulled to GND by an internal resistor. 1, 11, 14, 15, 17, 18, , 18, 19, 21 OUTB_ Bank B LVCMOS/LVTTL Outputs 6

7 QFN 21, 23, 24, 26, 27, 3, 31 PIN TSSOP 1, 2, 22, 24, 25, 27, 28 NAME OUTA_ 32 3 ENA Bank A LVCMOS/LVTTL Outputs Pin Description (continued) FUNCTION LVCMOS/LVTTL Level Logic Input. When ENA = high, outputs OUTA_ are enabled and follow the selected input. When ENA = low or open, outputs OUTA_ are driven low. ENA is pulled to GND by an internal resistor. EP* *EGJ and AEUI. Exposed Pad Solder to PC board OUT_ R IN2 FAIL-SAFE COMPARATOR C L IN+ -.3V TO INPUT MUX Figure 2. Output Load -4 C to +85 C. This device is available in 28-pin exposed and nonexposed pad TSSOP and 32-lead 5mm x 5mm QFN packages. IN- R IN1 R IN1 Figure 1. Fail-Safe Input Circuit Detailed Description The 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 2ps maximum output-to-output skew and ±1ps maximum added peak-to-peak jitter. The is designed to operate with a 3.3V supply voltage over the extended temperature range of Fail-Safe A fail-safe circuit on the sets enabled outputs high when the LVDS input is: Open Undriven and shorted Undriven and terminated Without a fail-safe circuit, when the LVDS input is selected and undriven, noise may cause the enabled outputs to switch. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure. When the LVDS input is driven with a differential signal with a common-mode voltage between IV ID /2I and 2.4V - IV ID /2I, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the fail-safe circuit pulls both of the LVDS inputs above -.3V, activating the fail-safe circuit and forcing the output high (Figure 1). 7

8 SE_IN /2 /2 V IN- IN+ V DIFFERENTIAL V DIFFERENTIAL 8% VCC 8% VOH 5% 5% OUT_ 2% 2% VOL tr tf Figure 3. Transition Time and Propagation Delay Timing Diagram Propagation Delay and RSET The delay can be adjusted by connecting a resistor from RSET to ground. See Typical Operating Characteristics for a graph of delay vs. RSET. Output Enables Each bank of seven LVTTL/LVCMOS drivers is controlled by an output enable. Outputs follow the selected input when EN_ is high. Outputs are low (not high impedance) when EN_ = low. Power Dissipation and Package Type Power dissipation at high switching frequencies may exceed the power dissipation capacity of the standard TSSOP package (see the Supply Current vs. Frequency graph in the Typical Operating Characteristics). An EP version of the TSSOP package is available that dissipates higher power. Also, a space-saving QFN package with EP is available. The EP must be soldered to the PC board. Supply Bypassing Bypass each supply pin with high-frequency surfacemount ceramic.1µf and.1µf capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the device. Board Layout A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep input and output signals separated to prevent coupling. TRANSISTOR COUNT: 756 PROCESS: CMOS Chip Information 8

9 ENA Functional Diagram OUTA[:6] SEL RSET IN+ IN- DELAY MUX SE_IN OUTB[:6] ENB 9

10 CARD 1 ASIC ASIC 14 CARD 2 Typical Application Circuit FPGA 1 FPGA LVDS SYSTEM CLOCK BACKPLANE R T TEST CLOCK SINGLE ENDED R T Pin Configurations (continued) TOP VIEW ENA 32 OUTA6 31 OUTA5 3 VCC 29 GND 28 OUTA4 27 OUTA GND SEL 1 24 OUTA2 SE_IN 2 23 OUTA GND IN OUTA OUTB6 IN GND GND 7 18 OUTB5 RSET 8 17 OUTB4 9 ENB 1 OUTB OUTB1 VCC GND OUTB2 OUTB3 VCC QFN 1

11 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 11

12 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 12

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to TSSOP, 4.,EXP PADS.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.