Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

Transcription

1 ; Rev 2; 4/09 Dual 1:5 Differential LPECL/LECL/HSTL General Description The are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecting the on-chip BB supply to one input as a reference voltage. The feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LPECL signals, these devices operate over a to +3.8 supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5 or +3.3 supply. For differential LECL operation, these devices operate from a to -3.8 supply. The MAX9312 features an on-chip BB reference output of below the positive supply voltage. The MAX9314 offers an on-chip BB reference output of 1.32 below the positive supply voltage. Both devices are offered in an industry-standard 32-pin 7mm x 7mm LQFP package. In addition, the MAX9312 is offered in a space-saving 32-pin 5mm x 5mm TQFN package. Precision Clock Distribution Low-Jitter Data Repeater Applications Features to +3.8 Differential HSTL/LPECL Operation to -3.8 Differential LECL Operation 30ps (typ) Part-to-Part Skew 12ps (typ) Output-to-Output Skew 312ps (typ) Propagation Delay 300m Differential Output at 3GHz On-Chip Reference for Single-Ended Inputs Output Low with Open Input Pin Compatible with MC100LEP210 (MAX9312) and MC100EP210 (MAX9314) Offered in Tiny QFN* Package (70% Smaller Footprint than LQFP) Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9312ECJ+ -40 C to +85 C 32 LQFP MAX9312ETJ+ -40 C to +85 C 32 TQFN-EP* MAX9314ECJ -40 C to +85 C 32 LQFP *Exposed pad. +Denotes a lead(pb)-free/rohs-compliant package. Functional Diagram QA0 QB0 QA0 QB0 QA1 QB1 CLKA CLKA QA1 QA2 QA2 QA3 CLKB CLKB QB1 QB2 QB2 QB3 BB EE EE QA3 QA4 EE EE QB3 QB4 QA4 QB4 Pin Configuration appears at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Dual 1:5 Differential LPECL/LECL/HSTL ABSOLUTE MAXIMUM RATINGS EE Inputs (CLK_, CLK_)... EE to CLK_ to CLK_...±3.0 Continuous Output Current...50mA Surge Output Current...100mA BB Sink/Source Current...±0.65mA Continuous Power Dissipation (T A = +70 C) 32-Pin LQFP (derate 20.7mW/ C above +70 C) mW 32-Pin TQFN (derate 34.5mW/ C above +70 C) mW Junction-to-Case Thermal Resistance (T JC ) (Note A) 32-Pin LQFP...12 C/W 32-Pin TQFN...2 C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ( EE = to +3.8, outputs loaded with 50Ω ±1% to 2.) (Notes 2 5) Junction-to-Ambient Thermal Resistance (T JA ) (Note 1) 32-Pin LQFP C/W 32-Pin TQFN...29 C/W Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +150 C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_)...2k Soldering Temperature (10s) C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to PARAMETER SYMBOL CONDITIONS INPUTS (CLK_, CLK_) -40 C +25 C +85 C MIN MAX MIN MAX MIN MAX UNITS Single-Ended Input High oltage IH B B connected to CLK_ ( IL for B B connected to C LK_) MAX9312 MAX Single-Ended Input Low oltage IL B B connected to CLK_ ( IL for B B connected to C LK_) MAX9312 EE 1.62 MAX9314 EE EE 1.62 EE EE 1.62 EE High oltage of Differential Input Low oltage of Differential Input Differential Input oltage IHD EE ILD EE EE EE EE EE For EE < CC CC CC - IHD - EE EE EE ILD For EE Input High Current CLK_ Input Low Current I IH µa I ILCLK µa 2

3 Dual 1:5 Differential LPECL/LECL/HSTL DC ELECTRICAL CHARACTERISTICS (continued) ( EE = to +3.8, outputs loaded with 50Ω ±1% to 2.) (Notes 2 5) PARAMETER SYMBOL CONDITIONS CLK_ Input Low Current OUTPUTS (Q, Q ) Single-Ended Output High oltage Single-Ended Output Low oltage Differential Output oltage REFERENCE ( BB ) Reference oltage Output (Note 6) POWER SUPPLY Supply Current (Note 7) -40 C +25 C +85 C MIN MAX MIN MAX MIN MAX I ILCLK µa OH Figure 1 OL Figure UNITS OH - OL Figure m BB I BB = ±0.5mA MAX9312 MAX I EE ma 3

4 Dual 1:5 Differential LPECL/LECL/HSTL AC ELECTRICAL CHARACTERISTICS ( EE = to +3.8, outputs loaded with 50Ω ±1% to 2, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), IHD = EE to, ILD = EE to 0.15, IHD - ILD = 0.15 to the smaller of 3 or EE, unless otherwise noted. Typical values are at EE = 3.3, IHD = 1, ILD = 1.5.) (Note 8) PARAMETER SYM B O L CONDITIONS Differential Inputto-Output Delay Output-to-Output Skew (Note 9) Part-to-Part Skew (Note 10) Added Random Jitter (Note 11) Added Deterministic Jitter (Note 11) -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS t PLHD, t PHLD Figure ps t SKOO ps t SKPP ps t RJ t DJ f IN = 1.5GHz clock pattern f IN = 3.0GHz clock pattern 3Gbps, PRBS pattern ps (RMS) ps (pk-pk) Switching Frequency Outp ut Ri se/fal l Ti m e ( 20% to 80%) OH - OL 300m, cl ock p atter n, Fi g ur e 2 f MAX OH - OL 500m, cl ock p atter n, Fi g ur e t R, t F Figure ps GHz Note 2: Measurements are made with the device in thermal equilibrium. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: Single-ended input operation using BB is limited to EE = 3.0 to 3.8 for the MAX9312 and EE = 2.7 to 3.8 for the MAX9314. Note 5: DC parameters production tested at T A = +25 C. Guaranteed by design and characterization over the full operating temperature range. Note 6: Use BB only for inputs that are on the same device as the BB reference. Note 7: All pins open except and EE. Note 8: Guaranteed by design and characterization limits are set at ±6 sigma. Note 9: Measured between outputs on the same part at the signal crossing points for a same-edge transition. Note 10: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 11: Device jitter added to the input signal. 4

5 Dual 1:5 Differential LPECL/LECL/HSTL Typical Operating Characteristics ( = +3.3, EE = 0, IHD = 0.95, ILD = CL , input transition time = 125ps (20% to 80%), f IN = 1.5GHz, outputs loaded with 50Ω to 2, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT, I EE vs. TEMPERATURE TEMPERATURE ( C) MAX9312 toc01 OUTPUT AMPLITUDE () OUTPUT AMPLITUDE ( OH - OL ) vs. FREQUENCY FREQUENCY (MHz) MAX9312 toc02 TRANSITION TIME (ps) TRANSITION TIME vs. TEMPERATURE t R t F TEMPERATURE ( C) MAX9312 toc03 PROPAGATION DELAY (ps) PROPAGATION DELAY vs. SINGLE-ENDED HIGH OLTAGE OF DIFFERENTIAL INPUT ( IHD ) t PHLD t PLHD IHD - ILD = 150m IHD () MAX9312 toc04 PROPAGATION DELAY (ps) PROPAGATION DELAY vs. TEMPERATURE 340 IHD = 0.95 ILD = t PLHD t PHLD TEMPERATURE ( C) MAX9312 toc05 5

6 Dual 1:5 Differential LPECL/LECL/HSTL PIN NAME FUNCTION Pin Description 1, 9, 16, 25, 32 Place the capacitors as close to the device as possible with the smaller value capacitor closest to Positive Supply oltage. Bypass from to EE with 0.1µF and 0.01µF ceramic capacitors. the device. 2 N.C. No Connection. Internally not connected. 3 CLKA Noninverting Differential Clock Input A 4 CLKA Inverting Differential Clock Input A 5 BB reference for single-ended operation. When used, bypass to with a 0.01µF ceramic Reference Output oltage. Connect to the inverting or noninverting clock input to provide a capacitor. 6 CLKB Noninverting Differential Clock Input B 7 CLKB Inverting Differential Clock Input B 8 EE Negative Supply oltage 10 QB4 Inverting QB4 Output. Typically terminate with 50Ω resistor to QB4 Noninverting QB4 Output. Typically terminate with 50Ω resistor to QB3 Inverting QB3 Output. Typically terminate with 50Ω resistor to QB3 Noninverting QB3 Output. Typically terminate with 50Ω resistor to QB2 Inverting QB2 Output. Typically terminate with 50Ω resistor to QB2 Noninverting QB2 Output. Typically terminate with 50Ω resistor to QB1 Inverting QB1 Output. Typically terminate with 50Ω resistor to QB1 Noninverting QB1 Output. Typically terminate with 50Ω resistor to QB0 Inverting QB0 Output. Typically terminate with 50Ω resistor to QB0 Noninverting QB0 Output. Typically terminate with 50Ω resistor to QA4 Inverting QA4 Output. Typically terminate with 50Ω resistor to QA4 Noninverting QA4 Output. Typically terminate with 50Ω resistor to QA3 Inverting QA3 Output. Typically terminate with 50Ω resistor to QA3 Noninverting QA3 Output. Typically terminate with 50Ω resistor to QA2 Inverting QA2 Output. Typically terminate with 50Ω resistor to QA2 Noninverting QA2 Output. Typically terminate with 50Ω resistor to QA1 Inverting QA1 Output. Typically terminate with 50Ω resistor to QA1 Noninverting QA1 Output. Typically terminate with 50Ω resistor to QA0 Inverting QA0 Output. Typically terminate with 50Ω resistor to QA0 Noninverting QA0 Output. Typically terminate with 50Ω resistor to 2. EP Exposed Pad (TQFN package only). Internally connected to EE. Connect EP to the EE pad on the PCB. 6

7 Dual 1:5 Differential LPECL/LECL/HSTL Detailed Description The are low-skew, dual 1-to-5 differential drivers designed for clock and data distribution. For interfacing to differential HSTL and LPECL signals, these devices operate over a to +3.8 supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5 or +3.3 supply. For differential LECL operation, these devices operate from a to -3.8 supply. The differential inputs can be configured to accept single-ended inputs when operating at approximately EE = 3.0 to 3.8 for the MAX9312 or EE = 2.7 to 3.8 for the MAX9314. This is accomplished by connecting the on-chip reference voltage, BB, to an input as a reference. For example, the differential CLKA, CLKA input is converted to a noninverting, single-ended input by connecting BB to CLKA and connecting the singleended input to CLKA. Similarly, an inverting input is obtained by connecting BB to CLKA and connecting the single-ended input to CLKA. With a differential input configured as single ended (using BB ), the singleended input can be driven to and EE or with a single-ended LPECL/LECL signal. When a differential input is configured as a single-ended input (using BB ), the approximate supply range is EE = 3.0 to 3.8 for the MAX9312 and EE = 2.7 to 3.8 for the MAX9314. This is because one of the inputs must be EE or higher for proper operation of the input stage. BB must be at least EE because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum BB = EE The minimum BB output for the MAX9312 is and the minimum BB output for the MAX9314 is Substituting the minimum BB output for each device into BB = EE results in a minimum supply of for the MAX9312 and 2.58 for the MAX9314. Rounding up to standard supplies gives the single-ended operating supply ranges of EE = 3.0 to 3.8 for the MAX9312 and EE = 2.7 to 3.8 for the MAX9314. When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to. If the BB reference is not used, it can be left open. The BB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use BB only for inputs that are on the same device as the BB reference. The maximum magnitude of the differential input from CLK_ to CLK_ is 3.0 or EE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting inputs (CLKA and CLKB) are biased with a pullup to and a pulldown to EE. The noninverting inputs (CLKA and CLKB) are biased with a pulldown to EE. Specifications for the high and low voltages of a differential input ( IHD and ILD ) and the differential input voltage ( IHD - ILD ) apply simultaneously ( ILD cannot be higher than IHD ). Output levels are referenced to and are considered LPECL or LECL, depending on the level of the supply. With connected to a positive supply and EE connected to GND, the outputs are LPECL. The outputs are LECL when is connected to GND and EE is connected to a negative supply. A single-ended input of at least BB ±95m or a differential input of at least 95m switches the outputs to the OH and OL levels specified in the DC Electrical Characteristics table. Applications Information Supply Bypassing Bypass to EE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for low inductance. When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to (if the BB reference is not used, it can be left open). Traces Input and output trace characteristics affect the performance of the. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs through 50Ω to 2 or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if QA0 is used as a single-ended output, terminate both QA0 and QA0. 7

8 Dual 1:5 Differential LPECL/LECL/HSTL CLK_ CLK_ Q_ Q_ Figure 1. Switching with Single-Ended Input CLK_ CLK_ Q_ t PLHD IH BB IL (CONNECTED TO CLK_) OH OH - OL OL IHD IHD - ILD ILD t PHLD OH Q_ OH - OL OL 80% 80% 0 (DIFFERENTIAL) 0 (DIFFERENTIAL) (Q_) - (Q_) 20% 20% t R t F Figure 2. Differential Transition Time and Propagation Delay Timing Diagram Pin Configuration Chip Information TOP IEW PROCESS: BIPOLAR QA0 QA0 QA1 QA1 QA2 QA N.C. 2 CLKA 3 CLKA 4 BB 5 CLKB 6 CLKB 7 EE 8 MAX9312 MAX QA3 23 QA QA4 QA QB0 QB0 18 QB1 17 QB1 Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 LQFP C TQFN-EP T QB4 QB4 QB3 QB3 QB2 QB2 LQFP OR TDFN 8

9 Dual 1:5 Differential LPECL/LECL/HSTL REISION NUMBER REISION DATE 2 4/09 DESCRIPTION Added lead-free TQFN package for MAX9312, deleted future product packages for MAX9314, and updated Pin Description Revision History PAGES CHANGED 1, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.