Ice Radio Sampler (IRS) & Buffered LABRADOR #3 (BLAB3) Preliminary Specification Review. Gary S. Varner Internal ID Lab Review, 10 AUG 09

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1 Ice Radio Sampler (IRS) & Buffered LABRADOR #3 (BLAB3) Preliminary Specification Review Gary S. Varner Internal ID Lab Review, 10 AUG 09

2 Goals for both ASICs Confirm Design Specifications Table Listing Preliminary Design Define simulations needed Basic functionality Additional monitor/control features Action items (changes prior to submission) Design Review (17 AUG 09) [21 st for any last changes] Submission Target (24 AUG 09)

3 Ice Radio Sampler (IRS) Actually a fairly generic part Follow-on test of deeper storage [TARGET, others] 2 stage transfer mechanism (reduced calibration) No amplifier on the input Buffered LABRADOR (BLAB3) Specifications (to follow) converged Must have deeper storage Better time alignment (sync to accelerator/common timebase) Amplifier needed (improve on problems of BLAB2 amp)

4 Askaryan Radio Array (ARA)

5 Askaryan Radio Array

6 Cluster Station

7 ARA Readout Electronics Uplink bandwidth (~1Mbit/s [wireless]) Multi-tier trigger Deeper sampling allows for array trigger (subthreshold)

8 9 x 260 samples = 2340 storage cells LABRADOR(3) architecture 4 RF inputs timing control 5 RF inputs SCA bank: 4 rows x 260 columns 12 Wilkinson ADC Convert all 2340 samples in parallel, transfer out on common 12-bit data bus IRS/BLAB3 Specification Review AUG-08 SCA bank: 5 rows x 260 columns tail samples

9 Wilkinson ADC No missing codes Linearity as good as can make ramp Can bracket range of interest Run count during ramp IRS/BLAB3 Digitization 12-bit ADC IRS/BLAB3 Specification Review AUG-08 Modified! (self-counter) [1-2 GHz] Excellent linearity Basically as good as can make current source/comparator Comparator ~ V; 133MHz GCC max (~31us)

10 Ice Radio Sampler (IRS) Specifications samples/chan (16-32us trig latency) 8 channels/irs ASIC 8 Trigger channels ~9 bits resolution (12-bits logging) 64 samples convert window (~32-64ns) 1-2 GSa/s 1 word (RAM) chan, sample readout 16 us to read all samples 100's Hz sustained readout (multibuffer) Strictly only 5 channels necessary 4x antenna, 1x reference channels Could interleave for twice depth, or multiple reference channels

11 IRS Block Diagram 9.42mm Timing

12 IRS Single Channel Sampling: 128 (2x 64 separate transfer lanes Recording in one set 64, transferring other ( ping-pong ) Storage: 64 x 512 (512 = 8 * 64) Wilkinson (32x2): 64 conv/channel

13 IRS Input Coupling Input Coupling versus total input Capacitance Input coupling versus frequency Analog Bandwidth [-3dB frequency] C=15fF,Ron=1k R_S = 50Ohm -1 C=15fF,Ron=5k -2 C=25fF,Ron=1k -3 C=25fF,Ron=5k Total input Capacitance [ff] Frequency [GHz] Input bandwidth depends on 2x terms f3db[input] = [2*π*Z*C tot ] -1 Relative amplitude [db] f3db[storage] = [2*π*R on *C store ] -1

14 IRS Input Coupling Input inductance impedance versus frequency Input coupling versus frequency Impedance [Ohms] Bond-wire Bump-bond Relative amplitude [db] Bond-wire Bump-bond Frequency [GHz] Frequency [GHz] Role of inductance

15 IRS/BLAB3 Specification Review AUG-08 Constraint: ktc Noise Desire small C for better Input Coupling

16 Sample Cell Main element is buffer amp (OTA) Relatively low current (10 s ua) operation possible

17 Storage Cell Diff. Pair as comparator Only power on selected block

18 Another Constraint: Leakage Current Need small C for Input Coupling Can Improve? (readout faster) IRS/BLAB3 Specification Review AUG-08 Sample channel-channel variation ~ fa leakage typically

19 Sampling Method Example ONLY To be done Base delay

20 Triggering Need 9 th channel for monitoring

21 Temperature Dependence Sample 6GSa/s aperature (172ps = 5.8GSa/s) 0.2%/degree C (can correct) Matches SPICE simulation IRS/BLAB3 Specification Review AUG-08

22 Wilkinson Clock Generation Strictly only 5 channels necessary 4x antenna, 1x reference channels Could interleave for twice depth, or multiple reference channels

23 Wilkinson Recording Start = start 0.5-2GHz Clock Ripple counter (run as fast as can)

24 IRS Floorplan 9.42mm All but timing, output channel decoding done ; map pins

25 Particle ID at the B-factories IRS/BLAB3 Specification Review AUG-08

26 Upgraded detector -PID(π/Κ) detectors - Inside current calorimeter - Use less material and allow more tracking volume Available geometry defines form factor - Barrel PID Aerogel RICH IRS/BLAB3 Specification Review AUG-08 e - 8.0GeV 1.2m 2.6m e + 3.5GeV

27 imaging TOP (itop) Concept: Use best of both TOP (timing) and DIRC and fit in Belle PID envelope BaBar DIRC Drawing by Marc Rosen(UH) IRS/BLAB3 Specification Review AUG-08 Bars compatible (though thinner) with proposed TOP counter Use new, compact solid-state photon detectors, new high-density electronics Use simultaneous T, θc [measuredpredicted] for maximum K/π separation Keep pixel size comparable to DIRC

28 Proposed Common Approach for Belle++

29 Baseline image block IRS/BLAB3 Specification Review AUG-08 Top View 2x 64-channel PMTs per fiber link 8x BLAB3 daughtercards (16x BLAB3) 1024 PMT channels/module (16 itop staves) 8 data, 8 trigger fiber pairs + HV power, LVDS RF clock, Revolution marker pairs

30 Baseline System Components Photo- Sensor Photo- Sensor BLAB3 BLAB3 BLAB3 BLAB3 MCP MAIN Giga-bit Fiber x4 FINESSE CARD x4 COPPER FIFO IRS/BLAB3 Specification Review AUG-08 BLAB3 is 8 channels, each 64k samples deep <~1us to read out 32-samples hit/blab3 Total channel numbers presented previously unchanged, partitioned slightly differently

31 Hit Processing reminder 8 Trans-Imp Amps BLAB3 ASIC 512 x 64 samples Per channel BLAB3 sampling Fast conversion Matrix (x256) Improvements based upon Lessons learned from BLAB2 Assume: 100kHz charged track hits on each bar ~32 p.e./track (1% of 100ns windows) 30kHz trigger rate Each PMT pair sees <8> hits 240k hits/s Each BLAB3 has an average occupancy <1 hit (assume 1) 400ns to convert 256 samples 16ns/sample to transfer At least 16 deep buffering (Markov overflow probability est. < ) Each hit = 64samples * 8bits = 512bits ~125Mbits/s (link is 1.2Gb/s ~ x10 margin) IRS/BLAB3 Specification Review AUG-08 Plan to model in standard queuing simulator, but looks like no problem (CF have done same exercise with Jerry Va vra for 150kHz L1 of SuperB and can handle rate)

32 Fast Feature Extraction Assume: 100kHz singles per pixel 150kHz trigger rate at SUPERB 200ns trigger window (2% occup.) Each 64-chan PMT has ~200k hits/s Each hit = 32 samples * 12bits = 384bits ~77Mbits/s (link is 2.5Gb/s ~ x10 margin) [perhaps 2x PMT/link] BlackFin DSP Pedestal subtract Feature extract T, Q (tentatively allow up to 8x hits in 200ns) Time = 2Bytes, Q = 2Bytes IRS/BLAB3 Specification Review AUG-08 1k PMT * 1.28 hit typ * 4By = 5.12kB/event Estimate 1.5us/hit processing time, To be evaluated

33 Context: BLAB2 & PD scale readout Initial Target: New f-dirc Readout System Courtesy: J. Buckley (Wash U. St. Louis) IRS/BLAB3 Specification Review AUG-08 Gen. 0 Prototype (LAB3) Target Submission: Feb. 11, 2008

34 BLAB2 Lessons RGC (Regulated Cascode) Fussy doesn t look like 50W for large voltage signals Not enough phase margin (oscillates) Sampling nmos/pmos does NOT work Alignment between sampling rows Overall timing alignment troublesome Better with fewer distinct samples, yet having more buffer depth

35 Experiment 2: 13-Mar-09 (~6 mo.) 448 channels readout at SLAC + few hundred UH [HI-TIDE] Install and operate (learn about system timing) Experiment 3: autumn (~6+ mo.) BLAB3 ASIC upgrade (lessons learned) At speed fast feature extraction IRS/BLAB3 Specification Review AUG-08

36 BLAB3 Specifications samples/chan (>5us trig latency) 8 channels/blab3 ASIC 8 Trigger channels ~9 bits resolution (12[10]-bits logging) 64 samples convert window (~16ns) 4GSa/s 1 word (RAM) chan, sample readout 1+n*0.02 us to read n samples (of same 64) 30 khz sustained readout (multibuffer) Time alignment critical Synchronize sampling to accelerator RF clock >5us a must for trigger, since single photon rates high Needs Gain!

37 Gain Needed What gain needed? At 10 6 gain, each p.e. = 160 fc At 2x10 5 gain (better for aging), each p.e. = 32 fc In typical ~5ns pulse, Vpeak = dq/dt * R = 32uA * R = 32mV * R [kω] (6.4mV) Amplifiers dominate board space Readout ASIC pair Gain Estimate Rterm 1 p.e. peak 50 1mV 1k 20mV 20k 400mV IRS/BLAB3 Specification Review AUG-08

38 BLAB3 Block Diagram xx mm Trans-impedance amplifiers

39 For Design Review Simulation results (after final layout) Sampling speed, analog bandwidth 2-stage transfer settling time (BLAB3 critical) Wilkinson operation (with parasitics) Trigger confirmation OTA input performance Things missing? Would like to get IRS back before BLAB3 submission but Design documentation for review [decoding logic ]

40 Time is extremely tight Summary weeks typical for fab (once tapes out) Final design review next week Trade-offs Capacitance versus BW, size, ktc noise Sampling Modes Amplifier choice Doesn t work for G > 2k Baseline stability

41 Back-up slides IRS/BLAB3 Specification Review AUG-08

42 Buffered LABRADOR (BLAB1) ASIC 10 real bits of dynamic range, single-shot Measured Noise 1.45mV 1.6V dynamic range IRS/BLAB3 Specification Review AUG-08

43 Design Basis: Buffered LABRADOR (BLAB1) ASIC Single channel 64k samples deep, same SCA technique as LAB, no ripple pointer Multi-MSa/s to Multi- GSa/s 12-64us to form Global trigger IRS/BLAB3 Specification Review AUG-08 3mm x 2.8mm, TSMC 0.25um Arranged as 128 x 512 samples Simultaneous Write/Read

44 IRS/BLAB3 Specification Review AUG-08 BLAB1 Architecture 200ps/sample FPGA-based TDC: 10-bits in 1us (300ps resolution)

45 BLAB1 Sampling Speed Can store 13us at 5GSa/s (before wrapping around) 200ps/sample Single sample: 200/SQRT(12) ~ 58ps In practice, treat each row of 512 samples as independent

46 BLAB1 Analog Bandwidth LAB3 ~ 900MHz -3dB ~300MHz Buffer amps A few fixes (lower power, higher BW) Multi-channel desired for BLAB2