RECENTLY, many direct-current (dc)/dc topologies for the

Transcription

1 5154 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011 A Pulse-Frequecy-Mdulated Full-Bridge DC/DC Cverter With Series Bst Capacitr Yg-Saeg Shi, Chag-Sep Kim, ad Sag-Ky Ha, Member, IEEE Abstract The cvetial zer-vltage switchig phase-shift full-bridge ZVS PSFB cverter has a large circulatig eergy durig the freewheelig iterval caused by the small duty cycle, which culd icrease the primary-side cducti lsses, the tur-ff switchig lsses f laggig-leg switches, ad the curret ripple thrugh the utput iductr. T vercme these prblems, this paper prpses a ew pulse-frequecy-mdulated full-bridge direct-curret dc/dc cverter with a series bst capacitr SBC. The prpsed cverter ctrls the utput vltage by varyig the vltage acrss the SBC accrdig t the switchig frequecy ad has freewheelig iterval due t a 50% fixed duty perati. As a result, sice its freewheelig curret is elimiated, the cducti lsses ca be csiderably reduced, as cmpared with thse f the cvetial ZVS PSFB cverter. Mrever, the ZVS f all pwer switches cat ly be esured alg wide lad rages, but the curret ripple thrugh the utput iductr ca be als sigificatly reduced. Therefre, it has very desirable merits such as high efficiecy, small utput iductr, ad imprved heat geerati. Operatial priciples, theretical aalysis, ad desig csideratis are preseted. T cfirm the perati, the validity, ad the features f the prpsed cverter, experimetal results frm a prttype that is V/100 A are preseted. Idex Terms Full bridge, pulse-frequecy mdulati PFM, series bst capacitr SBC. I. INTRODUCTION RECENTLY, may direct-curret dc/dc tplgies fr the distributed pwer supply f telecmmuicati r server systems have bee develped, which characterize the high efficiecy ad the high pwer desity. Amg these tplgies, a cvetial zer-vltage switchig phase-shift full-bridge ZVS PSFB cverter has received csiderable attetis fr medium- r high-pwer applicatis, which is because it features high cversi efficiecy, high pwer desity, ad lw electrmagetic iterferece EMI. May literatures have already aalyzed its perati priciples ad desig csideratis i detail [1] [4]. Mauscript received May 18, 2010; revised September 5, 2010; accepted Octber 28, Date f publicati March 7, 2011; date f curret versi September 7, This wrk was supprted i part by the Research Prgram 2011 f Kkmi Uiversity, Krea ad i part by the Miistry f Kwledge Ecmy, Krea, uder the Ifrmati Techlgy IT Research Ceter supprt prgram supervised by the Natial IT Idustry Prmti Agecy uder Grat NIPA-2011-c Y.-S. Shi ad S.-K. Ha are with the Departmet f Electrical Egieerig, Kkmi Uiversity, Seul , Krea shiys@kkmi.kr; djha@kkmi.ac.kr. C.-S. Kim is with the Departmet f Ifrmati ad Telecmmuicati Egieerig, Kyugw Uiversity, Segam , Krea sckim407@kyuw.ac.kr. Clr versis f e r mre f the figures i this paper are available lie at Digital Object Idetifier /TIE Hwever, it has several serius prblems such as arrw ZVS rage f laggig-leg switches, serius vltage rigig i the secdary-side rectifier, ad large duty cycle lss. I particular, the excessive circulatig curret durig the freewheelig iterval icreases the primary-side cducti lsses ad the tur-ff switchig lsses f the laggig-leg switches. Fig. 1 shws the circuit cfigurati ad the key wavefrms f the cvetial ZVS PSFB cverter. Usually, the vltage cversi rati M ad the curret ripple rati r f the utput iductr ca be easily expressed as a fucti f the duty cycle D as fllws: M = V V i = 2D r = Δi L I L 1 =1 2D R T s 2L. 2 Sice the hldup time requiremet, which is defied as the time durati that a pwer supply shuld remai its utput vltage regulated eve at a istat pwer failure f utility, must be csidered fr the pwer supply f telecmmuicati r server systems, the ZVS PSFB cverter shuld be fit fr a relatively wide iput vltage rage. Thus, the steady-state duty cycle is as small as apprximately 30% at a rmal peratig cditi, as shw i Fig. 1c. This small duty cycle has detrimetal effects the cverter perfrmace, such as a icreased circulatig curret ad assciated cducti lss, ad a large ripple curret thrugh the utput iductr L. Mrever, sice the eergy stred i the small leakage iductr is t large eugh t achieve the ZVS f laggig-leg switches uder light lad cditis, hard switchig perati ad pr EMI perfrmace are ievitable [5]. T cpe with these prblems, zer-vltage ad zer-curret switchig techiques, which ca reduce the tur- ad tur-ff switchig lsses ad circulatig eergy durig the freewheelig iterval, are preferred i these kids f applicatis [6] [19]. Hwever, all these appraches have the cmm practical drawbacks such as arrw ZVS rages, circulatig curret, large utput ripple curret, ad limited efficiecy rigiated frm the small duty cycle at the steady state. I this paper, a full-bridge dc/dc cverter usig a series bst capacitr SBC ctrlled by pulse-frequecy mdulati PFM is prpsed, as shw i Fig. 2. The prpsed cverter has a similar circuit cfigurati t the cvetial series resat cverter SRC. Hwever, it uses a resace betwee the magetizig iductace L m ad the /$ IEEE Dwladed frm

2 SHIN et al.: PULSE-FREQUENCY-MODULATED FULL-BRIDGE DC/DC CONVERTER WITH SBC 5155 Fig. 1. Cvetial ZVS PSFB cverter. a Circuit cfigurati; b key wavefrms; ad c the vltage cversi rati M ad curret ripple rati r f the utput iductr. Fig. 2. Schematic f the prpsed PFM-SBC full-bridge dc/dc cverter. resat capacitr C r, whereas the SRC emplys a resace betwee the leakage iductace L k ad the resat capacitr C r. Mrever, the switchig frequecy f the prpsed cverter is t varied t much alg a wide lad rage, whereas that f the SRC is widely varied. I particular, sice the SRC has utput filter iductr, it has several drawbacks such as large curret stress f each device, large rtmea-square RMS curret, ad subsequet pr cducti lsses. The prpsed cverter ctrls the utput vltage by varyig the vltage acrss the SBC accrdig t the switchig frequecy ad has freewheelig iterval with the aid f a 50% fixed duty perati. Therefre, its cducti lss is lwer tha that f the cvetial ZVS PSFB cverter. Mrever, the ZVS perati f all pwer switches ca be achieved uder wide lad rages, ad the peratig frequecy ca have small variati frm lad t full lad. The curret ripple f the utput iductr is very small; thus, the utput iductr ca be smaller tha that f the size f the utput iductr αl, α 1 ad ca be mre reduced tha that f the ZVS PSFB cverter L. These advatages make the prpsed cverter well suited fr high-pwer ad high-curret applicatis such as the pwer supply fr telecmmuicati r server systems. The peratis, the aalysis, the desig csideratis, ad the experimetal results are preseted t cfirm the validity f the prpsed cverter. Fig. 3. Vltage wavefrm the rectified vltage V rec accrdig t the switchig frequecy. II. OPERATIONAL PRINCIPLES A. Operati Priciples Fig. 2 shws the prpsed PFM-SBC full-bridge cverter. The gate sigals f M 1 ad M 2 ad M 3 ad M 4 are cmplemetarily cducted with small dead times i rder t avid sht-thrugh. Fig. 3 shws v rec accrdig t the switchig frequecy, where v rec is the rectified vltage the secdary side. As shw i this figure, areas A ad B are the egative ad psitive prtis f [v rec t V i /], respectively. I additi, v rec t ca be expressed as v rec t={v i v Cr t}/. Assumig that the iput vltage V i is cstat, the wavefrm f v rec t is varied by the vltage f the bst capacitr v Cr t, ad the utput vltage V is btaied by smthig v rec t by the utput L C filter. Therefre, the average value f v rec t is equal t the utput vltage V. Sice the vltage acrss the bst capacitr v Cr t is determied by the switchig frequecy, the prpsed cverter adjusts the switchig frequecy f M 1 M 4 i rder t regulate the utput vltage. Sice the differece betwee areas A ad B is large at lw frequecies, the utput vltage is higher tha V i /. O the ther had, sice the differece betwee areas A ad B is small at high frequecies, the utput vltage appraches V i /. Thrugh the afremetied mechaism, the utput vltage ca be regulated by the PFM.

3 5156 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011 The vltage acrss the bst capacitr v Cr t is charged by i pri t as fllws: t v Cr t =V Cr t 0 + t 0 t = V Cr t 0 + t 0 i pri tdt { i Lm t 0 + Vi v Cr t L m t t 0 + I } dt. 5 Fig. 4. Operatial key wavefrms f the prpsed cverter. B. Mde Aalysis Fig. 4 shws the peratial key wavefrms f the prpsed cverter. Oe switchig perid is divided it tw mdes, ad each equivalet circuit is shw i Fig. 5. The gates f M 1 ad M 2 ad M 3 ad M 4 are cmplemetarily tured ad ff with a 50% fixed duty. Fr the cveiece f the mde aalysis i the steady state, several assumptis are made as fllws. 1 All parasitic cmpets except thse specified i Fig. 3 are eglected. 2 The trasfrmer leakage L k is small eugh t be igred. 3 Curret I L thrugh the utput iductr L is cstatly equal t I. 4 There is dc ffset curret f the trasfrmer magetizig iductr L m. 5 The dead time betwee switches M 1, M 2, ad M 3, M 4 is small eugh t be igred. Befre t 0, it is assumed that M 3 ad M 4 are cductig ad the iput pwer is trasferred t the utput side by M 3, M 4,the trasfrmer, ad D S2. Mde 1 t 0 t 1 : Whe M 1 ad M 2 are tured at t 0, mde 1 begis, as shw i Fig. 5a. The iput pwer is trasferred t the utput side by M 1, M 2, the trasfrmer, ad D S1. Sice D S1 is cductig durig t 0 t 1, I is reflected t the trasfrmer primary side, ad at the same time, V i v Cr t is applied t the magetizig iductr L m. Therefre, i Lm t ad i pri t are expressed as fllws: Vi v Cr t i Lm t =i Lm t 0 + t t 0 3 L m i pri t =i Lm t+ I. 4 Mde 2 t 1 t 2 : After M 1 ad M 2 are tured ff at t 1, the iput pwer is trasferred t the utput side by M 3, M 4, the trasfrmer, ad D S2, as shw i Fig. 5b. Sice D S2 is cductig durig t 1 t 2, I is reflected t the trasfrmer primary side, ad V i v Cr t is applied t the magetizig iductr L m. Therefre, i Lm t ad i pri t are expressed as fllws: Vi + v Cr t i Lm t =i Lm t 1 t t 1 6 L m i pri t =i Lm t I. 7 The vltage acrss the bst capacitr v Cr t is discharged by i pri t as fllws: t v Cr t =V Cr t 1 + t 1 t = V Cr t 1 + t 1 i pri tdt { i Lm t 1 Vi + v Cr t L m t t 1 I } dt. 8 Whe M 3 ad M 4 are tured ff, this mde 2 eds at t 2. Subsequetly, the perati frm t 0 t t 2 is repeated. III. ANALYSIS OF THE PROPOSED CONVERTER A. Vltage Cversi Rati T simplify the aalysis f the vltage cversi rati, the leakage iductace L K ad the dead time betwee switches M 1 ad M 2 ad M 3 ad M 4 are eglected. Fig. 6 is a equivalet circuit diagram that perates durig t 0 t 1. As shw i this figure, a resat LC circuit is frmed, ad v Cr t ad i Lm t are expressed as fllws: C dv Crt dt = i Lm t+ I di Lm t V i = v Cr t+l m dt where C r ad L m have the fllwig iitial values: 9 10 v Cr t 0 = V V i Lm t 0 = I V. 11

4 SHIN et al.: PULSE-FREQUENCY-MODULATED FULL-BRIDGE DC/DC CONVERTER WITH SBC 5157 Fig. 5. Equivalet circuits f the prpsed cverter. a Mde 1 t 0 t 1. b Mde 2 t 1 t 2. Frm 11, 15, ad 16, V V ad I V ca be derived frm 11 as V V = Z I si0.5ω /f sw 1 + cs0.5ω /f sw 17 I V = V i Z si0.5ω /f sw 1 + cs0.5ω /f sw. 18 Fig. 6. Equivalet circuit durig mde 1 t 0 t 1. Therefre, v Cr t ad i Lm t ca be derived frm 9 ad 11 as v Cr t = Z I V I siω t V V + V i csω t+v i 12 i Lm t = I V I csω t + V V + V i Z siω t I 13 where the characteristic impedace Z ad the resat agular frequecy ω are defied as Lm 1 Z = ω =. 14 C r Lm C r Sice v Cr t ad i Lm t becme V V ad I V after a half switchig cycle, respectively, the fllwig equatis are satisfied: V V = Z I V I T s si ω 2 V V + V i cs T s ω 2 I V = I V I T s cs ω 2 + V V + V i Z T s si ω 2 + V i 15 I. 16 As shw i Fig. 3, sice the average f v rec t is equal t the utput vltage V, V ca be expressed as V = 1 T s /2 = 2 T s T s 0 [ Z ω [ ] 1 {V i V Cr t} dt I V I { T s cs ω 2 V V + V i ω T s si ω 2 } 1 ]. 19 Therefre, the vltage cversi rati f the prpsed cverter ca be derived frm as V V i = 2 siπf /f sw πf /f sw 1+csπf /f sw 20 where f ad f sw are the resat frequecy 1/2πL m C r 0.5 ad the switchig frequecy, respectively. Frm 20, the vltage cversi rati is depedet f sw, f, ad. Based 20, Fig. 7 shws the theretical vltage cversi rati accrdig t the rmalized switchig frequecy by the resat frequecy. B. ZVS Sice the switchig peratis f M 1 ad M 2 ad M 3 ad M 4 are symmetrical, ly M 1 is csidered. The ZVS f switch M 1 is achieved by the eergy stred i the leakage iductr. Therefre, the eergy stred i the leakage iductr must discharge C DS.M1 t the vltage level f 0 V befre switch M 1 is tured. The eergy required t displace the charge f the metal xide semicductr field-effect

5 5158 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011 The required dead time see Fig. 8 t achieve the ZVS is give as t dead = 2C ssv i + V V I V + I + π L k C ss. 24 Fig. 7. Theretical vltage cversi rati accrdig t the switchig frequecy. Fig. 8. Required dead time fr the ZVS f the prpsed cverter. trasistr s MOSFET liear utput capacitace ca be derived frm datasheet parameters. Assumig that the capacitace is a iverse square-rt fucti f its vltage, we ca use eergy equivalece relatiships t express the stred eergy i terms f a small-sigal measuremet [20]. The eergy required t achieve the ZVS is give as E required = 8 3 C ss Vss V 3/2 i. max 21 where C ss is a small-sigal MOSFET s equivalet utput capacitace measured at the drai surce vltage V ss.the eergy stred i the leakage iductace is give as E stred = 1 2 L ki 2 = 1 2 L k I V + PL I 2 22 where PL is defied as the rati betwee the miimum lad curret fr esurig the ZVS ad the maximum lad curret. T esure the ZVS, the eergy E stred stred i the leakage iductr L k must be greater tha the eergy E required stred i the switch utput capacitr. Therefre, the required miimum leakage iductace ca be determied frm 21 ad 22 as Vss V 3/2 L k. mi 16C ss 3 I V + PL I i. max. 23 C. Duty Cycle Lss The duty cycle lss ΔD f the prpsed cverter ccurs due t the liear variati f the curret thrugh the leakage iductace L k. If it is assumed that the vltage acrss the bst capacitr V Cr ad the magetizig curret I Lm are cstat, the duty cycle lss ca be derived as fllws: ΔD = ΔT 25 Ts ΔT = L 2I k 2L ki 26 V Cr V V 1 f eff = 27 T s 2ΔT where f eff is the effective switchig frequecy. It is shw i 28 that the larger leakage iductace L k prduces the larger duty cycle lss ad the higher effective switchig frequecy. D. Output Filter Iductr The utput iductaces required fr the cvetial ZVS PSFB cverter ad the prpsed cverter are give by 28 ad 29, respectively. The applied vltage t the utput iductr f the prpsed cverter is decreased due t the 50% fixed duty perati ad the vltage acrss the bst capacitr V Cr. Thus, the required utput iductace fr the same ripple curret cditi ca be sigificatly reduced i the prpsed cverter, as cmpared with that f the cvetial ZVS PSFB cverter. This prperty culd icrease the pwer desity f the system, i.e., L.ZVS PSFB = [V i/ ZVS.PSFB V ] DT s 28 ΔI L.prpsed = [V i v Cr t / V ] ΔI [ CV V + V i I V I + LC si 1 ] V IV I 2. +VV + V i 2 L C IV. DESIGN EXAMPLE 29 T verify the feasibility f the prpsed cverter, a simple desig example with the fllwig specificatis is take. A. Desig Specificatis 1 Iput vltage V i : V; 2 Output vltage V :12V;

6 SHIN et al.: PULSE-FREQUENCY-MODULATED FULL-BRIDGE DC/DC CONVERTER WITH SBC 5159 Fig. 9. PSIM simulati results. a ZVS PSFB cverter ad b prpsed PFM-SBC full-bridge dc/dc cverter. 3 Output pwer P : 1200 W; 4 Switchig frequecy f sw V i = 400 V,I = 100 A = 60 khz. B. Trasfrmer Tur Rati As metied i Secti III, the tur rati f trasfrmer ca be decided frm 20. I additi, t esure the regulated utput vltage, the trasfrmer tur rati must be decided at the miimum iput vltage. Whe the iput vltage is miimum 320 V, the cverter is perated at the miimum switchig frequecy f sw. mi /f.iff sw. mi /f, which is the desiger s chice ad is prprtial t the switchig frequecy variati, is chse as 1.9, the trasfrmer tur rati ca be calculated as 35. C. Magetizig Iductr L m ad Bst Capacitr C r f sw. max /f ca be calculated as 4.1 frm 20 whe the iput vltage is maximum 400 V. Assumig that the switchig frequecy at the maximum iput vltage 400 V is chse as 60 khz, csiderig the verall system efficiecy ad vlume, the miimum switchig frequecy at the miimum iput vltage 320 V ca be btaied as 27.8 khz frm 20. I particular, if the vltage acrss the bst capacitr exceeds V i + V a, the prpsed cverter cat prperly perate, where V a is the icreased amut i v Cr by the eergy stred i the leakage iductr after v Cr becmes equal t V i. Assumig that the leakage iductace L k is 2% f the magetizig iductace L m, the characteristic impedace Z shuld be desiged t be less tha frm 31. Fially, the magetizig iductace L m ad the bst capacitr C r are calculated as fllws: V a = L k I V + I 1 C r 10 2L m I V + I 30 C r Z V i. mi + 2 V i. mi si0.5ω /f sw. mi 10 1+cs0.5ω /f sw. mi I si0.5ω /f sw. mi 1+cs0.5ω /f sw. mi 2I 10 = [Ω] 31 L m Z ω = [μh], selected as L m = 1000 [μh] 32 C r L m Z 2 =53.5 [F], selected as C r =66[F]. 33 V. S IMULATION AND EXPERIMENTAL RESULTS I rder t verify the perati f the prpsed cverter, PSIM simulati ad experimet are perfrmed with the specificatis f the iput vltage V i = V, the utput vltage V =12 V, the maximum utput pwer P. max = 1.2 kw, the hldup time = 20 ms, the magetizig iductr L m =1 mh, the leakage iductr L k =22 μh, the utput iductr L =1.8 μh, the bst capacitr C r =66F, ad the utput capacitr C = 1550 μf. A. Simulati Results Fig. 9 shws the simulati results f the cvetial ZVS PSFB ad prpsed PFB-SBC full-bridge cverters. T cmpare the prpsed cverter with the cvetial ZVS PSFB cverter, simulatis are perfrmed uder the same cditis such as the switchig frequecy f sw, the magetizig iductace L m, ad the utput iductr L. As a result, the cvetial ZVS PSFB cverter has lg freewheelig itervals f abut 0.2T s, ad thereby, the peak primary curret I pri. max is measured as 7.18 A. O the ther had, the peak primary curret I pri. max f the prpsed cverter is measured as 4.62 A, which is because there exist freewheelig itervals i the prpsed cverter. Mrever, while the utput iductr curret ripple Δi L.PFM SBC f the prpsed cverter is as small as 8.48 A, Δi L.ZVS PSFB f the cvetial cverter is 25 A uder the same utput iductr L =1.8 μh. Therefre, the utput iductr f the prpsed cverter ad the subsequet cducti lss ca be mre reduced tha thse f the cvetial ZVS PSFB cverter. B. Experimetal Results The prttype f the prpsed cverter shw i Fig. 2 is implemeted with the specificatis f primary switches M 1 M 4 = SPP20N60C3, trasfrmer cre = tw verlapped EI3329vlume : mm 3,μ r : 2070, trasfrmer tur rati = 35:1:1, utput iductr cre = CH vlume : 4154 mm 3,μ r : 60, bst capacitr C r = plyprpylee film capacitr f 33 F2EA, ad sychrus rectifiers SRs M SR1 /M SR2 = IRFB3077. T reduce the trasfrmer cpper lsses caused by the prximity effect, a sadwich widig methd is emplyed, which ca reduce the alteratig-curret resistace depedig the wire type, mea legth, ad

7 5160 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011 Fig. 10. Key experimetal wavefrms. a I =20A; b I =50A; c I =80A; ad d I = 100 A. TABLE I MEASURED DATA OF THE PROPOSED CONVERTER AT V i = 400 V peratig frequecy. Mrever, t reduce the cducti lsses f the utput rectifier, the SRs are emplyed i the trasfrmer secdary side. Fig. 10 shws the key wavefrms f the M 1 gate sigal, the drai surce vltage V ds_m1 acrss switch M 1, ad the trasfrmer primary curret i pri. Mrever, Table I shws the measured data f the prpsed cverter. Althugh the small differece betwee the measured ad calculated utput vltages exists, they well cicide with the afremetied theretical results. This small differece rigiated frm the duty cycle lss, as stated abve. Sice switch M 1 is tured after the drai surce vltage drps t 0 V, the ZVS ca be achieved. Mrever, sice the switchig frequecy variati is t s wide as t the rage f 58.8 I = 100 A t 76.8 khz I =0A, the reactive cmpets such as the iductr, the trasfrmer, ad the capacitrs ca be easily desiged t be perated at ptimum cditis. As shw i this figure, the primary dc ffset curret ad the freewheelig itervals d t exist with the aid f the 50% fixed duty perati. Thus, it cat ly reduce the size f the trasfrmer but als imprve the device heat geeratis ad system efficiecy. As shw i Fig. 10d, the peak ad RMS values f the primary curret measured at full lad cditi are t s large, i.e., 4.3 ad A, respectively. Whe the utput iductr L is 1.8 μh, Fig. 11a shws the curret ripple thrugh the utput iductr at the full-lad cditi. While the curret ripple f the cvetial ZVS PSFB cverter is 25 A, that f the prpsed cverter is as small as 12.9 A with L =1.8 μh. I additi, whe the utput iductr is reduced frm 1.8 t 1 μh, Fig. 11b shws that the curret ripple thrugh the utput iductr is 17.1 A. Althugh the curret ripple is icreased by 4.2 A, it is still smaller tha that f the ZVS PSFB cverter. Therefre, the reduced wire legth ca csiderably reduce the cpper lss f the iductr wire. Mrever, the size f the utput capacitr ca be als reduced due t the reduced RMS curret thrugh the capacitr. Fig. 12 shws the cmparis f the measured efficiecy betwee the cvetial ZVS PSFB ad prpsed cverters. As shw i this figure, the prpsed cverter ca achieve apprximately 2% higher efficiecy alg wide lad rages A, ad its efficiecy at the full-lad cditi is as high as 96.57%. This high efficiecy rigiated frm freewheelig iterval, reduced ripple curret thrugh the utput iductr, ad subsequet reduced cducti lsses with the aid f the 50% fixed duty perati. VI. CONCLUSION The PFM-SBC full-bridge dc/dc cverter has bee prpsed i this paper. The cvetial ZVS PSFB cverter has large circulatig eergy durig the freewheelig iterval caused by the small duty cycle, which culd icrease the primary-side

8 SHIN et al.: PULSE-FREQUENCY-MODULATED FULL-BRIDGE DC/DC CONVERTER WITH SBC V/100 A have bee preseted. The experimetal results have verified the validity f the peratial priciple ad have demstrated that the prpsed cverter ca achieve efficiecy as high as ver 96.25% alg lad rages f A. The prpsed cverter havig these favrable advatages is expected t be well suited fr high-pwer-desity applicatis. Fig. 11. Curret ripple thrugh the utput iductr at the full-lad cditi. L = a 1.8 ad b 1.2 μh. Fig. 12. Cmparis f the measured efficiecy betwee the prpsed ad cvetial ZVS PSFB cverters. cducti lsses, the tur-ff switchig lsses f laggig-leg switches, ad the curret ripple thrugh the utput iductr. T vercme these prblems, the prpsed cverter regulates the utput vltage by varyig the vltage acrss the SBC accrdig t the switchig frequecy ad has freewheelig iterval with the aid f the 50% fixed duty perati. As a result, it ca csiderably reduce cducti lsses ad curret ripple thrugh the utput iductr, as cmpared with the cvetial ZVS PSFB cverter. Mrever, the ZVS perati f all pwer switches ca be achieved alg wide lad rages. Therefre, it has very desirable merits such as small utput iductr, high efficiecy, ad imprved heat geerati. Fially, t cfirm the perati, the features, ad the validity f the prpsed cverter, experimetal results frm a prttype f REFERENCES [1] J. A. Sabate, V. Vlatkvic, R. B. Ridley, F. C. Lee, ad B. H. Ch, Desig csideratis fr high-vltage high pwer full-bridge zer vltageswitched PWM cverter, i Prc. IEEE Appl. Pwer Electr. Cf., 1990, pp [2] P. K. Jai, W. Kag, H. Si, ad Y. Xi, Aalysis ad desig csideratis f a lad ad lie idepedet zer vltage switchig full bridge dc/dc cverter tplgy, IEEE Tras. Pwer Electr., vl. 17,. 5, pp , Sep [3] L. H. Mweee, C. A. Wright, ad M. F. Schlecht, A 1 kw 500 khz frted cverter fr a distributed pwer supply system, IEEE Tras. Pwer Electr., vl. 6,. 3, pp , Jul [4] D. M. Sable ad F. C. Lee, The perati f a full-bridge zer-vltage switched PWM cverter, i Prc. VPEC Semi., 1989, pp [5] J. M. Zhag, X. G. Xie, X. K. Wu, ad Z. Qia, Cmparis study f phase-shifted full bridge ZVS cverters, i Prc. Au. IEEE Pwer Electr. Spec. Cf., 2004, pp [6] J. G. Ch, J. A. Sabate, G. Hua, ad F. C. Lee, Zer-vltage ad zer-curret-switchig full bridge PWM cverter fr high-pwer applicatis, IEEE Tras. Pwer Electr., vl. 11,. 4, pp , Jul [7] J. G. Ch, J. W. Baek, C. Y. Jeg, D. W. Y, ad K. Y. Je, Nvel zer-vltage ad zer-curret-switchig full bridge PWM cverter usig trasfrmer auxiliary widig, IEEE Tras. Pwer Electr., vl. 15,. 2, pp , Mar [8] E. S. Kim, K. Y. Je, M. H. Kye, Y. H. Kim, ad B. D. Y, A imprved sft-switchig PWM FB dc/dc cverter fr reducig cducti lsses, IEEE Tras. Pwer Electr., vl. 14,. 2, pp , Mar [9] J. G. Ch, J. W. Baek, C. Y. Jeg, ad G. H. Rim, Nvel zer-vltage ad zer-curret-switchig full-bridge PWM cverter usig a simple auxiliary circuit, IEEE Tras. Id. Appl., vl. 35,. 1, pp , Ja./Feb [10] S. T. Tig ad H. Niaci, A vel zer-vltage ad zer-curretswitchig full-bridge PWM cverter, i Prc. IEEE Appl. Pwer Electr. Cf., 2003, pp [11] S. Misseev, S. Sat, S. Hamada, ad M. Nakaka, Full bridge sftswitchig phase-shifted PWM dc-dc cverter usig tapped iductr filter, i Prc. IEEE Pwer Electr. Spec. Cf., 2003, pp [12] E. H. Kim ad B. H. Kw, Zer-vltage- ad zer-curret-switchig full-bridge cverter with secdary resace, IEEE Tras. Id. Electr., vl. 57,. 3, pp , Mar [13] K. W. Sek ad B. H. Kw, A imprved zer-vltage ad zer-curretswitchig full-bridge PWM cverter usig a simple resat circuit, IEEE Tras. Id. Electr., vl. 48,. 6, pp , Dec [14] X. Rua ad Y. Ya, A vel zer-vltage ad zer curret switchig PWM full-bridge cverter usig tw dides i series with the laggig leg, IEEE Tras. Id. Electr., vl. 48,. 4, pp , Aug [15] F. Liu, J. Ya, ad X. Rua, Zer-vltage ad zer-curret-switchig PWM cmbied three-level dc/dc cverter, IEEE Tras. Id. Electr., vl. 57,. 5, pp , May [16] N. I. Kim ad G. H. Ch, ZVZCS full-bridge PWM dc/dc cverter usig a vel LCD eergy-recvery subber, i Prc. IEEE PESC, 2006, pp [17] W. Li, Y. She, Y. Deg, ad X. He, A ZVZCS full-bridge dc/dc cverter with a passive auxiliary circuit i the primary side, i Prc. IEEE PESC, 2006, pp [18] J. Dudric, P. Spaic, ad N. D. Trip, Zer-vltage ad zer-curret switchig full-bridge dc dc cverter with auxiliary trasfrmer, IEEE Tras. Pwer Electr., vl. 21,. 5, pp , Sep [19] X. Rua ad B. Li, Zer-vltage ad zer curret switchig PWM hybrid full-bridge three-level cverter, IEEE Tras. Id. Electr., vl. 52,. 1, pp , Feb [20] M. M. Walters ad W. M. Plivka, Extedig the rage f sft-switchig i resat-trasiti dc-dc cverters, i Prc. IEEE INTELEC, 1992, pp

9 5162 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011 Yg-Saeg Shi received the B.S. ad M.S. degrees i electric egieerig frm Kkmi Uiversity, Seul, Krea, i 2007 ad 2009, respectively, where he is curretly wrkig tward the Ph.D. degree. His curret research iterests are i the areas f aalysis, mdelig, desig, ad ctrl f pwer cverters. Chag-Sep Kim received the B.S., M.S., ad Ph.D. degrees i electrical egieerig frm Seul Natial Uiversity, Seul, Krea, i 1984, 1986, ad 1990, respectively. Frm 1992 t 2003, he was a Researcher with Krea Eergy Maagemet Crprati, Ygi, Krea. Frm 2003 t 2008, he was a Prfessr with the Graduate Schl f Kwledge-Based Techlgy ad Eergy, Krea Plytechic Uiversity, Siheug, Krea. Sice 2009, he has bee a Prfessr with the Departmet f Electrical Egieerig, Kyugw Uiversity, Segam, Krea. He is curretly a Represetative with the Istitute f Sustaiable Csumpti ad Prducti, the Assistat Admiistratr with the Departmet f Gree Grwth, Miistry f Public Admiistrati ad Security, ad the Vice Directr i the Departmet f Petrleum Mitr, Csumers Krea. Sag-Ky Ha S 04 M 10 received the B.E. degree i electrical egieerig frm Pusa Natial Uiversity, Pusa, Krea, i 1999, ad the M.S. ad Ph.D. degrees i electrical egieerig ad cmputer sciece frm Krea Advaced Istitute f Sciece ad Techlgy KAIST, Daeje, Krea, i 2001 ad 2005, respectively. Fr the ext six mths, he was a Pstdctral Fellw with KAIST, where he develped digital display pwer circuits ad prefrmed several research activities. Sice 2005, he has bee a Assistat Prfessr with the Departmet f Electrical Egieerig, Kkmi Uiversity, Seul, Krea, ad has wrked fr Samsug Pwer Electrics Ceter ad Samsug Netwrk Pwer Ceter as a Research Fellw. His primary areas f research iterest iclude pwer cverter tplgies, pwer factr cteti cverters, light-emittig dide drivers, reewable eergy system, ad battery charger fr electric vehicle. Dr. Ha is a member f the Krea Istitute f Pwer Electrics.