The fan-in of a logic gate is defined as the number of inputs that the gate is designed to handle.

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1 8 Lgic Families Characteristics f Digital IC Threshld Vltage The threshld vltage is defined as that vltage at the input f a gate which causes a change in the state f the utput frm ne lgic level t the ther. Prpagatin Delay A pulse thrugh a gate takes a certain amunt f time t prpagate frm input t utput. This interval f time is knwn as the prpagatin delay f the gate. Pwer dissipatin The pwer dissipatin f a lgic gate is the pwer required by the gate t perate with 50% duty cycle at a specified frequency and is expressed in mill watts. Fan-in The fan-in f a lgic gate is defined as the number f inputs that the gate is designed t handle. Fan-ut The fan-ut (lading factr) f a lgic gate is defined as the maximum number f standard lads that the utput f the gate can drive withut impairing its nrmal peratin. Nise Margin When the digital circuits perate in nisy envirnment the gates may malfunctin if the nise is beynd certain limits. The nise immunity f a lgic circuit refers t the circuit s ability t tlerate nise vltages at its input. A quantitative measure f nise immunity is called nise margin. Operating temperatures The IC gates and ther circuits are temperature sensitive being semicnductr devices. Hwever they are designed t perate satisfactrily ver a specified range f temperatures. The range specified fr cmmercial applicatins is 0 t 70 C, fr industrial it is 0 t 85 C and fr military applicatins it is -55 C t 125 C. Speed Pwer Prduct A cmmn means fr measuring and cmparing the verall perfrmance f an IC family is the speed pwer prduct which is btained by multiplying the gate prpagatin delay by the gate pwer dissipatin. The smaller the prduct, the better the verall perfrmance. Transistr-Transistr Lgic (TTL) The TTL is s named because f its independence n transistrs alne t perfrm basic lgic peratins. The TTL uses transistrs perating in saturated mde. It is the fastest f saturated lgic families. The basic TTL lgic circuit is the NAND gate. Gd speed, lw manufacturing cst, wide range f circuits and the availability in SSI and MSI are its advantages. Tight V CC tlerance, relatively high pwer cnsumptin, mderate packing density, generatin f nise spikes and susceptibility t pwer transients are its disadvantages. TTL lgic family cnsists f several subfamilies such as: Hardik A. Dshi, CE Department Digital Electrnics 1

2 Standard TTL High Speed TTL Lw Pwer TTL Schttky TTL Lw Pwer Schttky TTL Advanced Schttky TTL Advanced Lw Pwer Schttky TTL F (Fast) TTL Fr standard TTL, Prpagatin Delay time = 9 ns Pwer dissipatin per = 10 mw Nise Margin = 0.4 mv Fan-in = 8 Fan-ut = 10 Lgic 0 = 0 V t 0.8 V Lgic 1 = 2 V t 5 V Indeterminate Range = 0.8 V t 2 V Emitter-Cupled Lgic (ECL) MOSFET This lgic family is als called Current Mde Lgic r Current Steering Lgic. It is the fastest f all lgic families. Hardik A. Dshi, CE Department Digital Electrnics 8 Lgic Families ECL perates n the principle f current switching, whereby a fixed bias current less than IC switched frm ne transistr s cllectr t anther. Because f this mde peratin, this lgic frm is als referred t as Current Mde Lgic (CML). It is als called Current Steering Lgic (CSL), because current is steered frm ne device t anther. The ECL family is used in very high frequency applicatins where its speed is superir. The imprtant characteristics f ECL are: Transistrs never saturate. S, speed is high Lgic Levels are negative, -0.9 V fr Lgic 1 and -1.7 V fr Lgic 0. Nise Margin is less, abut 250 mv. This makes ECL, unreliable fr use in heavy industrial envirnment. ECL circuits prduce the utput and its cmplement, and therefre, eliminate the need fr inverters. Fan-ut is large because the utput impedance is lw. It is abut 25. Pwer dissipatin per gate is large. The ttal current flw in ECL is mre r less cnstant. S, n nise spikes will be internally generated. MOSFET family are simpler & inexpensive t fabricate, require much less pwer, have better nise margin, a greater supply vltage range, a higher fan-ut and require much less chip area as cmpared t ther biplar lgic families. Fr MOS lgic, Prpagatin Delay, t pd = 50 ns. Nise Margin, NM = 1.5 V. 2

3 8 Lgic Families Pwer Dissipatin, PD = 0.1 Mw. Fan ut = 50 fr frequencies greater than 100 Hz and it is virtually unlimited fr dc r lw frequencies. The prpagatin delay assciated with MOS gates is large (50 ns) because f their high utput resistance (100 k) and capacitive lading presented by the driven gates. There are three types f MOSFET: P-channel MOSFET (PMOS) Enhancement Type PMOS Depletin Type PMOS N-channel MOSFET (NMOS) Enhancement Type NMOS Depletin Type NMOS Cmplementary MOSFET (CMOS) Cmpare TTL, ECL, & CMOS lgic families. Characteristic TTL CMSO ECL Pwer Input Mderate Lw Mderate-High Frequency limit High Mderate Very high Circuit density Mderate-high High-very high Mderate Circuit types per family High High Mderate Lgic Family Prpagatin delay time (ns) Pwer dissipatin per gate (mw) Nise Margin (V) Fan-in Fan-ut Cst TTL Lw CMOS < Lw ECL High CMOS NAND Gate Figure shws a CMOS tw-input NAND gate and its equivalent circuits fr varius input cmbinatins. Hardik A. Dshi, CE Department Digital Electrnics 3

4 8 Lgic Families Here Q 1 and Q 2 are parallel-cnnected PMOS transistrs, and Q 3 and Q 4 are series-cnnected NMOS transistrs. Hardik A. Dshi, CE Department Digital Electrnics 4

5 8 Lgic Families When A = 0 V and B = 0 V, V GS1 = V GS2 = -5 V, V GS3 = V GS4 = 0 V. S Q 1 is ON, Q 3 is OFF, Q 2 is ON and Q 4 is OFF. Thus, the switching circuit (b) results with V ut = +5 V. When A = 0 V and B = +5 V, V GS1 = -5 V, V GS2 = 0 V, V GS3 = 0 V, V GS4 = 5 V. S Q 1 is ON, Q 3 is OFF, Q 2 is OFF and Q 4 is ON. Thus, the switching circuit (c) results with V ut = +5 V. When A = +5 V and B = 0 V, V GS1 = 0 V, V GS2 = -5 V, V GS3 = 5 V, V GS4 = 0 V. S Q 1 is OFF, Q 3 is ON, Q 2 is ON and Q 4 is OFF. Thus, the switching circuit (d) results with V ut = +5 V. When A = +5 V and B = +5 V, V GS1 = V GS2 = 0 V, V GS3 = V GS4 = 5 V. S Q 1 is OFF, Q 3 is ON, Q 2 is OFF and Q 4 is ON. Thus, the switching circuit (e) results with V ut = 0 V. Hardik A. Dshi, CE Department Digital Electrnics 5