Output Stages. Microelectronic Circuits. Ching-Yuan Yang. National Chung-Hsing University Department of Electrical Engineering.

Transcription

1 Micrelectrnic Circuits Output Stages Ching-Yuan Yang Natinal Chung-Hsing University Department f Electrical Engineering Outline Classificatin f Output Stages Class A Output Stage Class B Output Stage Class AB Output Stage Biasing the Class AB Circuit Variatins n the Class AB Cnfiguratin 14-1 Ching-Yuan Yang / EE, NCHU

2 Classificatin Of Output Stages 14- Ching-Yuan Yang / EE, NCHU Class A Stage The class A stage is biased at a current I C greater than the amplitude f the signal current, Î c. The transistr in a class A stage cnducts fr the entire cycle f the input signal; that is, the cnductin angle is Ching-Yuan Yang / EE, NCHU

3 Class B Stage The class B stage is biased at zer dc current. The transistr in a class B stage cnducts fr nly half f the cycle f the input sine wave, resulting in a cnductin angle f Ching-Yuan Yang / EE, NCHU Class AB Stage An intermediate class between A and B, named class AB, invlves biasing the transistr at a nnzer dc current much smaller than the peak current f the sine-wave signal. The transistr in a class AB stage cnducts fr a interval slightly greater than half a cycle. The resulting cnductin angle is greater than 180 but much less than Ching-Yuan Yang / EE, NCHU

4 Class C Stage The transistr in a class C stage cnducts fr an interval shrter than that f a half cycle; that is, the cnductin angle is less than 180. Class C amplifiers are usually emplyed fr radi-frequency (RF) pwer amplificatin (required, fr example, in mbile phnes and TV transmitters) Ching-Yuan Yang / EE, NCHU Class A Output Stage 14-7 Ching-Yuan Yang / EE, NCHU

5 Transfer Characteristic Because f its lw utput resistance, the emitter fllwer is the mst ppular class A utput stage. An emitter fllwer (Q 1 ) biased with a cnstant current I supplied by transistr Q : Since i E1 I + i, the bias current I must be greater than the largest negative lad current; therwise, Q 1 cuts ff and class A peratin will n lnger be maintained. The transfer characteristic f the emitter fllwer: v O v I v BE1 where v BE1 depends n the emitter current i E1 and thus n the lad current i Ching-Yuan Yang / EE, NCHU Transfer characteristic f the emitter fllwer: v O v I v BE1 The linear characteristic is btain by neglecting the change in v BE1 with i. The maximum psitive utput is determined by the saturatin f Q 1 : v V V O max CC CE1sat In the negative directin, the limit f the linear regin is determined either by Q 1 turning ff r by Q saturating, depending n the values f I and R. Q 1 turning ff : vo min IR Q saturating : v V + V (the abslutely lwest utput vltage) O min CC CE sat 14-9 Ching-Yuan Yang / EE, NCHU

6 Biasing current: The bias current I is greater than the magnitude f the crrespnding lad current. ( I i ) I V CC + V R CE sat Ching-Yuan Yang / EE, NCHU Signal Wavefrms (Neglect v CEsat ) Cnsider that maximum signal wavefrms are under the cnditin I V CC /R. v CE1 V CC v O The instantaneus pwer dissipatin in Q 1 : D1 v CE1 i C Ching-Yuan Yang / EE, NCHU

7 wer Dissipatin Maximum instantaneus pwer dissipatin in Q 1 V CC I. (v O 0). The pwer dissipatin in Q 1 depends n the value f R. If R, then i c1 I, cnstant. The maximum pwer dissipatin will ccur when v O V CC. D1 V CC I. The average pwer dissipatin in Q 1 is V CC I. If R 0, then A very large current may flw thrugh Q 1. It raises the junctin temperature beynd the specified maximum, causing Q 1 t burn up. Need shrt-circuit prtectin. The maximum instantaneus pwer dissipatin in Q is V CC I when v O V CC. A mre significant quantity fr design purpse is the average pwer dissipatin in Q, which is V CC Ching-Yuan Yang / EE, NCHU wer Cnversin Efficiency wer-cnversin efficiency Signal pwer delivered t lad ( ) η dc pwer supplied t utput circuit ( Average lad pwer O Ttal average supply pwer: 1V R S V CC I 100% ) Since the current in Q is cnstant (I ), the pwer drawn frm the negative supply is V CC I. The average current in Q 1 is equal t I, and thus the average pwer drawn frm the psitive supply is V CC I. Thus, the ttal average supply pwer is S V CC I. S Ching-Yuan Yang / EE, NCHU

8 Determine pwer-cnversin efficiency f the class A utput stage : η 1 4 Vˆ IR V O CC 1 Vˆ 4 IR O Vˆ V O CC Small signal, i.e., VˆO is small, η 0. static pwer cnsumptin V CC I even n excitatin. Since Vˆ O V CC and Vˆ O IR, maximum efficiency is btained when V ˆ V IR. η 5 max % O CC In practice the utput vltage is limited t lwer values in rder t avid transistr saturatin and assciated nnlinear distrtin. The efficiency achieved is usually in the 10% t 0% range. Class A peratin is a pr chice fr pwer amplificatin Ching-Yuan Yang / EE, NCHU Class B Output Stage Ching-Yuan Yang / EE, NCHU

9 Output Stages Ideal utput stages Supply external lad current w utput impedance arge utput swing V CC V EE (ideally) Cmmnly used cmplementary emitter fllwer Each transistr is n fr nly half the time Ching-Yuan Yang / EE, NCHU Circuit Operatin Class B utput stage cnsists f a cmplementary pair f transistrs cnnected in such a way that bth cnduct simultaneusly. v I 0, Q and Q N are cut ff and v O 0. v I > 0.5V, Q is cut ff ; Q N turns n and acts as an emitter fllwer. v O v I v BEN and Q N supplies the lad current. v I < 0.5V, Q N is cut ff ; Q cnducts and perates as an emitter fllwer. v O v I + v EB and Q supplies the lad current. Operatin in push-pull fashin: The transistrs in class B stage are biased at zer current and cnduct nly when the input signal is present. Q N pushes (surces) current int the lad when v I is psitive, and Q pulls (sinks) current frm the lad when v I is negative Ching-Yuan Yang / EE, NCHU

10 Transfer Characteristic There exists an range f v I centered arund zer where bth transistrs are cut ff and v O is zer. This dead band results in the crssver distrtin Ching-Yuan Yang / EE, NCHU Illustrating hw the dead band in the class B transfer characteristic results in crssver distrtin. The effect f crssver distrtin will be prnunced when the amplitude f the input signal is small. Crssver distrtin in audi pwer amplifiers gives rise t unpleasant sunds Ching-Yuan Yang / EE, NCHU

11 wer Cnversin Efficiency We neglect the crssver distrtin and cnsider the case f an utput sinusid f peak amplitude. Vˆ Average lad pwer Ttal supply pwer The peak amplitude f current draw frm supply: The average current draw frm supply: Vˆ π The average pwer drawn frm each f the tw pwer supplies: 1 Vˆ S + S VCC π R Vˆ The ttal supply pwer S VCC π R π Vˆ Efficiency η (14.15) 4 V CC ηmax π 78.5% when Vˆ VCC VCEsat VCC 4 1VCC Maximum average pwer available max R ˆ 1V R R Vˆ R 14-0 Ching-Yuan Yang / EE, NCHU wer Dissipatin Unlike the class A stage, which dissipates maximum pwer under quiescent cnditins (v O 0), the quiescent pwer dissipatin f the class B stage is zer. Average pwer dissipatin D S VCC D max π R Vˆ π R V CC By Eq. (14.15), at the pint f max. pwer dissipatin the efficient η 50%. Vˆ 1 Average lad pwer R ˆ 1V R D Maximum average pwer dissipatin 0 Vˆ when Vˆ V CC D max π V CC DN max D max π R 14-1 Ching-Yuan Yang / EE, NCHU

12 wer dissipatin f the class B utput stage versus amplitude f the utput sinusid. D Vˆ V π R CC ˆ 1V R Increasing Vˆ beynd V CC /π decreases the pwer dissipated in the class B stage while increasing the lad pwer. The price paid is an increase in nnlinear distrtin as a result f appraching the saturatin regin f peratin f Q and Q N. Transistr saturatin flattens the peaks f the utput sine wavefrm. This type f distrtin cannt be significantly reduced by the applicatin f negative feedback. The transistr saturatin shuld be avided in applicatins requiring lw THD. 14- Ching-Yuan Yang / EE, NCHU Example 9.1 Class B utput stage design The class B utput stage deliver an average pwer f 0W t an 8-Ω lad. Select the pwer supply such that V CC is abut 5V greater than the peak utput vltage. This avids transistr saturatin and the assciated nnlinear distrtin, and allws fr including shrtcircuit prtectin circuitry. Determine the supply vltage required, the peak current drawn frm each supply, the ttal supply pwer, and the pwer-cnversin efficiency. Als determine the maximum pwer that each transistr must be able t dissipate safely. Slutin Determine V CC : 1 Vˆ ˆ V V R R ˆ The peak current drawn frm each supply ˆ V 17.9 I.4A R 8 1 Vˆ 1 The average pwer drawn frm each supply S + S VCC W π R π Ttal supply pwer S+ + S 3.8W 0 The pwer-cnversin efficiency η 61% S 3.8 The maximum pwer dissipated in each transistr (3) π 8 CC DN max D max π R V 6.7W 14-3 Ching-Yuan Yang / EE, NCHU

13 Distrtin in the Class B ush-ull Stage Harmnic distrtin Fr matched devices Q N & Q i N and i are identical except shifted in phase by 180 i i i N I I i + B i ( ωt) i c c N N + B i 0 ( ωt + π ) 0 + B B 1 1 ( B csωt + B csωt + B 1 csωt + B cs ωt + B cs ωt B cs 3ωt + ) cs 3ωt + cs 3ωt + i N i Even-rder harmnic distrtins have been eliminated. If I -Vs f Q N & Q are nt identical, then even-rder harmnic is expected. Crssver distrtin: has been discussed befre Ching-Yuan Yang / EE, NCHU Reducing Crssver Distrtin Class B circuit with an p amp cnnected in a negative-feedback lp t reduce crssver distrtin The ±0.7V dead band is reduced t ±0.7/A 0 vlts, where A 0 is the dc gain f the p amp. Slew-rate limiting f the p amp Ching-Yuan Yang / EE, NCHU

14 Single-Supply Operatin Class B utput stage perated with a single pwer supply 14-6 Ching-Yuan Yang / EE, NCHU Class AB Output Stage 14-7 Ching-Yuan Yang / EE, NCHU

15 Class AB Output Stage Crssver distrtin can be virtually eliminated by biasing the cmplementary utput transistrs at a small, nn-zer current. A bias vltage V BB is applied between the bases f Q N and Q, giving rise t a bias current V BB /V i i I I e T (Assuming matched devices) N Q S 14-8 Ching-Yuan Yang / EE, NCHU Circuit Operatin in i iq v BEN + veb VBB VT ln + VT ln V T ln ini i IS IS IS As i N increases, i decreases by the same rati while the prduct remains cnstant. Q i N i + i in iin IQ Ching-Yuan Yang / EE, NCHU

16 Output resistance Determine the small-signal utput resistance f the class AB circuit R r ut en r e where r en and r e are the small-signal emitter resistances f Q N and Q, respectively. V T r en and in V r e i T R ut V i T N V i T VT i + i N Ching-Yuan Yang / EE, NCHU Biasing The Class AB Circuit Ching-Yuan Yang / EE, NCHU

17 Biasing Using Dides Class AB utput stage utilizing dides fr biasing. If the junctin area f the utput devices, Q N and Q, is n times that f the biasing devices D 1 and D, a quiescent current I Q ni bias flws in the utput devices Ching-Yuan Yang / EE, NCHU Example 14. Class AB utput stage design V CC 15V, R 100Ω, and the utput is sinusidal with a maximum amplitude f 10V. et Q N and Q be matched with I S A and β 50. Assume the biasing dides have ne-third the junctin area f the utput devices. Find the value f I bias that guarantees a minimum f 1mA thrugh the dide at all times. Determine the quiescent current and the quiescent pwer dissipatin in the utput transistrs (i.e., at v O 0 ). Als find V BB fr v O 0, +10V, and 10V. The maximum current thrugh Q N : i max 10V/0.1k Ω 100mA The maximum base current in Q N is ma. T maintain a min. f 1mA thrugh the dides, we select I bias 3mA. A quiescent current f 9mA thrugh Q N and Q. Quiescent pwer dissipatin DQ mW Fr v O 0, I B,Q1 9/ mA. I D I D1,D mA 1 13 Since the dides have I 3 10 S, then I D.8mA VBB VT ln 0.05 ln 1.6V I I S v O +10V I D 1mA V BB 1.1V v O 10V I D 3mA V BB 1.6V S Ching-Yuan Yang / EE, NCHU

18 Biasing using the V BE multiplier Find V BB : I R V R BE1 1 R + + VBB I R( R1 R) VBE1 1 R1 Determine V BE1 : I V C1 BE1 I bias V T I R I ln I C1 S Ching-Yuan Yang / EE, NCHU A discrete-circuit class AB utput stage with a ptentimeter used in the V BE multiplier. The ptentimeter is adjusted t yield the desired value f quiescent current in Q N and Q Ching-Yuan Yang / EE, NCHU

19 Variatins On The Class AB Cnfiguratin Ching-Yuan Yang / EE, NCHU Use f Input Emitter Fllwers High input resistance Quiescent current in Q 3 and Q 4 is equal t that in Q 1 and Q if R and R 3 R 4 0. R 3 and R 4 are small and are included t guard against the pssibility f thermal runaway due t temperature differences between the input and utput stage transistr Ching-Yuan Yang / EE, NCHU

20 Use f Cmpund Devices The Darlingtn cnfiguratin 1. increase current gain. reduce base current drive 3. Equivalent V BE(eq. ) V BE 4. can be used fr bth NN transistrs and N transistrs The cmpund-pnp cnfiguratin 1. used t imprve N cnfiguratin Q 1 is usually a lateral N having lw β ( 5 10) Ching-Yuan Yang / EE, NCHU A class AB utput stage utilizing a Darlingtn npn and a cmpund pnp. Biasing is btained using a V BE multiplier. Bias is btained using a V BE multiplier. V BE multiplier is required t prvide 3V BE Ching-Yuan Yang / EE, NCHU

21 Shrt-Circuit rtectin A class AB utput stage is equipped with prtectin against the effect f shrtcircuiting the utput while the stage is surcing current. A large current that flws thrugh Q 1 in the event f a shrt circuit will develp a vltage drp acrss R E1 f sufficient value t turn Q 5 n. The cllectr f Q 5 will then cnduct mst f the current I bias, rbbing Q 1 f its base drive. The current thrugh Q 1 will thus be reduced t a safe perating level. i V RE1 I C5 I B1 I C Ching-Yuan Yang / EE, NCHU Thermal Shutdwn Thermal shutdwn circuit Transistr Q is nrmally ff. As the chip temperature rises, a cmbinatin f psitive temperature cefficient f zener dide Z 1 and the negative temperature cefficient f V BE1 causes the vltage at the emitter f Q 1 t rise. This in turn raises the vltage at the base f Q t the pint at which Q turns n. T V Z1, V BE V R I C Q absrbs bias current f OAM Ching-Yuan Yang / EE, NCHU

22 Hmewrk rblem, 11, 16, 19, Ching-Yuan Yang / EE, NCHU