Lab 1 Fun with Diodes

Transcription

1 GOAL Lab 1 Fun with Dides The verall gal f this lab is t gain sme experience building and simulating sme useful dide circuits. OBJECTIVES T build, test, simulate, and understand the fllwing circuits: 1) Half-wave rectifier with smthing capacitr 2) Vltage limiter GENERAL GUIDELINES 1) Each student must build, test, and dem all circuits. 2) During the lab sessin, students may need t share test statins. 3) Students are allwed (even encuraged) t help each ther. Of curse, Prfessr Hedrick will be arund t prvide assistance as well. Use neat wiring fr yur circuits! A messy circuit will cst yu 10 pts frm yur lab dem grade. 4) D nt wrry if yu need lts f help during the lab. Just make sure yu knw yur stuff fr the exams. In additin t the written exams, there will be labratry exams where each student is tested n basic skills in circuit cnstructin and simulatin. 5) Ask questins! The mre questins yu ask, the mre yu learn. 6) Build yur circuits with neat wiring! Messy circuits will result in a deductin frm yur lab grade. Neat means: crrect wire clrs, using grund and pwer busses, and a minimum f excess and crssed wires and cmpnents. 7) Please keep yur lab kit and wrk area rganized. PARTS AND MATERIALS Lab kit (breadbard, wire stripper, wire) Digital scillscpe and test prbe Arbitrary wavefrm generatr and caxial cable (with alligatr clips) Dide: 1N40023 (1) Resistrs: 100 hm (brwn/black/brwn) (1) 10 khm (brwn/black/range) (1) Capacitrs: 1 uf electrlytic (1) 100 ufelectrlytic (1) LEDs: Green (1) Red (1) 1

2 PART 1: HALF-WAVE RECTIFIER Step 1a: build the circuit in Figure 1 _GND Step 1b: Input a sine wave (10 V PP, 60 Hz) t the rectifier circuit. Fig. 1: Half-wave rectifier circuit. Set the Agilent wavefrm generatr t High Z utput. First, press Utility Then Output Then High Z Finally, press Dne. Set the amplitude t 10 V PP and frequency t 60 Hz. Cnnect the utput f wavefrm generatr t the circuit input using the caxial cable with alligatr clips. Press the Output buttn n the wavefrm generatr t turn n the utput. NOTE: Remember that we discussed what this means in class: High Z means the lad is expected t be high impedance (as ppsed t 50, which is pretty lw). Otherwise, the generatr will utput TWICE the vltage that yu want (very annying fr this curse). Step 1c: Measure a few cycles f the rectified vltage. Yu can ask Prfessr Hedrick fr assistance if yu are unable t cnfigure each f the settings belw. Yur scpe trace shuld similar t yur PreLab1 (Circuit 1) simulatin! Press the Default buttn n the scpe. This resets the scpe. Use CH1 f the scpe t measure a few cycles f the rectified vltage. DO NOT PRESS AUTOSCALE! Prfessr Hedrick will deduct 300 pts frm yur lab grade if he catches yu pressing autscale. CH1 vltage scale = 1 V/div CH1 zer psitin = -2.0 V Hrizntal time scale = 5 ms/div Trigger Level = 3 V Make sure yu scpe prbe is set t 10X, therwise yur measured vltages will be ff by a factr f 10! Measure the peak vltage using Measure >> Vmax n the scpe and recrd this value. Use the swave cmmand in MATLAB t capture a scpe trace. Save this scpe snapsht (e.g. jpg r emf file) fr yur lab reprt. 2

3 PART 2: HALF-WAVE RECTIFIER WITH SMOOTHING CAPACITOR Step 2a: Fig. 2 shws the circuit fr testing. Place the 1 uf electrlytic capacitr in parallel with the 10 k Ω resistr. Remember that electrlytic capacitrs must be prperly inserted int the circuit! Apply the 10V PP, 60 Hz sine wave t the input. _GND 1u C1 Fig. 2: Half-wave rectifier with 1 uf smthing capacitr. Step 2b: Measure the lad vltage with the scpe. Yur scpe trace shuld like the PreLab1(Circuit2) simulatin! Yu shuld be able t use the same scpe settings as Step 1c. Measure the peak vltage using Measure >> Vmax n the scpe and recrd this value. Measure the vltage ripple using Measure >> VPP n the scpe and recrd this value. Capture a scpe trace in MATLAB and save this scpe snapsht fr yur lab reprt. Step 2c: Fig. 3 shws the next circuit fr testing. We can reduce vltage ripple by replacing the 1 uf capacitr with a 100 uf capacitr. Remember that electrlytic capacitrs must be prperly inserted int the circuit! _GND 100u C1 Step 2d: Measure the lad vltage with the scillscpe. Fig. 3: Smthing capacitr is nw 100 uf. Yu shuld find that the scpe trace lks pretty flat, but tends t flicker. This is because the scpe trigger is nt reliable, since the signal is s flat. Measure the peak vltage n the scpe and recrd this value. In rder t get a nice view f the vltage ripple, yu will need t make several changes t the scpe: CH1 cupling = AC (g t 1 >> COUPLING >> AC) CH1 vltage scale = 20 mv/div CH1 zer psitin = 0 V Trigger HF Reject = ON (g t TRIG MENU >> SET UP >> HF REJECT) Trigger level = 20 mv Yur scpe trace shuld lk like yur PreLab1(circuit3) simulatin wavefrm. Measure the vltage ripple and recrd this value. Capture a scpe trace in MATLAB and save this scpe snapsht fr yur lab reprt. 3

4 PART 3: VOLTAGE LIMITER The simple AC vltage tester is really a vltage limiter using LEDs instead f dides. Bth LEDs shuld light up! Nte that an actual AC vltage tester is usually capacitively cupled (a tpic we will cver sn ). Step 3a: Fig. 4 shws the vltage limiter circuit. Remember the (-) end f the LED is the flat end f the LED package. Remember that the green and red LEDs are pinting in ppsite directins! Apply a 10V PP, 10 Hz sine wave t the input. Bth LEDs shuld light up! Step 3b: Measure the lad vltage with the scillscpe. _GND 100 R1 GREEN LED RED LED Fig. 4: Vltage limiter circuit using green and red LEDs. Make the fllwing changes t the scpe settings: CH1 cupling = DC CH1 vltage scale = 1V/div CH1 zer psitin = 0 V Hrizntal time scale = 20 ms/div Trigger Level = 0 V Yur scpe trace shuld lk like yur PreLab1(circuit 4) simulatin. The signal is clipped at apprximately +/- 2V. The clipping is nt abrupt (the crners are pretty runded). Measure the maximum and negative vltages and recrd these values. Capture a scpe trace in MATLAB and save this scpe snapsht fr yur lab reprt. Step 3c: Reduce the functin generatr sine wave vltage t 1V PP. Yur scpe trace shuld nw lk like an undistrted 1V PP sine wave. Yu d NOT need t recrd a scpe trace. Why are the scpe traces in Step3b and 3c different? Yu must explain this difference in yur lab reprt. 4

5 PART 4: CIRCUIT DEMOS (30 PTS OF TOTAL LAB GRADE) Prfessr Hedrick will reset the scpe and ask yu t shw the fllwing scpe traces with the prper scpe settings: Half-wave rectifier with 1 uf capacitr (15 pts f lab dem grade) Input = 10 V PP, 60 Hz sine wave Scpe prbe measures lad vltage Scpe settings: CH1 vltage scale = 1 V/div CH1 zer psitin = -2.0 V Hrizntal time scale = 5 ms/div Trigger Level = 3 V Measurements = V MAX and V PP Vltage limiter (15 pts f lab dem grade) Input = 10 V PP, 60 Hz sine wave Scpe prbe measures lad vltage Scpe settings: CH1 vltage scale = 1 V/div CH1 zer psitin = 0 V Hrizntal time scale = 5 ms/div Trigger Level = 0.5 V Measurements = V MAX and V MIN NOTE: When yu dem yur circuits, Prfessr Hedrick will ask yu t perate the scpe WITHOUT USING THE AUTOSCALE BUTTON. Prfessr Hedrick will deduct 300 pts frm yur lab grade if yu press Autscale! (End f Lab 1) Spring