Circuit-Level Considerations for Mixed-Signal Programmable Components

Transcription

1 Field-Prgrammable Mixed Systems Circuit-Level Cnsideratins fr Mixed-Signal Prgrammable Cmpnents Luigi Carr, Marcel Negreirs, Gabriel Parmegiani Jahn, Adã Antôni de Suza Jr., and Denis Teixeira Franc Universidade Federal d Ri Grande d Sul The use f digital cmpensatin algrithms eliminates the errr intrduced by switches and the nnlinear behavir f MOS transistrs. This apprach greatly reduces analg area and permits field-prgrammable mixed-signal systems built with entirely digital technlgies. IN THE PAST DECADE, researchers have paid significant attentin t the design f hetergeneus embedded systems. Hwever, mst f their wrk fcused n digital hardware and assciated sftware, 1,2 which remain firmly rted in an all-digital envirnment. In cntrast, an embedded system must generally interface with the real wrld. At this level, mst signals are cntinuus time and can assume nly analg values. Mst sensrs (such as thse fr temperature, pressure, humidity, resistance, and s n) generate small vltages r currents, and systems must preprcess (amplify and filter) these signals befre using them. Currently, many applicatins use digital signal prcessing because f its fast design cycle, available tls, and integratin with current design methdlgies. Designers can use this technique in any prblem that des nt require a gigahertz frequency bandwidth r extremely lw pwer dissipatin. Nevertheless, althugh digital prcessrs can implement many analg functins, sme analg functins must be develped in the analg dmain. Fr example, amplifiers, lw-pass antialias filters, and an A/D cnverter can be develped nly in the analg dmain; the digital dmain has n equivalent. S althugh mst f a mixed-signal system might be digital, such systems still require analg functins. Fr linear behavir, a system shuld in principle use linear cmpnents. Hwever, linear capacitrs r resistrs in MOS technlgy take up t much area. Mrever, prgrammability generally cmes in the frm f MOS switches. These transistrs intrduce sme extra ple-zer pairs, and wrse, they have nnlinear vltage-current characteristics. We will shw that, even when using analg technlgies that allw cmpnents like linear capacitrs r resistrs, the resulting circuit will display nnlinear behavir because f the prgrammability requirement. Mrever, this apprach will still cnsume significant circuit area. Fr these reasns, designers need a new paradigm fr designing analg circuits. Here, we prpse the use f nnlinear analg cmpnents with digital cmpensatin. Such cmpnents can be area effective, allwing designers t easily build imprtant circuits. It is als pssible t directly develp this class f circuits in a digital technlgy. Mrever, the prpsed circuit technique is easily prgrammable using switches and incurs nly a slight perfrmance degradatin. Sme f ur results, such as thse fr amplifiers and integratrs, use nly a small area and demnstrate a perfect balance between the pssibility f prgramming an analg r a digital device in the same chip. This methdlgy allws the develpment f linear r sampled circuits like switched capacitrs. Althugh sme wrk has addressed analg fieldprgrammable gate arrays, 3-5 mst f it fcuses n the prttyping f analg functins like filters and amplifiers. Hwever, the embedded-systems market seems t require mixed-signal prgrammable systems, nt /03/$ IEEE Published by the IEEE Cmputer Sciety IEEE Design & Test f Cmputers

2 Cntinuus system Amplifier Antialias filter Sampler A/D cnverter Figure 1. Input path fr the target applicatins f the prpsed field-prgrammable mixed system (FPMS). nly analg circuits. In a mixed-signal cntext, the mst imprtant design parameter might be the tradeff between speed and accuracy, as in the case f Σ- cnverters. Mst f the signal prcessing shuld ccur in the digital dmain, because it is much simpler t design and easier t prttype and t autmate than in the analg dmain. Als, a mixed-signal chip will include a micrprcessr f sme srt that a designer culd use t develp the signal prcessing in the digital dmain. Cnsideratins fr mixed-signal prgrammable systems Many electrnic devices, such as current systemn-a-chip (SC) designs, cntain cmpnents that have increasing levels f integratin and fit int a single chip. Hwever, when it cmes t field cnfigurability, just as fr field-prgrammable gate arrays (FPGAs), the analg interface t the wrld which includes all cnditining and acquisitin circuits remains utside the IC. Maintaining this separatin requires external analg devices and increases the prbability f cnnectin-related malfunctins. Such a situatin is typical fr the analg frnt end in systems that perfrm tasks such as data acquisitin in cntrl and measurement applicatins. One gal f the prpsed prgrammable analg circuit is t cver such needs in a SC envirnment. Fr this envirnment, we wuld like t prvide a frnt-end analg subsystem that permits full develpment, prttyping, and testing f typical embedded applicatins. The entire field-prgrammable mixed system (FPMS) is usable in the same way as purely digital FPGAs. Designers culd then fully develp an acquisitin device cmpsed f a sensr, its cnditining circuitry, and the digital data manipulatin and strage blck n the FPMS device. They culd als avid testing delays by eliminating the need fr designing a bard and assembling all the necessary ICs and analg cmpnents. Figure 1 shws the typical frnt-end tplgy fr a desired target applicatin. A real-wrld, cntinuus-time prcess generally needs sme amplificatin, because sensrs rarely give the required vltage r current levels. Because f present-day technlgy and supprting tl sets, mst signal prcessing ccurs in the digital dmain, s an antialias filter is abslutely required. Finally, depending n the required cnverter s speed and reslutin, an applicatin might need a sampler t maintain the reslutin while wrking with fast signals. Assuming that Figure 1 cvers mst applicatins that we want t address, several parameters must be subject t prgrammability. The signal frm the cntinuus system can be either a current r a vltage signal, which means that the amplificatin stage shuld be able t change its input impedance and gain. In additin t this requirement, the signal s frequency respnse must be treatable in a secnd stage that can implement filters. This, in turn, means that we must be able t place ples and zers at certain frequencies. Finally, analg sampling shuld be ne f the prgrammable features. Yu shuld be able t chse whether A/D and D/A cnverters are multiplexed between channels and whether the system shuld trade speed fr reslutin in any f the A/D r D/A cnverters. Analg frnt-end tplgy Lking at Figure 1, we can divide the analg blck int three main parts. The first part receives and amplifies the analg signal; the secnd perfrms the antialias filtering n the signal; and the final blck cnverts the signal t the digital dmain. In a design, we must cnsider which tplgy t use in each f these stages t achieve an ptimal cmbinatin f prgrammability and verall perfrmance. Our initial effrts t design and test the building blcks fr the future FPMS lgic cell fcus n cntinuus-time circuits. Other grups have already used switched capacitr and switched current as the basic technlgy fr the prgrammable analg part. 3-5 In cntrast, we chse the cntinuus-time implementatin t ensure that all the circuitry befre the antialias filter wuld nt intrduce spurius frequencies. January February

3 Field-Prgrammable Mixed Systems Prgrammable amplifiers and instrumentatin amplifiers Ruting Figure 2. FPMS macrarchitecture. Prgrammable biquadratic filters Prgrammable integratrs Ruting Time-discrete prcessing and A/D cnversin First stage: Analg-signal amplificatin T amplify the input signal, we must prvide a blck that can implement vltage and current gain. We started with the well-knwn differential amplifier with three peratin amplifiers (p amps) and als prvided shrtcuts t allw ne input t use nly the final inverting stage. Thus, every tw analg inputs are assciated with three p amps, and are usable as differential vltage inputs. The first input f each pair can als bypass the input pair f p amps and use the third p amp as an inverting amplifier; the secnd input becmes unavailable. Secnd stage: Antialias filtering Just after amplificatin, the signal must pass thrugh an antialias filter befre it underges A/D cnversin. The antialias filter s underlying cmplexity strngly relates t the A/D cnversin prcess and the sampling rati. Therefre, if the applicatin requires a high sampling rate, it is mre likely t have an A/D cnversin prcess that cannt be strngly versampled, hence the need fr an effective analg antialias filter. On the ther hand, if a high versampling rati is allwable, even a single-ple integratr can serve as an antialias filter. We can nw picture tw distinct blcks, ne with a cmplete, prgrammable antialias-filter design and the ther with single integratrs. Each f these grups can cnnect t the first rw f amplifying cells thrugh a cnnectin netwrk. Anther prject pssibility is t design the entire blck as a set f integratr r gain cells that designers can rearrange t prvide higher-rder antialias filters. Researchers have used this type f design with arrays in sme switched-capacitr wrk; 3-5 these designs are als an ptin fr further analysis. In ur initial architecture, we chse t have bth integratrs and secnd-rder antialias filters, and prvided internal paths, allwing designers t cascade these cells t frm higher-rder filters. We can use tw different tplgies t actually implement the prgrammable analg part. The first tplgy culd be ne presented earlier, which ffers an array f amplifiers, switches, and capacitrs. 3-5 This wrk uses nly linear devices, a distinct disadvantage in terms f area usage. The prgrammable tplgy prpsed by Pavan, Tsividis, and Nagaraj wuld be anther pssibility. 6 This wrk addresses the prblem f filter prgrammability; its implementatin uses nly MOS transistrs and gate-t-channel capacitrs. Althugh this implementatin uses nnlinear capacitrs, the capacitrs are biased s that they perate in their linear regin. Our apprach is quite different than all previus wrk because it des nt cancel r mask nnlinearities in the analg dmain, but rather wrks within the digital dmain. Final stage: Discrete-time and signal digitalizatin We will separate this stage frm the filtering rw by using a cnnectin netwrk t assign each A/D cnversin input t a filter utput. Yu can use the same netwrk t perfrm time multiplexing f the A/D cnverters. Using a Σ- cnverter autmatically lets the designer custmize the A/D cnversin, balancing sampling rate and data reslutin. The entire system is based n versampling and cnsists f an integratr, a ne-bit A/D cnverter, and a ne-bit D/A cnverter n the analg side, plus a digital filter. Once the input signal reaches this last rw f cells in the FPMS, it has already passed the antialias filter. Thus, an implementatin might use discrete-time techniques, such as switched capacitrs r currents, t perfrm additinal signal prcessing, befre cnverting the signal t the digital dmain. The implementatin can apply a mre selective filter t narrw the band f allwed frequencies r t eliminate envirnmental nise. This last set f cells is definable as a standard, recnfigurable switched-capacitr filter directly cnnected t the input f each cnversin cell. Alternatively, yu can use these cells as a new rw f intercnnectable cells between filtering and cnversin stages. 3-5 Figure 2 presents the prpsed FPMS macrarchitecture. Fr each grup f eight inputs, fur prgrammable biquadratic filters are available t wrk as antialias filters, as well as fur prgrammable integratrs. As mentined earlier, yu can cascade these filters t prduce mre cmplex filters when versampling is nt pssible. 78 IEEE Design & Test f Cmputers

4 After the antialias filters, further amplificatin is pssible, but nw wuld ccur in the sampled data dmain f switched capacitrs. The next blck cnsists f prgrammable cmpnents targeted t implement A/D and D/A cnverters, fllwed by regular digital prcessing. Analg prgrammability and nnlinear behavir In discussing analg prgrammability in nnlinear behavir, it is necessary t discuss surces f nnlinearity in switches, as well as externally linear, internally nnlinear circuits. We als discuss adaptive filters, which generally wrk with linear systems. Surces f nnlinearity in switches The cncept f prgrammability in the analg dmain intrduces several prblems. Let us take a simple prgrammable integratr as an example. Imagine that bth R and C are linear. Hwever, in a prgrammable device, yu wuld expect the value f R and C t be prgrammable, at least. This requires placement f a set f switches that permit the cnnectin f capacitrs and resistrs in series-parallel arrays. The imprtant pint is that a switch will always intrduce charge sharing and extra resistivity in the signal path. A secnd level f prgramming related t the cnnectin f different analg blcks (such as filters, A/D cnverters, r amplifiers) culd aggravate these prblems. It is pssible t implement an integratr cnnecting tw capacitrs C and single resistr R. Cnsider an ideal peratinal amplifier, but include resistance R d f the switch and the drain and surce capacitance, C d. The frequency respnse f the mdel in Figure 1 is v 1 scr d+ sc drd + 1 sr C d d = 2 v i 2 srcc + sc srrdc d + Rd + R d d This equatin shws a clear frequency respnse mdificatin because f the intrductin f extra ples and zers, and assumes linear devices. The switch, implemented with MOS devices, actually has a nnlinear resistance (dependent n the vltage acrss it), as well as parasitic capacitrs, which are junctin capacitrs, and hence als vltage dependent. Externally linear, internally nnlinear circuits The simple mathematical study develped in the previus sectin shws that any prgrammable analg cnnectin develped with MOS devices wuld require a dedicated and cmplex cmpensatin circuit t restre the desired analg behavir. Mrever, such MOS-based devices severely cmprmise simple peratins like prviding gain because any switch wuld intrduce a frequency-dependent behavir, requiring further cmpensatin fr stability r an extremely limited passband. Any apprach using MOS devices as switches will intrduce nnlinearities in the signal path, necessitating a crrectin circuit. Hwever, this crrectin circuit wuld intrduce an area verhead, which wuld add t the large area fr the linear array f capacitrs. Mrever, as shwn befre, prgrammability implies a certain nnlinearity, which the circuit must cmpensate fr in ne way r anther, even when it uses linear cmpnents. Fr example, the area fr the cmpensatin circuit f a linear MOSFET-C filter is rughly 23% f the analg part, and the linear capacitr area adds anther 23% t the ttal circuit area. 7 Researchers have discussed the advantage f using gate-t-channel capacitance. 6,8,9 Mre recent wrk examined nnlinear devices manufactured in a typical 0.25-micrn prcess with five metal layers. Fr these devices, the capacitance-t-area rati f the gate-tchannel capacitr culd be seven times higher than the rati fr the ply-ply capacitr and 35 times the capacitance available in a sandwich f all metal layers and ply. 9 This wrk shws that the use f nnlinear circuits in the analg part f mixed-signal systems prduces huge area advantages. Of curse, the vltage dependence f such capacitances als causes nnlinearities in the signal-prcessing circuit s utput. T cpe with these prblems f area and parasitic nnlinearity, we suggest using a new class f circuits, with externally linear, internally nnlinear behavir. Example uses f these systems are available, such as the MOSFET-C filter, which uses the MOS transistr as a linear resistr. 8,9 By emplying the same nnlinear vltagecurrent characteristic f the MOS transistr, ther researchers have devised a linear current divisin technique. 10 Tsividis presents a revisin f nnlinear techniques applied t linear circuit design. 11 Every nnlinear-behavir cmpensatin scheme has a certain cst, which can cme in the frm f area, speed, r design time (because a cmplex circuit requires mre design time). Externally linear, internally nnlinear analg circuits, althugh still nt as characterized as linear nes, d have sme advantages. Yu can January February

5 Field-Prgrammable Mixed Systems Z 1 0 X 2 X 3 X 4 1 α α X 2 X 3 X 4 β 0 Γ 0 Κ 0 β 1 Γ 1 Κ 1 Z 1 shw a crss prduct between the input and the utput: v 1 = vi CK2viv RC dt + ( ) Adder (+) Figure 3. Adaptive nnlinear filter. Input pin Output pin + + develp the circuits in less area, because the MOS gate capacitr is well cntrlled and has a high capacitance per area; use MOS channels as resistrs; and use switched-capacitr circuits that depend n nnlinear capacitances. As an example, cnsider a simple integratr implemented using nnlinear devices. Imagine a nnlinear capacitr, which has a capacitance that varies linearly with the vltage acrss it: C = f(v C ) = C 0 + K 1 v C. In this case, assuming that the p amp gain is large enugh t put the negative input at r near virtual grund, capacitance C is a functin f the utput signal. Cnsidering a linear resistr, slving the differential equatin yields the fllwing equatin, in which the utput has a term dependent n the square f the utput. v v RK v 2 1 = i dt + RC 1 2 Adder (+) Analg blck Analg nnlinear input blck Amplifier Analg utput Linear D/A cnverter Antialias Σ mdulatr Digital blck Adaptive filter Reference Figure 4. Circuit t train the filter and fr peratin in steady state. Alternatively, yu can cnsider the resistr as R = g(v R ) = R 0 + K 2 v R, and a linear capacitr, and the result will + When bth cmpnents are nnlinear, the utput will have cnsiderable harmnic distrtin, even fr such simple nnlinear characteristics. Althugh the preceding analysis assumes imaginary cmpnents (MOS transistrs have mre cmplex resistance-vltage and capacitance-vltage curves), the verall effect f nnlinearity is t generate harmnics at the utput. In additin t these harmnics, ther prblems arise frm the effect f limited p amp gain and bandwidth, and the static characteristics such as ffset. Digital cmpensatin s gal is t restre the frequency behavir f the utput signal withut harmnic distrtin. Nnlinear cmpensatin: Use f adaptive digital filters In this wrk, we use the nnlinear adaptive filter shwn in Figure 3 t perfrm digital cmpensatin. Adaptive filters are generally designed t wrk with linear systems. Mst practical applicatins, hwever, include sme nnlinear behavir. Sme designers chse t ignre the nnlinearity r t limit the signal s dynamic range s that the nnlinear behavir is nt meaningful. Here, we have used a nnlinear, adaptive least-meansquare filter, mdified frm an example by Widrw and Walach. 12 Figure 3 shws the mdified filter. The main mdificatin cncerns the filter tplgy, where the nnlinear behavir cmes frm the expnential peratins applied t input signal x in each filter tap. An imprtant pint regarding adaptive filters is their need fr training befre peratinal deplyment. Figure 4 shws the verall structures necessary t supprt the training phase f digital adaptive filters. After establishing all the cnnectins in the analg blck, designers use white nise t excite the input f each analg prcessing path. They then cmpare the resulting acquired data with the expected signal, derived frm the internal reference prgrammed with the behavir f the implemented analg functin. The resulting errr signal becmes the basis fr adjusting the filter cefficients. 80 IEEE Design & Test f Cmputers

6 The implementatin must have a D/A cnverter t excite the filter and the analg circuit (which needs a knwn excitatin in the training phase). This cnverter must als have enugh passband t guarantee that it excites the filter circuit with all frequencies f interest. The requirement fr a D/A cnverter is usually nt a prblem because mixed-signal prgrammable systems typically include ne. The training signal must be rich in frequencies t excite all the circuit ples and zers that require cmpensatin. In peratinal mde, all the necessary characteristics have been trained int the filter, which cmpensates fr the nnlinear behavir develped within the circuit s nnlinear devices. The circuit desn t need the feedback frm the errr signal anymre; it als n lnger needs the D/A cnverter fr cmpensatin (thugh it might perfrm ther functins in a mixed-signal system). Practical results We assembled a strngly nnlinear circuit and devices fr its cmpensatin frm discrete cmpnents. Using this prttype, we measured real-time data using a digital filter implemented as a sftware rutine running n a DSP. Figure 5 shws this nnlinear circuit; because f the dide, this circuit demnstrates a strng nnlinearity, which ranges frm the secnd- t higherrder harmnics, as Figure 6a shws. The system perfrms training and peratin t a single sine wavefrm, such as when yu shuld excite and mnitr the utput f a strain gauge, fr example. Figure 6 shws the fast Furier transfrm (FFT) f the utput signal and the signal after linearizatin. As yu can see in Figure 6b, the nnlinear filter cancels ut all harmnics inserted by the nnlinear amplifier. We implemented 75% f the adaptive filter in an Altera 10K10 FPGA (8 equivalent bits, running at 8 khz). We chse these cmpnents because f the available memries t stre filter data and cefficients. We develped anther versin fr audi passband with 48 wrds f cde fr a DSP running at 40 MHz. It is interesting t ntice the very small number f nnlinear cefficients: They are nly ne-third the number f the linear nes. January February 2003 V i Practical results with nnlinearity in the signal s passband An imprtant questin cncerns the cmpensatin fr nnlinearities whenever the harmnic cmpnents fall inside the design s band f interest. S we assembled a new set f experiments t shw ur cmpensatin methd s rbustness. We mdified the circuit in Figure 5 t change its ple t apprximately 100 Hz. A 33-Hz sine wave served as the input signal t the system. T evaluate the distrtin intrduced by the circuit, we cmputed the ttal harmnic distrtin (THD) using 2 ΣA THD = h A f D R R Figure 5. Nnlinear integratr used fr validatin. In this implementatin, R = 10.2 kω (± 1%), and C = 680 nf (± 10%). It used a 1N4148 dide and LM741CN p amp with a ± 15-V supply. where A f is the amplitude f the fundamental frequency and A h is the amplitude f the harmnics. We btained the signal cmpnents using an FFT f length 1,024 pints. We nrmalized the fundamental frequency t 0 db; the detectin threshld was 80 db. Our analysis cnsidered frequencies up t 2 khz and used an integratr develped with linear cmpnents as a reference circuit. Measured THD fr the linear reference circuit was 0.02%. Table 1 shws the signal s cmpnents after the signal passes thrugh the nnlinear integratr. The resulting THD is 12.72% within the band f interest (dc t 100 Hz) and 12.83% within the band frm dc t 2 khz. Table 1. Signal cmpnents after Table 2 presents the measured values after nnlin- nnlinear circuit (abve 80 db). ear digital cmpensatin fr each specific harmnic cmpnent. In this situatin, THD is 0.37% frm dc t 100 Hz, and 0.39% frm dc t 2 khz. This is still 10 times wrse when cmpared t the linear signal. Hwever, the THD f the digital signal used as the reference during train- Frequency (Hz) Amplitude (db) C V 81

7 Field-Prgrammable Mixed Systems Fast Furier transfrm (db) (a) Fast Furier transfrm (db) (b) acquisitins ,000 1,125 1,250 Nnlinear utput signal (Hz) acquisitins ,000 1,125 1,250 Output f cmpensated signal (Hz) Figure 6. FFT f the nnlinear utput (a) and the signal after cmpensatin (b). Ntice that cmpensatin cancels ut the secnd and third harmnics. ing was 0.15% within the Table 2. Signal cmpnents f passband, and 0.15% within the full range (frm dc cmpensated circuit (abve 80 db). Frequency (Hz) Amplitude (db) t 2 khz). This means that the cmpensatin methd wrked almst as well as the reference signal. A better reference signal culd lead t an even lwer THD. Fr all these tests, we used a nnlinear filter with 100 linear taps, and 20 secnd- and 20 third-rder taps. We develped the prgram in a DSP; it takes nly 928 prgram wrds, including thse fr cmmunicatin with a PC, start-up, and s n. The actual cmpensatin takes 298 instructins per sample, and using an 8-kHz sampler, requires a ttal f 8, = MIPS. The ADSP2181 prcessr has 29 MIPS available. Training takes nly a few secnds. Area results T evaluate the area that nnlinear devices cnsume, we develped analg cmpnents using a 0.8-micrn CMOS technlgy. Table 3 shws these area results. As yu can see, fr a purely digital technlgy, the area f the nnlinear devices is much smaller than that f the linear devices. In mre advanced fabricatin prcesses, yu can achieve a sevenfld gain by using a gate-t-channel capacitance rather than a ply1-ply2 capacitance, in a 0.25-micrn prcess. 9 Als, a capacitr frmed by a sandwich f metal and ply layers is 35 times larger than the gate-tchannel equivalent capacitr frmed by a sandwich f five metal layers alne. ALTHOUGH WE HAVE NOT YET prttyped a cmplete system-level device, this wrk demnstrates prmising results. The cmpensated test cases can cnfigure the set amplifier and filter, and becme part f a mixed-signal applicatin, such as data acquisitin frm a sensr system. The need fr a digital filter might seem t be a prblem, but yu can easily develp the filter as a specific sftware blck inside a micrprcessr. Alternatively, yu can frm the filter as an array f cells in the digital part f an FPGA itself, as we have shwn here. Anther issue is the area ccupied by the digital adaptive filter. Designers must develp the area tradeff at system level. This way, althugh including a signal prcessr increases the area, the use f nnlinear 82 IEEE Design & Test f Cmputers

8 cmpnents reduces the analg part. A simple, nnlinear capacitr is at least Table 3. Capacitr area cmparisn (area in square micrns). ne rder f magnitude smaller than its linear equivalent. Mrever, frm the pint f view f an FPMS, a prcessr is readily available, and the main tradeff invlves speed versus accuracy. The use f nnlinear adaptive filters is Capacitr value (ff) 500 1,000 Linear ply1-ply ,162 Linear metal1-metal2 13,605 27,603 Linear metal1-ply 9,067 18,347 Nnlinear limited in the sense that, during pwer up, a training phase must exist. The training phase must use white nise t excite the user-specified analg circuit and the cmpensating filter. Althugh easy t achieve, this excitatin requires a D/A cnverter, s the architecture f the mixed-signal prgrammable system must include ne f these devices. Als, because the cmpensatin methdlgy requires a digital filter, the speed f the set analg-cnverter cmpensating filter limits the whle system s frequency respnse. Our future wrk invlves a cncrete evaluatin f the area-perfrmance tradeff fr a mixed-signal prgrammable system as prpsed here. We als plan t cmplete the layut f the field-prgrammable analg part. Mrever, we must als study a specific test methdlgy, because having analg and digital parts n the same 8. J.C.M. Bermudez, M.C. Schneider, and C.G. Mntr, Linearity f Switched Capacitr Filters Emplying Nnlinear Capacitrs, IEEE Int l Symp. Circuits and Systems, IEEE Press, Piscataway, N.J., 1992, pp H. Yshizawa et al., MOSFET-Only Switched-Capacitr Circuits in Digital CMOS Technlgy, IEEE J. Slid- State Circuits, vl. 34, n. 6, June 1999, pp K. Bult and G.J.G.M. Geelen, An Inherently Linear and Cmpact MOST-Only Current Divisin Technique, IEEE J. Slid-State Circuits, vl. 27, n. 12, Dec. 1992, pp Y. Tsividis, Externally Linear, Time-Invariant Systems and Their Applicatin t Cmpanding Signal Prcessrs, IEEE Trans. Circuits and Systems, II: Analg and Digital Signal Prcessing. vl. 44, n. 2, Feb. 1997, pp chip will impse new challenges in this field. 12. B. Widrw and E. Walach, Adaptive Inverse Cntrl, Prentice Hall, Upper Saddle River, N.J., 1996, p References 1. G. De Micheli and R.K. Gupta, Hardware/Sftware C- Design, Prc. IEEE, vl. 85, n. 3, Mar. 1997, pp J.K. Adams and D.E. Thmas, The Design f Mixed Hardware/Sftware Systems, Design Autmatin Cnf. (DAC 96), ACM Press, New Yrk, 1996, pp E.K.F. Lee and W.L. Hui, A Nvel Switched-Capacitr- Based Field-Prgrammable Analg Array Architecture, J. Analg Integrated Circuits and Signal Prcessing, vl. 17, n. 1/2, Sept. 1998, pp H. Kutuk and S. Kang, A Switched Capacitr Apprach t Field-Prgrammable Analg Array (FPAA) Design, J. Analg Integrated Circuits and Signal Prcessing, vl. 17, n. 1/2, Sept. 1998, pp A. Bratt and I. Macbeth, DPAD2 A Field Prgrammable Analg Array, J. Analg Integrated Circuits and Signal Prcessing, vl. 17, n. 1/2, Sept. 1998, pp S. Pavan, Y.P. Tsividis, and K. Nagaraj, Widely Prgrammable High-Frequency Cntinuus-Time Filters in Digital CMOS Technlgy, IEEE J. Slid-State Circuits, vl. 35, n. 4, Apr. 2000, pp Y. Tsividis, M. Banu, and J. Khury, Cntinuus-Time MOSFET-C Filters in VLSI, IEEE J. Slid-State Circuits, vl. 21, n. 1, Feb. 1986, pp Luigi Carr is a prfessr in the Electrical Engineering Department f Universidade Federal d Ri Grande d Sul (UFRGS), Prt Alegre, Brazil, and a lecturer in the Cmputer Science Department at UFRGS. His research interests include mixed-signal design, digital signal prcessing, and rapid system prttyping. Carr has a BS in electrical engineering and a PhD in cmputer science frm UFRGS. He is a member f the IEEE and the Brazilian Cmputing Sciety. Marcel Negreirs is an assciate researcher in the Signal Prcessing Labratry f the Electrical Engineering Department at UFRGS, where he is als wrking tward a PhD in cmputer science. His research interests include digital signal prcessing and adaptive systems. Negreirs has a BS in electrical engineering and an MS in engineering frm UFRGS. January February

9 Field-Prgrammable Mixed Systems Gabriel Parmegiani Jahn is a telecmmunicatins engineer at Telefnica Celular RS in the area f cell planning. His research interests include digital signal prcessing, pwer measurement and quality analysis, and telecmmunicatins, particularly cell planning and data transmissin. Jahn has a BS in electrical engineering frm UFRGS. Adã Antôni de Suza Jr. is an assciate researcher in the Hardware Prttyping and Testing Labratry at UFRGS, where he is als wrking tward a PhD in cmputer science. His research interests include evlutive hardware, hardware implementatin f adaptive systems, and field-prgrammable mixed-signal arrays. Suza has a BS in electrical engineering and an MSc in engineering frm UFRGS. Denis Teixeira Franc is a lecturer in the Physics Department f Fundaçã Universidade Federal d Ri Grande (FURG), Brazil. He participated in this research as a student at UFRGS. His research interests include cmputer architecture, digital systems design, and cnfigurable cmputing technlgy. Franc has a BS in electrical engineering frm the Cathlic University f Peltas, and an MSc in cmputer science frm UFRGS. Direct questins and cmments abut this article t Luigi Carr, Departament de Engenharia Elétrica, Universidade Federal d Ri Grande d Sul, Av. Osvald Aranha 103, Prt Alegre RGS, Brasil, CEP ; carr@eletr.ufrgs.br. Fr further infrmatin n this r any ther cmputing tpic, visit ur Digital Library at publicatins/dlib. Get access t individual IEEE Cmputer Sciety dcuments nline. Mre than 57,000 articles and cnference papers available! US$5 per article fr members US$10 fr nnmembers 84 IEEE Design & Test f Cmputers