PGB2 Series Halogen Free / Lead-Free

Transcription

1 Halogen Free / Lead-Free Description PulseGuard ESD Suppressors help protect sensitive electronic equipment against electrostatic discharge (ESD). They use polymer composite materials to suppress fastrising ESD transients (as specified in IEC 61-4-), while adding virtually no capacitance to the circuit. They supplement the on-chip protection of integrated circuitry and are best suited for low-voltage, high-speed applications where low capacitance is important to ensure minimal interference of data signal integrity. Equivalent Circuits The new and ultra-small surface mount PGB 4 series offers a RoHS Compliant, Halogen Free, and 1% Lead Free circuit protection alternative. 1 Features Product Characteristics Part Number Lines Protected Component Package PGB14KRHF 1 4 Applications Computer Electrical Characteristics Specification PGB14 Notes ESD Capability: IEC Direct Discharge Measured per IEC Discharge Method Capacitance (typical).7 pf, typical Measured at 5 MHz Response Time <1nS Measured per IEC pulses min Some shifting in characteristics may occur when tested over multiple pulses at a very rapid rate 1

2 Typical ESD Response Curve Dimensions Dimensions: mm (inch) /-.5 (.39" +/-.") Voltage (V) Time (ns) Typical TLP Response Curve.51 +/-.5 (." +/-.").3 Nom. (.9").3 +/-.1 (.9" +/-.4") 1.55 (.61").18 +/-.1 (.7" +/-.4").559 (.") Recommended for reflow soldering only.381 (.15").584 (.3") Recommended Pad Layout.3 +/-.8 (.1" +/-.3") Voltage (V) 15 1 Part Numbering System PGB 1 4 KR HF Time (ns) LEAD-FREE HALOGEN-FREE PULSEGUARD ESD SUPPRESSORS LINES PROTECTED: 1 = 1 line HALOGEN FREE QUANTITY & PACKAGING CODE: KR = 1, pieces DEVICE SIZE CODE: 4 = 4 (15) Typical Insertion Loss Typical Device Capacitance.1 Insertion Loss (db) Capacitance (pf) Frequency (MHz) Frequency (MHz)

3 Physical Specifications Environmental Specifications Materials Operating Temperature -65 C to +15 C Device Weight.349 mg Biased Humity: Biased Heat: 4 C, 95% RH, 1 hours 85 C, 1 hours Solderability MIL-STD-, Method 8 Soldering Parameters Thermal Shock Vibration MIL-STD-, Method 17G, -65 C to 15 C, 3 min. cycle, 1 cycles Design Consideration Chemical Resistance MIL-STD-, Method 15 Because of the fast rise-time of the ESD transient, proper consideration to achieving optimal ESD suppression. The devices should be placed on the circuit board as close to the source of the ESD transient as possible. Install PulseGuard directly behind the connector so that they are the first boardlevel circuit component encountered by the ESD transient. Solder Leach Resistance and Terminal Adhesion Soldering Parameters Reflow Condition Pb Free assembly - Temperature Min (T s(min) ) 15 C Pre Heat - Temperature Max (T s(max) ) C - Time (min to max) (t s ) 6 18 seconds Average ramp up rate (Liquidus Temp (T L ) to peak T S(max) to T L - Ramp-up Rate Reflow - Temperature (T L ) (Liquidus) 17 C - Temperature (t L ) 6 15 seconds Peak Temperature (T P ) 6 C Time within 5 C of actual peak Temperature (t p ) 1 3 seconds Ramp-down Rate Time 5 C to peak Temperature (T P ) Notes: - recommended for reflow soldering only - For recommended soldering pad layout dimensions, please refer to Dimensions section of this data sheet 3

4 Packaging Part Number Quantity & Packaging Code Quantity Packaging Option Packaging Specification PGB14 KR 1 Tape & Reel (7 reel) Tape and Reel Specifications T t D d D s Description 4 Series (mm) C t.53 T w D d - Drive hole diameter 1.55 P d P h D s - Drive hole spacing 4. P d.41 C t P s P w P h 1.1 Carrier Tape: 8mm, paper Reel: 7 (178mm) P s. P w.6 T t.61 T w - Carrier tape width 8. Typical ESD Pulse Test Setup FARADAY CAGE COMPUTER AGILENT INFINIIUM 1.5 GHz 8 GS/s 3dB PASTERNAK ATTENUATOR PE75-3 TEKTRONIX LOW CAP PROBE 6158 (x TIP) QUADTECH 1865 RESISTANCE METER RESISTANCE TEST FIXTURE ESD TEST FIXTURE TEST BOARD W/ DUT ESD PULSE GENERATOR Notes: - QuadQuadTech 1865 High Resistance Meter: Measures insulation resistance values - Faraday cage: Shields the acquisition equipment from the electromagnetic fields generated by the simulator 4

5 Characterization Methods for ESD Suppressors Two of the most common methods used in industry for characterizing the performance of ESD suppressors are ESD transient testing, per IEC ESD waveform, qualification of ESD suppressor performance, these two methods have become the de-facto standard for determining device trigger and clamp specifications. It is common to see trigger values to be based on the TLP method and clamping values based on the ESD transient method. Low voltage TLP obtained trigger values most closely resemble device DC turn-on.since the two test correlate suppressor response between the two test methods, trigger and clamp values should be specified for each method. ESD transient testing, which is based on the IEC standard waveform, consists of subjecting a ESD suppressor to an subnanosecond risetime 8Kv transient generated by a commercial ESD simulator and recording trigger and clamp voltage levels. Clamp voltage level is obtained at 5ns. The basic ESD simulator circuit consists 4 GHz oscilloscope(5 ohm input) with X resistive divider probes and a 3dB attenuator. Figures 1 and show IEC current waveform and test setup. TLP testing consists of subjecting a ESD suppressor to a 5 ohm transmission line discharge pulse with a subnanosecond risetime and a pulse width of 65ns. Trigger values are obtained by varying the TLP voltage until a are captured using a 4 GHz oscilloscope(5 ohm input) with X resistive divider probes and a 3dB attenuator. Figures 3 and 4 show a typical TLP voltage waveform and test setup. for obtaining trigger and clamp voltage levels. Trigger and clamp values will vary from one test setup to another. Due to the subnanosecond risetime of ESD and TLP waveforms, any parasitic inductance and capacitance in due to inductance and capacitance need to be subtracted from the final measurement. It is important to remember that the test system will introduce a load across the ESD suppressor under test and this will also affect and probes(>1ghz) need to be used for obtaining best at least X in order to obtain high input impedance for measurements. Figure 1 Volts Current (I) % % 9% I 3 I 6 1% tr =.7 to 1.ns 3n pf DUT - 6n Figure ESD Simulator Scope Probe 3db Attenuator 5 Ohm Scope Input 1 Figure 3 Figure Time in nanoseconds TLP Scope Probe 3db Attenuator 5 Ohm Scope Input DUT