CD22202, CD V Low Power DTMF Receiver

Transcription

1 November 00 OBSOLETE PRODUCT NO RECOMMDED REPLACEMT contact our Technical Support Center at 1--TERSIL or CD0, CD0 5V Low Power DTMF Receiver Features Central Office Quality No Front End Band Splitting Filters Required Single, Low Tolerance, 5V Supply Detects Either or 1 Standard DTMF Digits Uses Inexpensive.57955MHz Crystal for Reference Excellent Speech Immunity Output in Either -Bit Hexadecimal Code or Binary Coded -of- Synchronous or Handshake Interface Three-State Outputs Excellent Latch-Up Immunity Part Number Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD0E 0 to 70 1 Ld PDIP E1. CD0E 0 to 70 1 Ld PDIP E1. Description The CD0 and CD0 complete dual-tone multiple frequency (DTMF) receivers detect a selectable group of or 1 standard digits. No front-end pre-filtering is needed. The only externally required components are an inexpensive.57955mhz TV colorburst crystal (for frequency reference) and a bias resistor. Extremely high system density is possible through the use of the clock output of a crystal connected CD0/CD0 receiver to drive the time bases of additional receivers. This is a monolithic integrated circuit fabricated with low-power, complementary symmetry CMOS processing. It only requires a single low tolerance power supply. The CD0 and CD0 employ state-of-the-art circuit technology to combine the digital and analog functions on the same CMOS chip using a standard digital semiconductor process. The analog input is preprocessed by 0Hz reject and band splitting filters and then hard limited to provide AGC. Eight Bandpass filters detect the individual tones. The digital post processor times the tone durations and provides the correctly coded digital outputs. Outputs interface directly to standard CMOS circuitry and are three-state enabled to facilitate bus oriented architectures. Pinout Functional Diagram D1 HEX/B 1 ED (0 ONLY), NC (0) CD0, CD0 (PDIP) TOP VIEW 1 1 D D D CLR ATB ATB PREPROCESSOR/ BANDSPLIT FILTER CLOCK GERATOR LOW B/P HIGH B/P CHIP CLOCKS VOLTAGE REG./REF. DETECTORS AND SIGNAL- PROCESSG CIRCUITS I ED-0 NC-0 CLR HEX/B D1 D D D CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1--TERSIL or Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00. All Rights Reserved 1 FN195.

2 Absolute Maximum Ratings DC Supply Voltage ( )(Referenced to Terminal) V Power Dissipation T A = 5 o C (Derate above T A = 5 o C at.5mw/ o C mW Input Voltage Range All Inputs Except Analog In ( +0.5V) to -0.5V Analog in Voltage Range ( +0.5V) to ( -10V) DC Current into any Input or Output ±0mA NOTE: Unused inputs must be connected to or as appropriate. CD0, CD0 Thermal Information Maximum Junction Temperature o C Maximum Junction Temperature (Plastic) o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 10s) o C Operating Conditions Temperature Range o C to 70 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications 0 o C T A +70 o C, = 5V ±10% PARAMETER TEST CONDITIONS M TYP MAX UNITS Frequency Detect Bandwidth ±(1.5 + Hz) ±. ±.5 % of f O Amplitude for Detection Each Tone dbm Referenced to 00Ω Minimum Acceptable Twist High Tone db Twist = Low Tone 0Hz Tolerance V RMS Dial Tone Tolerance Precise Dial Tone db Referenced to Lower Amplitude Tone Talk Off MITEL Tape #CM Hits Digital Outputs (except ) 0 Level, 00µA Load V 1 Level, 00µA Load V Digital Inputs 0 Level 0-0. V 1 Level V Supply Current T A = +5 o C ma Noise Tolerance MITEL Tape #CM791 (Note 1) db Referenced to Lowest Amplitude Tone Input Impedance V ( -10) 100kΩ//pF 00kΩ - NOTE: 1. Bandwidth limited (khz) Gaussian noise.

3 CD0, CD0 Functional Block Diagram BANDPASS CD0 CD0 PREPROCESSOR BAND SPLIT 0Hz 9 PRE EMP BS1 REJECT ZERO CROSSG DETECTORS AMPLITUDE DETECTORS EARLY DETECT BS TIMG CIRCUITRY CLR ATB 1 CLOCK GERATOR CHIP CLOCKS STROBE DATA STROBE F.F CLR 1 H/B 1 D1 1MΩ POWER REGULATOR VOLTAGE REF DECODER REGISTER 1 D 17 D 1 D DATA CLEAR NOTE: Pin : Early detect output on CD0 only. System Functions Analog In The Analog In pin accepts the analog input. It is internally biased so that the input signal may be either AC or DC coupled, as long as it does not exceed the positive supply voltage. Proper input coupling is illustrated below. AUDIO PUT (+dbm MAXIMUM) 00pF 0.01µF kω 70kΩ OPTIONAL HIGH FREQUCY NOISE FILTER (f C =.9kHz) 9 CD0, CD0 (ON CHIP) 10pF >100kΩ FIGURE 1. The CD0 and CD0 are designed to accept sinusoidal input waveforms, but will operate satisfactorily with any input that has the correct fundamental frequency with harmonics that are at least 0dB below the fundamental. Crystal Oscillator The CD0 and CD0 contain an on-board inverter with sufficient gain to provide oscillation when connected to a low cost television color-burst (.57955MHz) crystal. The crystal oscillator is enabled by tying high. The crystal is connected between and. A 1MΩ resistor is also connected between these pins in this mode. ATB is a clock frequency output. Other CD0 and CD0 devices may use the same frequency reference by tying their ATB pins to the ATB output of a crystal connected device. and of the auxiliary devices must then be tied high and low, respectively. Up to ten devices may be run from a single crystal connected CD0 and CD0 as shown in Figure.

4 CD0, CD MHz 1M ATB CD0/0 1 sensed and decoded at the output pins D1, D, D, and D. remains high until a valid pause occurs or CLR is raised high, whichever is sooner. This handshake can save microprocessor time. DTMF Dialing Matrix COL 0 09Hz COL 1 1Hz COL 177Hz COL 1Hz CONNECTED TO CD0/0 1 UP TO 10 DEVICES ROW 0 97Hz ROW 1 770Hz ROW 5Hz ROW 91Hz 1 A 5 B 7 9 C * 0 # D HEX/B FIGURE. CRYSTAL OSCILLATOR This pin selects the format of the digital output code. When HEX/B is tied high, the output is hexadecimal. When tied low, the output is binary coded -of-. The following table describes the two output codes. ED This pin, on the CD0 only, indicates the presence of frequencies which are likely to be DTMF digits, but have not yet been verified by a signal. It is comparable to a buttondown output, and it is useful as an EARLY DETECT signal to interrupt a microprocessor for digit storage and validation. and CLR TABLE 1. CODES HEXADECIMAL BARY CODED -OF- DIGIT D D D D1 D D D D * # A B C D signals a detection by going high after a valid tone pair is NOTE: Column is for special applications and is not normally used in telephone dialing. 1 When tied high, this pin inhibits detection of tone pairs containing the 1Hz component. For detection of all 1 standard digits, 1 must be tied low. N/C Pin This pin has no internal connection and should be left floating. Digital Inputs and Outputs All digital inputs and outputs of the DTMF receivers are represented by the schematic below. Only the analog in pin is different, and is described above. Care must be exercised not to exceed the voltage or current ratings on these pins as listed in the maximum ratings section. PUT Input Filter CMOS CIRCUITRY FIGURE. PUTS AND S The CD0 and CD0 will tolerate total input noise of a maximum of db below the lowest amplitude tone. For most telephone applications, the combination of the high frequency attenuation of the telephone line and internal band limiting make special circuitry at the input to these receivers unnecessary. However, noise near the 5kHz internal sampling frequency will be aliased (folded back)

5 CD0, CD0 into the audio spectrum, so if excessive noise is present above khz, the simple RC filter shown below may be used to band limit the incoming signal. The cut off frequency is.9khz. PARAMETER SYMBOL M TYP MAX UNITS Tone Time For Detection t ON ms For Rejection t ON ms NOISY SIGNAL 70kΩ CD0 CD0 Pause Time For Detection t OFF ms 0.00µF kω For Rejection t OFF ms Detect Time t D 5 - ms FIGURE. FILTER FOR USE EXTREME HIGH FREQUCY PUT NOISE VIRONMT Noise will also be reduced by placing a grounded trace around and pins on the circuit board layout when using a crystal. It is important to note that is not intended to drive an additional device. may be driven externally; in this case, leave floating. Timing Waveforms TONE BURST 1 PUT D1, D D, D t D t ON t R t OFF PAUSE TONE BURST t SU t H t CL Release Time t R 5 50 ms Data Setup Time t SU µs Data Hold Time t H. - 5 ms Clear Time t CL ns CLR Pulse Width t PW ns ED Detect Time t ED 7 - ms ED Release Time t ER - 1 ms Output Enable Time C L = 50pF, R L = 1kΩ Output Disable Time C L = 5pF, R L = 500Ω Output Rise Time C L = 50pF Output Fall Time C L = 50pF ns ns ns ns CLR t ED t ER ED (NOTE) NOTE: Early Detect output is available only on the CD0. FIGURE 5. t PW Guard Time Whenever the DTMF receiver is continually monitoring a voice channel containing distorted or musical voices or tones, additional guard time may be added in order to prevent false decoding. This may be done in software by verifying that both ED and are present simultaneously for about 55ms. An appropriate guard time should be selected to balance the fastest expected dialing speed against the rejection of distorted or musical voices or tones (most autodialers operate in the 5ms to 75ms range although a few generate 50ms tones). A hardware guard time circuit is shown in Figure. R and R should keep the voice amplitude as low as practical, while R and R 5 adjust detection speed. 5