TIE Plus. The step towards interconnect simulation technology

Transcription

1 Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 11,0 cm) TIE Plus. The step towards interconnect simulation technology Catalin Negrea, Ph. D. Team Leader - EE Simulation & Controller Platforms Technical Expert - Signal & Power Integrity Continental Automotive, Interior Division 23 April 2015 IID EE CDH

2 Virtual Prototyping Virtual prototyping = the usage of computer based modeling and simulation techniques for the definition of a multidisciplinary model of the device under development (with the goal of predicting physical behavior in different use cases) SPICE-like Circuit Sim. CAD Model Virtual Prototype Thermal Simulation SI \ PI \ EMI Simulation Source: Aberdeen Group Market Study Why PCB Design Matters to the Executive, Feb Ideal world goal Real R&D world goal Get it right the first time! Reduce number of design loops, prototype costs, development time 2

3 TIE Plus Objectives TIE Plus = a new contest challenge under the TIE brand, dedicated to virtual prototyping disciplines that support high-complexity PCB design Objectives: Promoting simulation based PCB design disciplines in universities and R&D centers Stimulating the development of future specialist in the field of interconnect simulation in a accordance to best-in-class companies demands Create a collaborative-competitive environment where the candidates presents their technical solutions, but also exchange ideas on simulation approaches and get in touch other PCB design professionals Subject topics for upcoming editions of TIE plus: Signal Integrity (SI) -> simulations for signal integrity associated with wired data transmissions at PCB and system level Power Integrity (PI) -> simulation power supply distribution networks in high frequency digital applications 3

4 What is high speed? As the variation speed of electric signals increases, physical properties of the interconnect structures can induce unwanted signal distortion Due to the need of high data rates (implying high frequency), the signal s rise&fall times become smaller and smaller (for DDR interfaces tr~0.2-1 ns) The interconnect path can be no longer modeled as an RLC structure, but as a transmission line with a electrical behavior described by the telegraphers equations The following items fall in to the high speed domain and must be considered in the analysis: interconnect reflections losses due to skin effect crosstalk (near end and far end) interconnect timing delays IC package parasitics IC driver\receiver circuit characteristics A signal can have a frequency of just some khz and but still pose a SI risk due to it s variation speed (V/ns) 21 September 2015 Author, Continental AG 4

5 What can be considered an interconnect? Every electrical connection element placed in the signal path is a potential source for signal degradation and its electrical behavior must be characterized in order evaluate the impact on the transmitted signal {- die-to-package connection (wire bond, flip-chip) - package wiring Interconnects - PCB routing - connectors - cables Driver Receiver IC Receiver 21 September 2015 Author, Continental AG 5

6 What is a transmission line? (At least) two parameter determine a transmission line Propagation speed Characteristic impedance Z L A transmission line can be cut in short pieces having the length Δx: Inductance per unit length i(x,t) R Δx L Δx i(x+δx,t) Δx v(x,t) C Δx G Δx v(x+δx,t) Δx Capacitance per unit length Transmission Line RLCG segment 6

7 What is high speed? When do these effects become critical? Rule of thumb (for FR4): l max l max / inch tr Source: Eric Bogatin, Signal and Power Integrity Simplified, Prentice Hall, 2004 so for a 25mm trace length, a signal with a rise time < 1ns (for 3.3V logic this would mean ~2V/ns) creates already a SI risk of signal if the interconnect is not properly designed and properly designed for SI means impedance matching at circuit level / ns ( mm) ~ 25 tr (ns) The term high speed indicates an unhappy combination of interconnect length and variation speed 7

8 Impedance Discontinuities Changes in interconnect impedance over the signal transmission path will cause distortion depending on driver characteristics (every IC I/O has a non-linear impedance curve) and interconnect discontinuity characteristics. Impedance discontinuities have consequences: overshoot \ undershoot reflections in the triggering region false logic triggering interconnect added jitter timing deviations 21 September 2015 Author, Continental AG 8

9 Controlled Impedance Routing Microstrip Stripline 21 September 2015 Author, Continental AG 9

10 But some things can not be avoided. Reality may look something like this Via (bottom to inner layer) Microvia Meander Via (top to bottom layer) 21 September 2015 Author, Continental AG 10

11 .and there are EM interaction as well 21 September 2015 Author, Continental AG 11

12 The need for SI simulations The need to incorporate such specialized electromagnetic simulations in to the PCB design flow is determined by the fact that, at high frequencies associated with digital data transmissions, the interconnect can be no longer considered an ideal electrical connection and the parasitic elements have to be taken in to consideration. Assuring the compliance of signal waveforms to data transmission standards in a non-ideal electromagnetic environment is becoming more of a challenge as data transfer rates and component density continually increase. Signal integrity is becoming a mandatory discipline in the EE design flow even for medium complexity\density projects (4 layers, BGA) 12

13 SI \ PI Workflow Problem evaluate of system\ interface requirements define design targets define modeling approach Formulation layout directives Pre-layout Analysis define PCB stack-up (layers, materials) what-if simulations explore design possibilities in order to meet interface requirements, obtain best performance/cost ratio PCB design optimization fine-tuning troubleshooting Post-layout Analysis PCB stack-up and CAD represent the inputs for the simulation Identify potential problems that were not considered in prelayout debugging of a physical prototype problem; identify root cause and define possible remedies 13

14 Signal integrity simulation model types involved 3D solver imports IBIS Models (Vendor) Transmission Line Models Simple RLC SPICE Models (Vendor) Touchstone (s-param files) 14

15 SI & PI Simulation Tools Designer SI, HFSS, SIWave 15

16 High Speed Design makes the difference.and after optimization Address line waveforms for a DDR3 multi-drop system before optimization 16

17 Power Integrity Power integrity (PI) is a topic that is related to the voltage variation in the power distribution network (PDN). It is a relatively new topic as compared to electromagnetic compatibility (EMC) and signal integrity (SI). However, they cannot be separated as the identification and solving of these problems are still based on Maxwell s EM theory. Power Integrity Concept Problems Micro-controller DDR Memories DDR Memories DDR Memories DDR Memories DDR Memories DDR Memories DC DDR Memories DDR Memories Add parasitic elements AC Micro-controller 21 September 2015 Author, Continental AG 17

18 Impedance (Ω) Power Integrity In a power distribution network, there are many peripherals that can affect its performance. It is important to note that the effectiveness of each component is frequency limited. PCB High Frequency Capacitors Electrolytic Capacitors Power Supply 1 KHz 1 MHz 100 MHz GHz Frequency 18

19 TIE Plus workflow ation of the subject on TIE website Online contestant registration Solving the subject Assessment of the solutions ation of subject The subject content will published on the TIE website in a separate form TIE Plus. Also contest topics, recommended bibliography and contest regulations will be available. At this stage only the subject text and block diagrams will be public. The simulation models, datasheets and other details will be available for download only after the contestant is registered. Contestant registration The registration will be done using an on-line application form. The provided information will be analyzed by the technical committee and a notification will be sent to the applicant (accepted \ rejected as a contestant for TIE Plus). After acceptance the contestant will receive user login information on the TIE plus platform. Based on this he will be able to download all necessary files associated with the subject. Solving the subject Solving the subjects will be done own (or university/company based) technical means (hardware and software). The technical solution will be posed as R&D report document that shall be uploaded on the web platform. Assessment of the solutions The contestants are required to prepare a short presentation (10-15 min.) that will be exposed to the technical committee during an evaluation meeting. The presentation content must be in full agreement with the uploaded R&D report. 19

20 TIE Plus topics Transmission line theory. Line impedance. Propagation delay. Reflections Single ended and differential data transmissions Terminations Eye diagrams Routing topologies Crosstalk Coupling mechanisms Near-End and Far-End crosstalk Crosstalk induced ISI IC modeling for SI simulations IBIS Modeling I\O buffer impedance analysis Package parasitics modeling Passive components & interconnect modeling S-parameters Touchstone modeling Capacitor model Via hole modeling 2D\3D Field solver extraction PCB Stack-up definition Timing analysis Interface budget planning Interconnect propagation delays Jitter characterization Signal Integrity simulation Power Integrity simulation 20

21 TIE Plus recommended bibliography Signal Integrity Issues and Printed Circuit Board Design, Douglas Brooks, Prentice Hall PTR High-Speed Digital Design A handbook of Black Magic, H. W. Johnson, Prentice Hall PTR High-Speed Circuit Board Signal Integrity, Stephen C. Thierauf, Artech House Advanced Signal Integrity for High-Speed Digital Designs, Stephen Hall, Howard Heck, IEEE-Wiley, Frequency Domain Characterization of Power Distribution Networks, Istvan Novak, Jason R. Miller, Artech House, Boston, Signal Integrity Simplified, Eric Bogatin, Prentice Hall, New Jersey, Signal Integrity Characterization Techniques, Mike Resso, Eric Bogatin, IEC, START HERE! Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Brian Young, Prentice Hall, Timing Analysis and Simulation for Signal Integrity Engineers, Greg Edlund, Prentice Hall,

22 TIE Plus evaluation criteria Modeling approach (using the right field solver for a specific problem) Modeling fidelity (how close does the simulation model gets to the physical system) Exposure of numerical results (e.g. variation timing parameters vs. trace length ) Correctness of simulation problem formulation (transposing interface requirements and datasheet information in to a simulatable system ) Formulation and argumentation of layout directives (clarity of directives; applicability in to a real design) Applicability of the provided solution to a PCB (complies with generic IPC and is implementable using conventional fabrication processes) 22

23 A SIMPLE REAL WORLD EXAMPLE - Parallel Flash Memory Interface Analysis - 23

24 System Overview Controll lines Series R Controll lines IO Lines Series R IO Lines ucontroller R/B Pull up R + Series R NAND Flash ucontroller IBIS: ucx21_pl_modified.ibs Output driver models used: model-613_yo model-615_yo Parallel memory interface Fdata_lines = 25MHz Tdata_lines = 40 ns Rise/ fall time = ~ ns Micron Flash Memory : IBIS: m60a_at.ibs I/O driver models used: DQ_FULL_33 Datasheet: m60a_4gb_8gb_16gb_ecc_nand.pdf Requirements: 1. Indentify network resistor values to meet the timing (high time time above 1 ) and level requirements (undershoots and overshoots) during read operation 24

25 PCB Design IC3300 NAND Stack-up IC508 ucontroller 25

26 ucontroller Input Requirements V IH = 0.8Vcc = 2.4 / 2.64 / 2.88 V (slow\typ\fast) V IL = 0.2Vcc = 0.6 / 0.66 / 0.72 V (slow\typ\fast) V in_min =-0.25 V V in_max = 3.75 V T high/low min = 15ns T setup min =10ns T hold min =5ns 26

27 2D sectional extraction Layout Sectional meshing in field solver 1699 sections up to 1GHz 27

28 Simulation Topology I/O lines Resistor Networks NAND Layout extraction -touchstone file *.s32p ucontroller 28

29 Results: I/O Lines Read R0Ω, DIE FAST TYP SLOW Over and Under shoot values exceed maximum specification 29

30 Resistor values sweep in FAST case / Rising edge 3.75 V 0 R 47 R 22 R 68 R 100R 30

31 Resistor values sweep in FAST case / Falling edge 100 R 68R 47 R 22 R V 0 R 31

32 Timing verification in SLOW case 47 R 68 R 100R 100R => 14.6ns 68R => 15.8ns 47R => 16.8ns Choose the slowest signal that meets requirements 32

33 Results: I/O Lines Read R68Ω, DIE FAST TYP SLOW 33

34 Thank you for your attention.