A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL
|
|
- Leslie Green
- 5 years ago
- Views:
Transcription
1 A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL Chung-Lun Hsu and Drew A. Hall University of California, San Diego, La Jolla, CA, USA International Solid-State Circuits Conference 1of 41
2 Motivation: Current Input Biosensors Patch Clamp Electrochemical Nanotube Nanopore International Solid-State Circuits Conference 2of 41
3 Motivation: Current Input Biosensors Patch Clamp Electrochemical Nanotube Nanopore Large signal range I s = 1 pa 1 µa Small signal with large offset ΔI s = 1 pa 1 na with I s = 1 na 1 µa A front-end with >120dB DR and >60dB linearity is required. International Solid-State Circuits Conference 3of 41
4 Conventional Current-Input AFE R-TIA C-TIA Х High noise: = 4 / Х Low DR:, = / О Low noise Х Periodic reset Х Low DR:, = / DR is limited by circuit noise and supply voltage. International Solid-State Circuits Conference 4of 41
5 Current-Input AFE Using C-TIA C-TIA with DC servo loop [JSSC, 2009] Σ w/ pulse modulation [TBioCAS, 2007] О Low noise О Continuous-time Improved DR О Low noise О High DR О Inherent digitization Good linearity with slow f s Challenge: Achieving >120dB DR and >60dB linearity International Solid-State Circuits Conference 5of 41
6 System Overview Input Current <1pA to 10µA Hourglass ADC Predictive DAC International Solid-State Circuits Conference 6of 41
7 C-TIA with Improved DR Conventional C-TIA C F saturates when i sig > limited DR International Solid-State Circuits Conference 7of 41
8 C-TIA with Improved DR Conventional C-TIA C-TIA w/ Hourglass Switch C F saturates when i sig > limited DR Keep amplifying w/o saturation increased DR International Solid-State Circuits Conference 8of 41
9 C-TIA with Hourglass Switch Goal: Increase DR, keep amplifying w/o saturation International Solid-State Circuits Conference 9of 41
10 C-TIA with Hourglass Switch Goal: Increase DR, keep amplifying w/o saturation Method: Flipping the input polarity asynchronously International Solid-State Circuits Conference 10 of 41
11 C-TIA with Hourglass Switch Two continuous-time comparators controls the hourglass switch small i sig large i sig C-TIA: low input-referred current noise Asynchronous Hourglass switching: i sig >> / The DR of a C-TIA is improved with an asynchronous Hourglass switch. International Solid-State Circuits Conference 11 of 41
12 Hourglass ADC The comparators work as a 1-bit quantizer small i sig large i sig, + International Solid-State Circuits Conference 12 of 41
13 Hourglass ADC The comparators work as a 1-bit quantizer small i =0 large i =1, + Analog Input Digital Output Quantization Error [ V R, +V R ] w.r.t. φ dir International Solid-State Circuits Conference 13 of 41
14 Hourglass ADC The comparators work as a 1-bit quantizer small i =0 large i =1, + Analog Input Digital Output Quantization Error Question: How to improve the resolution? Save e q for extending counting? International Solid-State Circuits Conference 14 of 41
15 Hourglass ADC with Noise-Shaping Eliminate the need for periodic reset International Solid-State Circuits Conference 15 of 41
16 Hourglass ADC with Noise-Shaping Digital differentiator: provides 1 st -order noise-shaping At each sampling instance: C F stores quantization error Digital output International Solid-State Circuits Conference 16 of 41
17 Hourglass ADC with Noise-Shaping Equivalent to a CCO-based (Current-Controlled Oscillator) ADC The Hourglass ADC is an asynchronous 1 st -order Σ with improved resolution. International Solid-State Circuits Conference 17 of 41
18 Ideal I sig -to-f φ,dir behavior Linearity in Hourglass ADC,, = 4 International Solid-State Circuits Conference 18 of 41
19 Ideal I sig -to-f φ,dir behavior Linearity in Hourglass ADC,, = 4 I-to-F conversion compressed with a non-ideal OPAMP,,,, The linearity of the I-to-F conversion in an Hourglass ADC is well-defined. International Solid-State Circuits Conference 19 of 41
20 Linearity Calibration in Hourglass ADC BW vs. Linearity 3.2 f 4bit 52 f 8bit International Solid-State Circuits Conference 20 of 41
21 Linearity Calibration in Hourglass ADC BW vs. Linearity This design: 3.2 f dir,max w/ linear 16x power reduction compared to the 8-b linearity case 3.2 f 4bit 52 f 8bit Power hungry amplifier Calibration Foreground characterize the I-to-F curve: BW loop and A loop Increase power efficiency using a lower BW OPAMP The foreground calibration improves the Hourglass ADC energy efficiency. International Solid-State Circuits Conference 21 of 41
22 Linearity Calibration in Hourglass ADC Use an I-DAC to measure I-to-F curve and poly-fit the non-linearity 5 th order Binary-Weighted Tri-state DAC C p & noise DEM [TCAS-I, 2008] DAC linearity International Solid-State Circuits Conference 22 of 41
23 Closed-Loop Hourglass ADC The I-DAC subtracts i s by linear extrapolating the input at f OSR i [n-1] + i / t OSR 1 st -order Predictor [DCAS, 2014] International Solid-State Circuits Conference 23 of 41
24 Closed-Loop Hourglass ADC The I-DAC subtracts i s by linear extrapolating the input at f OSR i fine = i s [n] { 2i [n-1] - i [n-2] } < i s,fs /2 9 with OSR > 71 i [n-1] + i / t OSR = 2i [n-1] - i [n-2] 1 st -order Predictor [DCAS, 2014] International Solid-State Circuits Conference 24 of 41
25 Input Current <1pA to 10µA System Overview Hourglass ADC О High DR О Async. quantization О Noise-shaping О High linearity Predictive DAC О Coarse prediction International Solid-State Circuits Conference 25 of 41
26 C-TIA with Hourglass Switch Dual Cascode-Compensated Amplifier [TCAS-I, 2004] Benefit: Increase f p2 by g m R o Reduce C c by 3-4 Improve power efficiency A DC = 99dB f UGB = 26MHz Pwr = 180µW International Solid-State Circuits Conference 26 of 41
27 C-TIA with Hourglass Switch Low-Leakage Switch 0.1 pf Hourglass Switch International Solid-State Circuits Conference 27 of 41
28 Continuous-Time Comparator 1.3 V 0.5 V Switched-capacitor sampling: o Sample at start-up o Store both V R and V os International Solid-State Circuits Conference 28 of 41
29 Continuous-Time Comparator 1.3 V 0.5 V Switched-capacitor sampling: o Sample at start-up o Store both V R and V os Pre-amp + dynamic amp: o Reduce propagation delay International Solid-State Circuits Conference 29 of 41
30 Feedback Loop 9-bit Binary-Weighted I-DAC 1/10 Digital blocks in FPGA [TCAS-I, 2008] [DCAS, 2014] 1/10 o Biasing: g m /I D ~ 4, thermal noise o Large size: matching & flicker noise o Cascoded tail current: R out International Solid-State Circuits Conference 30 of 41
31 Die Photo TSMC 180nm CMOS process Core area ~0.5mm 2 International Solid-State Circuits Conference 31 of 41
32 Hourglass ADC with DAC off Measurement Results The linearity of the Hourglass ADC is improved by >37. International Solid-State Circuits Conference 32 of 41
33 Hourglass ADC with DAC off Measurement Results The input-referred noise in the Hourglass ADC is < 30fA/ Hz. International Solid-State Circuits Conference 33 of 41
34 Hourglass ADC with DAC on Measurement Results Linearity Error < ±7ppm The linearity of the entire current-measurement front-end is < ±7ppm. International Solid-State Circuits Conference 34 of 41
35 Power Breakdown The total power consumption is 295 µw. International Solid-State Circuits Conference 35 of 41
36 Summary & Comparison International Solid-State Circuits Conference 36 of 41
37 Summary & Comparison DR = 160 db International Solid-State Circuits Conference 37 of 41
38 Summary & Comparison Tconv 2.5 faster International Solid-State Circuits Conference 38 of 41
39 Summary & Comparison FOM = 197 db International Solid-State Circuits Conference 39 of 41
40 Summary & Comparison International Solid-State Circuits Conference 40 of 41
41 Conclusions The current measurement front-end enables precise wide dynamic range for bio-sensing applications Key challenges: dynamic range and linearity To address this, we: Designed an Hourglass ADC to increase DR and decrease quantization noise Designed a DAC with a 1 st -order predictor to further increase DR and improve the front-end power efficiency Used DEM and linearity compensation to improve linearity Result: A current measurement front-end with 160dB DR, 7ppm INL, and 197dB FOM International Solid-State Circuits Conference 41 of 41
A Dynamically Reconfigurable ECG Analog Front-End with a 2.5 Data-Dependent Power Reduction
A Dynamically Reconfigurable ECG Analog Front-End with a 2.5 Data-Dependent Power Reduction Somok Mondal 1, Chung-Lun Hsu 1, Roozbeh Jafari 2, Drew Hall 1 1 University of California, San Diego 2 Texas
More informationA Electrochemical CMOS Biosensor Array with In-Pixel Averaging Using Polar Modulation
Session 11 - CMOS Biochips and Bioelectronics A 16 20 Electrochemical CMOS Biosensor Array with In-Pixel Averaging Using Polar Modulation Chung-Lun Hsu *, Alexander Sun *, Yunting Zhao *, Eliah Aronoff-Spencer
More informationA Fast-Readout Mismatch-Insensitive Magnetoresistive Biosensor Front-End Achieving Sub-ppm Sensitivity
A Fast-Readout Mismatch-Insensitive Magnetoresistive Biosensor Front-End Achieving Sub-ppm Sensitivity Xiahan Zhou, Michael Sveiven, Drew A. Hall University of California, San Diego, La Jolla, CA, USA
More informationA Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury
A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury Garren Boggs, Hua Chen, Sridhar Sivapurapu ECE 6414 Final Presentation Outline Motivation System Overview Analog Front
More informationA 2-in-1 Temperature and Humidity Sensor Achieving 62 fj K 2 and 0.83 pj (%RH) 2
Session 22 Sensors and Integration A 2-in-1 Temperature and Humidity Sensor Achieving 62 fj K 2 and 0.83 pj (%RH) 2 Haowei Jiang, Chih-Cheng Huang, Matthew Chan, and Drew A. Hall University of California,
More informationA 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier
A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline Background Body voltage controlled
More informationIntegrated Microsystems Laboratory. Franco Maloberti
University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti franco.maloberti@unipv.it OUTLINE Introduction Managing the noise power budget Challenges of State-of-the-art
More informationA 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation
Y. Zu, C.- H. Chan, S.- W. Sin, S.- P. U, R.P. Martins, F. Maloberti: "A 35 fj 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self- Embedded Offset Cancellation"; IEEE Asian Solid-
More informationSigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC
Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Jinseok Koh Wireless Analog Technology Center Texas Instruments Inc. Dallas, TX Outline Fundamentals for ADCs Over-sampling and Noise
More informationA Mostly Digital Variable-Rate Continuous- Time ADC Modulator
A Mostly Digital Variable-Rate Continuous- Time ADC Modulator Gerry Taylor 1,2, Ian Galton 1 1 University of California at San Diego, La Jolla, CA 2 Analog Devices, San Diego, CA INTEGRATED SIGNAL PROCESSING
More informationArchitectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters
0 Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters F. Maloberti University of Pavia - Italy franco.maloberti@unipv.it 1 Introduction Summary Sigma-Delta
More informationSession 11 CMOS Biochips and Bioelectronics A Sub-1 µw Multiparameter Injectable BioMote for Continuous Alcohol Monitoring
Session 11 CMOS Biochips and Bioelectronics A Sub-1 µw Multiparameter Injectable BioMote for Continuous Alcohol Monitoring Haowei Jiang, Xiahan Zhou, Saurabh Kulkarni, Michael Uranian, Rajesh Seenivasan,
More informationAnalog to Digital Conversion
Analog to Digital Conversion Florian Erdinger Lehrstuhl für Schaltungstechnik und Simulation Technische Informatik der Uni Heidelberg VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg
More informationA Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation. Outline
A Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation Ashok Swaminathan,2, Kevin J. Wang, Ian Galton University of California, San Diego, CA 2 NextWave Broadband, San
More informationCMOS ADC & DAC Principles
CMOS ADC & DAC Principles Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 201 Table of contents Definitions Digital-to-analog converters Resistive Capacitive
More information9 Feedback and Control
9 Feedback and Control Due date: Tuesday, October 20 (midnight) Reading: none An important application of analog electronics, particularly in physics research, is the servomechanical control system. Here
More informationDesign of High-Speed Op-Amps for Signal Processing
Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS
More informationSummary Last Lecture
Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations
More informationEE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting
EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class
More informationLecture #6: Analog-to-Digital Converter
Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,
More informationSummary 185. Chapter 4
Summary This thesis describes the theory, design and realization of precision interface electronics for bridge transducers and thermocouples that require high accuracy, low noise, low drift and simultaneously,
More informationDesign of High Gain Low Voltage CMOS Comparator
Design of High Gain Low Voltage CMOS Comparator Shahid Khan 1 1 Rustomjee Academy for Global Careers Abstract: Comparators used in most of the analog circuits like analog to digital converters, switching
More informationLF411 Low Offset, Low Drift JFET Input Operational Amplifier
Low Offset, Low Drift JFET Input Operational Amplifier General Description These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input
More informationLecture 9, ANIK. Data converters 1
Lecture 9, ANIK Data converters 1 What did we do last time? Noise and distortion Understanding the simplest circuit noise Understanding some of the sources of distortion 502 of 530 What will we do today?
More informationLF442 Dual Low Power JFET Input Operational Amplifier
LF442 Dual Low Power JFET Input Operational Amplifier General Description The LF442 dual low power operational amplifiers provide many of the same AC characteristics as the industry standard LM1458 while
More information2011/12 Cellular IC design RF, Analog, Mixed-Mode
2011/12 Cellular IC design RF, Analog, Mixed-Mode Mohammed Abdulaziz, Mattias Andersson, Jonas Lindstrand, Xiaodong Liu, Anders Nejdel Ping Lu, Luca Fanori Martin Anderson, Lars Sundström, Pietro Andreani
More informationEE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.
EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:
More informationSelecting and Using High-Precision Digital-to-Analog Converters
Selecting and Using High-Precision Digital-to-Analog Converters Chad Steward DAC Design Section Leader Linear Technology Corporation Many applications, including precision instrumentation, industrial automation,
More informationOBSOLETE. High Performance, BiFET Operational Amplifiers AD542/AD544/AD547 REV. B
a FEATURES Ultralow Drift: 1 V/ C (AD547L) Low Offset Voltage: 0.25 mv (AD547L) Low Input Bias Currents: 25 pa max Low Quiescent Current: 1.5 ma Low Noise: 2 V p-p High Open Loop Gain: 110 db High Slew
More informationA 9.35-ENOB, 14.8 fj/conv.-step Fully- Passive Noise-Shaping SAR ADC
A 9.35-ENOB, 14.8 fj/conv.-step Fully- Passive Noise-Shaping SAR ADC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa Tokyo Institute of Technology Symposia on VLSI Technology and Circuits Outline Background
More informationCHAPTER. delta-sigma modulators 1.0
CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly
More informationNOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN
NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN 1.Introduction: CMOS Transimpedance Amplifier Avalanche photodiodes (APDs) are highly sensitive,
More informationLINEAR IC APPLICATIONS
1 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 1 (a) Why is R e in an emitter-coupled differential amplifier replaced by a constant current source? (b)
More informationOPERATIONAL AMPLIFIER PREPARED BY, PROF. CHIRAG H. RAVAL ASSISTANT PROFESSOR NIRMA UNIVRSITY
OPERATIONAL AMPLIFIER PREPARED BY, PROF. CHIRAG H. RAVAL ASSISTANT PROFESSOR NIRMA UNIVRSITY INTRODUCTION Op-Amp means Operational Amplifier. Operational stands for mathematical operation like addition,
More informationModulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies
A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.
More informationAn ECG Chopper Amplifier Achieving 0.92 NEF and 0.85 PEF with AC-coupled Inverter-Stacking for Noise Efficiency Enhancement
An ECG Chopper Amplifier Achieving 0.92 NEF and 0.85 PEF with AC-coupled Inverter-Stacking for Noise Efficiency Enhancement Somok Mondal and Drew A. Hall University of California, San Diego Outline Motivation
More informationInput Stage Concerns. APPLICATION NOTE 656 Design Trade-Offs for Single-Supply Op Amps
Maxim/Dallas > App Notes > AMPLIFIER AND COMPARATOR CIRCUITS Keywords: single-supply, op amps, amplifiers, design, trade-offs, operational amplifiers Apr 03, 2000 APPLICATION NOTE 656 Design Trade-Offs
More informationA 400 MHz 4.5 nw 63.8 dbm Sensitivity Wake-up Receiver Employing an Active Pseudo-Balun Envelope Detector
A 400 MHz 4.5 nw 63.8 dbm Sensitivity Wake-up Receiver Employing an Active Pseudo-Balun Envelope Detector Po-Han Peter Wang, Haowei Jiang, Li Gao, Pinar Sen, Young-Han Kim, Gabriel M. Rebeiz, Patrick P.
More informationReceiver Architecture
Receiver Architecture Receiver basics Channel selection why not at RF? BPF first or LNA first? Direct digitization of RF signal Receiver architectures Sub-sampling receiver noise problem Heterodyne receiver
More informationAnalog-to-Digital Converters
EE47 Lecture 3 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ
More informationA Pulse-Based CMOS Ultra-Wideband Transmitter for WPANs
A Pulse-Based CMOS Ultra-Wideband Transmitter for WPANs Murat Demirkan* Solid-State Circuits Research Laboratory University of California, Davis *Now with Agilent Technologies, Santa Clara, CA 03/20/2008
More informationSensors & Transducers Published by IFSA Publishing, S. L.,
Sensors & Transducers Published by IFSA Publishing, S. L., 208 http://www.sensorsportal.com Fully Differential Operation Amplifier Using Self Cascode MOSFET Structure for High Slew Rate Applications Kalpraj
More informationA 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction. Andrea Panigada, Ian Galton
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction Andrea Panigada, Ian Galton University of California at San Diego, La Jolla, CA INTEGRATED SIGNAL PROCESSING
More informationAn Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs
International Journal of Research in Engineering and Innovation Vol-1, Issue-6 (2017), 60-64 International Journal of Research in Engineering and Innovation (IJREI) journal home page: http://www.ijrei.com
More informationHigh Current, High Power OPERATIONAL AMPLIFIER
High Current, High Power OPERATIONAL AMPLIFIER FEATURES HIGH OUTPUT CURRENT: A WIDE POWER SUPPLY VOLTAGE: ±V to ±5V USER-SET CURRENT LIMIT SLEW RATE: V/µs FET INPUT: I B = pa max CLASS A/B OUTPUT STAGE
More information2. ADC Architectures and CMOS Circuits
/58 2. Architectures and CMOS Circuits Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es
More informationDesign of a MIMO System for Interference Reduction in a Laptop System. EECS 522 Final Project Group 1 Roland Florenz Maksym Kloka Ben Sutton
Design of a MIMO System for Interference Reduction in a Laptop System EECS 522 Final Project Group 1 Roland Florenz Maksym Kloka Ben Sutton Outline Motivation Block Diagram/Concept Introduction Component
More informationEXAM Amplifiers and Instrumentation (EE1C31)
DELFT UNIVERSITY OF TECHNOLOGY Faculty of Electrical Engineering, Mathematics and Computer Science EXAM Amplifiers and Instrumentation (EE1C31) April 18, 2017, 9.00-12.00 hr This exam consists of four
More information2. Single Stage OpAmps
/74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated
More informationDesign of Operational Amplifier in 45nm Technology
Design of Operational Amplifier in 45nm Technology Aman Kaushik ME Scholar Dept. of E&CE, NITTTR Chandigarh Abstract-This paper presents the designing and performance analysis of Operational Transconductance
More informationFig 1: The symbol for a comparator
INTRODUCTION A comparator is a device that compares two voltages or currents and switches its output to indicate which is larger. They are commonly used in devices such as They are commonly used in devices
More informationCHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE
CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined
More informationLinear IC s and applications
Questions and Solutions PART-A Unit-1 INTRODUCTION TO OP-AMPS 1. Explain data acquisition system Jan13 DATA ACQUISITION SYSYTEM BLOCK DIAGRAM: Input stage Intermediate stage Level shifting stage Output
More informationA 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California
A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1 Outline Background Chip Architecture
More informationOPERATIONAL AMPLIFIERS and FEEDBACK
Lab Notes A. La Rosa OPERATIONAL AMPLIFIERS and FEEDBACK 1. THE ROLE OF OPERATIONAL AMPLIFIERS A typical digital data acquisition system uses a transducer (sensor) to convert a physical property measurement
More informationDesign And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu
Design And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu Gireeja D. Amin Assistant Professor L. C. Institute of
More informationA Low-Power 6-b Integrating-Pipeline Hybrid Analog-to-Digital Converter
A Low-Power 6-b Integrating-Pipeline Hybrid Analog-to-Digital Converter Quentin Diduck, Martin Margala * Electrical and Computer Engineering Department 526 Computer Studies Bldg., PO Box 270231 University
More informationOp-Amp Simulation Part II
Op-Amp Simulation Part II EE/CS 5720/6720 This assignment continues the simulation and characterization of a simple operational amplifier. Turn in a copy of this assignment with answers in the appropriate
More informationSwitched-mode power supply control circuit
DESCRIPTION The /SE6 is a control circuit for use in switched-mode power supplies. It contains an internal temperature- compensated supply, PWM, sawtooth oscillator, overcurrent sense latch, and output
More informationDesign of Analog and Mixed Integrated Circuits and Systems Theory Exercises
102726 Design of nalog and Mixed Theory Exercises Francesc Serra Graells http://www.cnm.es/~pserra/uab/damics paco.serra@imb-cnm.csic.es 1 Introduction to the Design of nalog Integrated Circuits 1.1 The
More informationLow-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationPublication [P3] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Publication [P3] Copyright c 2006 IEEE. Reprinted, with permission, from Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 5-9 Feb. 2006, pp. 488 489. This
More informationThe Importance of Data Converter Static Specifications Don't Lose Sight of the Basics! by Walt Kester
TUTORIAL The Importance of Data Converter Static Specifications Don't Lose Sight of the Basics! INTRODUCTION by Walt Kester In the 1950s and 1960s, dc performance specifications such as integral nonlinearity,
More informationLF444 Quad Low Power JFET Input Operational Amplifier
LF444 Quad Low Power JFET Input Operational Amplifier General Description The LF444 quad low power operational amplifier provides many of the same AC characteristics as the industry standard LM148 while
More informationNPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering.
NPTEL Syllabus VLSI Data Conversion Circuits - Video course COURSE OUTLINE This course covers the analysis and design of CMOS Analog-to-Digital and Digital-to-Analog Converters,with about 7 design assigments.
More information2008/09 Advances in the mixed signal IC design group
2008/09 Advances in the mixed signal IC design group Mattias Andersson Mixed-Signal IC Design Department for Electrical and Information Technology Lund University 1 Mixed Signal IC Design Researchers Associate
More informationDesign of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications
RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication
More informationDimensions in inches (mm) .021 (0.527).035 (0.889) .016 (.406).020 (.508 ) .280 (7.112).330 (8.382) Figure 1. Typical application circuit.
IL Linear Optocoupler Dimensions in inches (mm) FEATURES Couples AC and DC signals.% Servo Linearity Wide Bandwidth, > khz High Gain Stability, ±.%/C Low Input-Output Capacitance Low Power Consumption,
More informationElectronics II Physics 3620 / 6620
Electronics II Physics 3620 / 6620 Feb 09, 2009 Part 1 Analog-to-Digital Converters (ADC) 2/8/2009 1 Why ADC? Digital Signal Processing is more popular Easy to implement, modify, Low cost Data from real
More informationBrushless DC motor controller
NE/SA7 DESCRIPTION The NE/SA/SE7 is a three-phase brushless DC motor controller with a microprocessor-compatible serial input data port; 8-bit monotonic digital-to-analog converter; PWM comparator; oscillator;
More informationOversampling Converters
Oversampling Converters Behzad Razavi Electrical Engineering Department University of California, Los Angeles Outline Basic Concepts First- and Second-Order Loops Effect of Circuit Nonidealities Cascaded
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationAnalog Electronic Circuits Code: EE-305-F
Analog Electronic Circuits Code: EE-305-F 1 INTRODUCTION Usually Called Op Amps Section -C Operational Amplifier An amplifier is a device that accepts a varying input signal and produces a similar output
More informationExperiment 1: Amplifier Characterization Spring 2019
Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using
More informationIJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 04, 2016 ISSN (online):
IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 04, 2016 ISSN (online): 2321-0613 Designing and FFT Analysis of Sigma Delta Converter using Spice Ritika Bathri 1 Prachi
More informationRELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE
RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE Mehdi Taghizadeh and Sirus Sadughi Department of Electrical Engineering, Science and Research Branch,
More informationGábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25
Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/25 Noise Intrinsic (inherent) noise: generated by random physical effects in the devices.
More informationEE247 Lecture 23. Advanced calibration techniques. Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC
EE247 Lecture 23 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Advanced calibration techniques Compensating inter-stage amplifier non-linearity Calibration via parallel
More informationLF444 Quad Low Power JFET Input Operational Amplifier
LF444 Quad Low Power JFET Input Operational Amplifier General Description The LF444 quad low power operational amplifier provides many of the same AC characteristics as the industry standard LM148 while
More informationA Compact, Low-Power Low- Jitter Digital PLL. Amr Fahim Qualcomm, Inc.
A Compact, Low-Power Low- Jitter Digital PLL Amr Fahim Qualcomm, Inc. 1 Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL
More informationLF155/LF156/LF355/LF356/LF357 JFET Input Operational Amplifiers
JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationADC0808/ADC Bit µp Compatible A/D Converters with 8-Channel Multiplexer
ADC0808/ADC0809 8-Bit µp Compatible A/D Converters with 8-Channel Multiplexer General Description The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital
More informationAdvanced Regulating Pulse Width Modulators
Advanced Regulating Pulse Width Modulators FEATURES Complete PWM Power Control Circuitry Uncommitted Outputs for Single-ended or Push-pull Applications Low Standby Current 8mA Typical Interchangeable with
More informationLow-output-impedance BiCMOS voltage buffer
Low-output-impedance BiCMOS voltage buffer Johan Bauwelinck, a) Wei Chen, Dieter Verhulst, Yves Martens, Peter Ossieur, Xing-Zhi Qiu, and Jan Vandewege Ghent University, INTEC/IMEC, Gent, 9000, Belgium
More informationImplementing a 5-bit Folding and Interpolating Analog to Digital Converter
Implementing a 5-bit Folding and Interpolating Analog to Digital Converter Zachary A Pfeffer (pfefferz@colorado.edu) Department of Electrical and Computer Engineering University of Colorado, Boulder CO
More informationA Digitally Enhanced 1.8-V 15-b 40- Msample/s CMOS Pipelined ADC
A Digitally Enhanced.8-V 5-b 4- Msample/s CMOS d ADC Eric Siragusa and Ian Galton University of California San Diego Now with Analog Devices San Diego California Outline Conventional PADC Example Digitally
More informationA single-slope 80MS/s ADC using two-step time-to-digital conversion
A single-slope 80MS/s ADC using two-step time-to-digital conversion The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published
More informationEE247 Lecture 24. EE247 Lecture 24
EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: -12:30pm-3:30pm- Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper
More informationOperational Amplifiers
Operational Amplifiers Table of contents 1. Design 1.1. The Differential Amplifier 1.2. Level Shifter 1.3. Power Amplifier 2. Characteristics 3. The Opamp without NFB 4. Linear Amplifiers 4.1. The Non-Inverting
More informationComparison between Analog and Digital Current To PWM Converter for Optical Readout Systems
Comparison between Analog and Digital Current To PWM Converter for Optical Readout Systems 1 Eun-Jung Yoon, 2 Kangyeob Park, 3* Won-Seok Oh 1, 2, 3 SoC Platform Research Center, Korea Electronics Technology
More informationMixed-Signal-Electronics
1 Mixed-Signal-Electronics PD Dr.-Ing. Stephan Henzler 2 Chapter 6 Nyquist Rate Analog-to-Digital Converters 3 Pipelined ADC 2 4 High-Speed ADC: Pipeline Processing Stephan Henzler Advanced Integrated
More informationAnalysis and Design of High Speed Low Power Comparator in ADC
Analysis and Design of High Speed Low Power Comparator in ADC 1 Abhishek Rai, 2 B Ananda Venkatesan 1 M.Tech Scholar, 2 Assistant professor Dept. of ECE, SRM University, Chennai 1 Abhishekfan1791@gmail.com,
More informationLF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier
LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed
More informationLF353 Wide Bandwidth Dual JFET Input Operational Amplifier
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage
More informationPhase-locked loop PIN CONFIGURATIONS
NE/SE DESCRIPTION The NE/SE is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 0MHz. As shown in the Block Diagram, the NE/SE consists of a VCO, limiter, phase comparator,
More informationHIGH POWER DUAL OPERATIONAL AMPLIFIER
MILPRF8 CERTIFIED M.S.KENNEDY CORP. HIGH POWER DUAL OPERATIONAL AMPLIFIER 707 Dey Road Liverpool, N.Y. 088 () 7067 FEATURES: Space Efficient Dual Power Amplifier Low Cost High oltage Operation: 0 Low Quiescent
More informationAnalysis and Design of High Speed Low Power Comparator in ADC
Analysis and Design of High Speed Low Power Comparator in ADC Yogesh Kumar M. Tech DCRUST (Sonipat) ABSTRACT: The fast growing electronics industry is pushing towards high speed low power analog to digital
More informationPHYS 536 The Golden Rules of Op Amps. Characteristics of an Ideal Op Amp
PHYS 536 The Golden Rules of Op Amps Introduction The purpose of this experiment is to illustrate the golden rules of negative feedback for a variety of circuits. These concepts permit you to create and
More informationMTJ based Random Number Generation and Analog-to-Digital Conversion Chris H. Kim University of Minnesota
MTJ based Random Number Generation and Analog-to-Digital Conversion Chris H. Kim University of Minnesota Workshop on the Future of Spintronics, June 5, 216 1 Switching Probability of an MTJ Parallel: Low
More information